XenonRecomp/thirdparty/capstone/tests/MC/AArch64/SME2/uvdot.s.yaml

test_cases:
  -
    input:
      bytes: [ 0x30, 0x00, 0x50, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"

  -
    input:
      bytes: [ 0x30, 0x00, 0x50, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"

  -
    input:
      bytes: [ 0x75, 0x45, 0x55, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"

  -
    input:
      bytes: [ 0x75, 0x45, 0x55, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"

  -
    input:
      bytes: [ 0xb7, 0x6d, 0x58, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"

  -
    input:
      bytes: [ 0xb7, 0x6d, 0x58, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"

  -
    input:
      bytes: [ 0xf7, 0x6f, 0x5f, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"

  -
    input:
      bytes: [ 0xf7, 0x6f, 0x5f, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"

  -
    input:
      bytes: [ 0x35, 0x0e, 0x50, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"

  -
    input:
      bytes: [ 0x35, 0x0e, 0x50, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"

  -
    input:
      bytes: [ 0x31, 0x04, 0x5e, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"

  -
    input:
      bytes: [ 0x31, 0x04, 0x5e, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"

  -
    input:
      bytes: [ 0x70, 0x46, 0x54, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"

  -
    input:
      bytes: [ 0x70, 0x46, 0x54, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"

  -
    input:
      bytes: [ 0xb0, 0x09, 0x52, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"

  -
    input:
      bytes: [ 0xb0, 0x09, 0x52, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"

  -
    input:
      bytes: [ 0x31, 0x48, 0x5a, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"

  -
    input:
      bytes: [ 0x31, 0x48, 0x5a, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"

  -
    input:
      bytes: [ 0xf5, 0x0a, 0x5e, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"

  -
    input:
      bytes: [ 0xf5, 0x0a, 0x5e, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"

  -
    input:
      bytes: [ 0x32, 0x65, 0x51, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"

  -
    input:
      bytes: [ 0x32, 0x65, 0x51, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"

  -
    input:
      bytes: [ 0xb7, 0x29, 0x5b, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"

  -
    input:
      bytes: [ 0xb7, 0x29, 0x5b, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"

  -
    input:
      bytes: [ 0x30, 0x80, 0x50, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"

  -
    input:
      bytes: [ 0x30, 0x80, 0x50, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"

  -
    input:
      bytes: [ 0x35, 0xc5, 0x55, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"

  -
    input:
      bytes: [ 0x35, 0xc5, 0x55, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"

  -
    input:
      bytes: [ 0xb7, 0xed, 0x58, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"

  -
    input:
      bytes: [ 0xb7, 0xed, 0x58, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"

  -
    input:
      bytes: [ 0xb7, 0xef, 0x5f, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"

  -
    input:
      bytes: [ 0xb7, 0xef, 0x5f, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"

  -
    input:
      bytes: [ 0x35, 0x8e, 0x50, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"

  -
    input:
      bytes: [ 0x35, 0x8e, 0x50, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"

  -
    input:
      bytes: [ 0x31, 0x84, 0x5e, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"

  -
    input:
      bytes: [ 0x31, 0x84, 0x5e, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"

  -
    input:
      bytes: [ 0x30, 0xc6, 0x54, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"

  -
    input:
      bytes: [ 0x30, 0xc6, 0x54, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"

  -
    input:
      bytes: [ 0xb0, 0x89, 0x52, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"

  -
    input:
      bytes: [ 0xb0, 0x89, 0x52, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"

  -
    input:
      bytes: [ 0x31, 0xc8, 0x5a, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"

  -
    input:
      bytes: [ 0x31, 0xc8, 0x5a, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"

  -
    input:
      bytes: [ 0xb5, 0x8a, 0x5e, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"

  -
    input:
      bytes: [ 0xb5, 0x8a, 0x5e, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"

  -
    input:
      bytes: [ 0x32, 0xe5, 0x51, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"

  -
    input:
      bytes: [ 0x32, 0xe5, 0x51, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"

  -
    input:
      bytes: [ 0xb7, 0xa9, 0x5b, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"

  -
    input:
      bytes: [ 0xb7, 0xa9, 0x5b, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"

  -
    input:
      bytes: [ 0x18, 0x88, 0xd0, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"

  -
    input:
      bytes: [ 0x18, 0x88, 0xd0, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"

  -
    input:
      bytes: [ 0x1d, 0xcd, 0xd5, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"

  -
    input:
      bytes: [ 0x1d, 0xcd, 0xd5, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"

  -
    input:
      bytes: [ 0x9f, 0xed, 0xd8, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]"

  -
    input:
      bytes: [ 0x9f, 0xed, 0xd8, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]"

  -
    input:
      bytes: [ 0x9f, 0xef, 0xdf, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]"

  -
    input:
      bytes: [ 0x9f, 0xef, 0xdf, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]"

  -
    input:
      bytes: [ 0x1d, 0x8e, 0xd0, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]"

  -
    input:
      bytes: [ 0x1d, 0x8e, 0xd0, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]"

  -
    input:
      bytes: [ 0x19, 0x8c, 0xde, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"

  -
    input:
      bytes: [ 0x19, 0x8c, 0xde, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"

  -
    input:
      bytes: [ 0x18, 0xce, 0xd4, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"

  -
    input:
      bytes: [ 0x18, 0xce, 0xd4, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"

  -
    input:
      bytes: [ 0x98, 0x89, 0xd2, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]"

  -
    input:
      bytes: [ 0x98, 0x89, 0xd2, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]"

  -
    input:
      bytes: [ 0x19, 0xc8, 0xda, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]"

  -
    input:
      bytes: [ 0x19, 0xc8, 0xda, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]"

  -
    input:
      bytes: [ 0x9d, 0x8a, 0xde, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]"

  -
    input:
      bytes: [ 0x9d, 0x8a, 0xde, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]"

  -
    input:
      bytes: [ 0x1a, 0xed, 0xd1, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"

  -
    input:
      bytes: [ 0x1a, 0xed, 0xd1, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"

  -
    input:
      bytes: [ 0x9f, 0xa9, 0xdb, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]"

  -
    input:
      bytes: [ 0x9f, 0xa9, 0xdb, 0xc1 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
    expected:
      insns:
        -
          asm_text: "uvdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]"