mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
221 lines
5.0 KiB
YAML
221 lines
5.0 KiB
YAML
![]() |
test_cases:
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input:
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bytes: [ 0x00, 0xa0, 0x5b, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "fcvtzu z0.h, p0/m, z0.h"
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input:
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bytes: [ 0x00, 0xa0, 0x5d, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "fcvtzu z0.s, p0/m, z0.h"
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input:
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bytes: [ 0x00, 0xa0, 0x9d, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "fcvtzu z0.s, p0/m, z0.s"
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input:
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bytes: [ 0x00, 0xa0, 0xd9, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "fcvtzu z0.s, p0/m, z0.d"
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-
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input:
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bytes: [ 0x00, 0xa0, 0x5f, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "fcvtzu z0.d, p0/m, z0.h"
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-
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input:
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bytes: [ 0x00, 0xa0, 0xdd, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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asm_text: "fcvtzu z0.d, p0/m, z0.s"
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input:
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bytes: [ 0x00, 0xa0, 0xdf, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "fcvtzu z0.d, p0/m, z0.d"
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input:
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bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "movprfx z5.d, p0/z, z7.d"
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input:
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bytes: [ 0x05, 0xa0, 0xdf, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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asm_text: "fcvtzu z5.d, p0/m, z0.d"
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input:
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bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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asm_text: "movprfx z5, z7"
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input:
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bytes: [ 0x05, 0xa0, 0xdf, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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asm_text: "fcvtzu z5.d, p0/m, z0.d"
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input:
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bytes: [ 0x00, 0xa0, 0x5b, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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asm_text: "fcvtzu z0.h, p0/m, z0.h"
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input:
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bytes: [ 0x00, 0xa0, 0x5d, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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asm_text: "fcvtzu z0.s, p0/m, z0.h"
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input:
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bytes: [ 0x00, 0xa0, 0x9d, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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asm_text: "fcvtzu z0.s, p0/m, z0.s"
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input:
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bytes: [ 0x00, 0xa0, 0xd9, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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asm_text: "fcvtzu z0.s, p0/m, z0.d"
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input:
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bytes: [ 0x00, 0xa0, 0x5f, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "fcvtzu z0.d, p0/m, z0.h"
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-
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input:
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bytes: [ 0x00, 0xa0, 0xdd, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "fcvtzu z0.d, p0/m, z0.s"
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-
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input:
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bytes: [ 0x00, 0xa0, 0xdf, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "fcvtzu z0.d, p0/m, z0.d"
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input:
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bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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asm_text: "movprfx z5.d, p0/z, z7.d"
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-
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input:
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bytes: [ 0x05, 0xa0, 0xdf, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "fcvtzu z5.d, p0/m, z0.d"
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input:
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bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "movprfx z5, z7"
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-
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input:
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bytes: [ 0x05, 0xa0, 0xdf, 0x65 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "fcvtzu z5.d, p0/m, z0.d"
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