mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
101 lines
2.4 KiB
YAML
101 lines
2.4 KiB
YAML
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test_cases:
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-
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input:
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bytes: [ 0x00, 0xe0, 0x80, 0xa5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "ldnt1d { z0.d }, p0/z, [x0]"
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-
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input:
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bytes: [ 0x00, 0xe0, 0x80, 0xa5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "ldnt1d { z0.d }, p0/z, [x0]"
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-
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input:
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bytes: [ 0xb7, 0xed, 0x88, 0xa5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl]"
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-
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input:
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bytes: [ 0x55, 0xf5, 0x87, 0xa5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "ldnt1d { z21.d }, p5/z, [x10, #7, mul vl]"
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-
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input:
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bytes: [ 0x00, 0xc0, 0x80, 0xa5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]"
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-
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input:
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bytes: [ 0x00, 0xe0, 0x80, 0xa5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "ldnt1d { z0.d }, p0/z, [x0]"
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-
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input:
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bytes: [ 0x00, 0xe0, 0x80, 0xa5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "ldnt1d { z0.d }, p0/z, [x0]"
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-
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input:
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bytes: [ 0xb7, 0xed, 0x88, 0xa5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl]"
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-
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input:
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bytes: [ 0x55, 0xf5, 0x87, 0xa5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "ldnt1d { z21.d }, p5/z, [x10, #7, mul vl]"
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-
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input:
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bytes: [ 0x00, 0xc0, 0x80, 0xa5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]"
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