mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
101 lines
2.4 KiB
YAML
101 lines
2.4 KiB
YAML
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test_cases:
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-
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input:
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bytes: [ 0x00, 0x40, 0x00, 0xe5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
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expected:
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insns:
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-
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asm_text: "st1w { z0.q }, p0, [x0, x0, lsl #2]"
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-
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input:
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bytes: [ 0x55, 0x55, 0x15, 0xe5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
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expected:
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insns:
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-
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asm_text: "st1w { z21.q }, p5, [x10, x21, lsl #2]"
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-
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input:
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bytes: [ 0xb7, 0x4d, 0x08, 0xe5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
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expected:
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insns:
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-
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asm_text: "st1w { z23.q }, p3, [x13, x8, lsl #2]"
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-
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input:
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bytes: [ 0xb7, 0x4d, 0x08, 0xe5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
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expected:
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insns:
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-
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asm_text: "st1w { z23.q }, p3, [x13, x8, lsl #2]"
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-
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input:
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bytes: [ 0x00, 0xe0, 0x00, 0xe5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
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expected:
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insns:
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-
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asm_text: "st1w { z0.q }, p0, [x0]"
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-
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input:
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bytes: [ 0x00, 0xe0, 0x00, 0xe5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
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expected:
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insns:
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-
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asm_text: "st1w { z0.q }, p0, [x0]"
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-
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input:
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bytes: [ 0x55, 0xf5, 0x05, 0xe5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
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expected:
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insns:
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-
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asm_text: "st1w { z21.q }, p5, [x10, #5, mul vl]"
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-
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input:
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bytes: [ 0xb7, 0xed, 0x08, 0xe5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
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expected:
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insns:
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-
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asm_text: "st1w { z23.q }, p3, [x13, #-8, mul vl]"
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-
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input:
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bytes: [ 0xff, 0xff, 0x0f, 0xe5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
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expected:
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insns:
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-
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asm_text: "st1w { z31.q }, p7, [sp, #-1, mul vl]"
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-
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input:
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bytes: [ 0xff, 0xff, 0x0f, 0xe5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
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expected:
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insns:
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-
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asm_text: "st1w { z31.q }, p7, [sp, #-1, mul vl]"
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