mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
104 lines
4.0 KiB
TableGen
104 lines
4.0 KiB
TableGen
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// Capstone definitions fix for X86 LLVM instructions.
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let Defs = [EFLAGS] in
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def INT1 : I<0xf1, RawFrm, (outs), (ins), "int1", []>;
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def FSETPM : I<0xDB, MRM_E4, (outs), (ins), "fsetpm", []>;
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// Capstone: comment out below lines for X86 Reduce mode
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/*
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// X87 Floating Point Stack.
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include "X86InstrFPStack.td"
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// SIMD support (SSE, MMX and AVX)
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include "X86InstrFragmentsSIMD.td"
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// FMA - Fused Multiply-Add support (requires FMA)
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include "X86InstrFMA.td"
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// XOP
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include "X86InstrXOP.td"
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// SSE, MMX and 3DNow! vector support.
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include "X86InstrSSE.td"
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include "X86InstrAVX512.td"
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include "X86InstrMMX.td"
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include "X86Instr3DNow.td"
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// MPX instructions
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include "X86InstrMPX.td"
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//include "X86InstrTSX.td"
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include "X86InstrSGX.td"
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// Various unary fpstack operations default to operating on ST1.
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// For example, "fxch" -> "fxch %st(1)"
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def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
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def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>;
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def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
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def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
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def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>;
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def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
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def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
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def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
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def : InstAlias<"fxch", (XCH_F ST1), 0>;
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def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
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def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
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def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
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def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
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def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
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def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
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def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
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def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
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// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
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// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
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// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
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// gas.
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multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
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def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
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(Inst RST:$op), EmitAlias>;
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def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
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(Inst ST0), EmitAlias>;
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}
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defm : FpUnaryAlias<"fadd", ADD_FST0r>;
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defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
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defm : FpUnaryAlias<"fsub", SUB_FST0r>;
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defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
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defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
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defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
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defm : FpUnaryAlias<"fmul", MUL_FST0r>;
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defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
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defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
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defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
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defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
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defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
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defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
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defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
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defm : FpUnaryAlias<"fcompi", COM_FIPr>;
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defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
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// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
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// commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
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// solely because gas supports it.
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def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
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def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
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def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
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def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
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def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
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def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
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def : InstAlias<"fnstsw" , (FNSTSW16r), 0>;
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// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas,
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// which supports this due to an old AMD documentation bug when 64-bit mode was
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// created.
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def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
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(MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
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def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
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(MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
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*/
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