mirror of
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351 lines
13 KiB
C
351 lines
13 KiB
C
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an AArch64 MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
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#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <capstone/platform.h>
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#include "AArch64Mapping.h"
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#include "../../MCInst.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MCInstPrinter.h"
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#include "../../SStream.h"
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#include "../../utils.h"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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#define CHAR(c) #c[0]
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void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
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void printRegName(SStream *OS, unsigned Reg);
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void printRegNameAlt(SStream *OS, unsigned Reg, unsigned AltIdx);
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// Autogenerated by tblgen.
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const char *getRegName(unsigned Reg);
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bool printSysAlias(MCInst *MI, SStream *O);
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bool printSyspAlias(MCInst *MI, SStream *O);
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bool printRangePrefetchAlias(MCInst *MI, SStream *O, const char *Annot);
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// Operand printers
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void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
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void printImm(MCInst *MI, unsigned OpNo, SStream *O);
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void printImmHex(MCInst *MI, unsigned OpNo, SStream *O);
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#define DECLARE_printSImm(Size) \
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void CONCAT(printSImm, Size)(MCInst * MI, unsigned OpNo, SStream *O);
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DECLARE_printSImm(16);
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DECLARE_printSImm(8);
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#define DECLARE_printImmSVE(T) void CONCAT(printImmSVE, T)(T Val, SStream * O);
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DECLARE_printImmSVE(int16_t);
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DECLARE_printImmSVE(int8_t);
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DECLARE_printImmSVE(int64_t);
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DECLARE_printImmSVE(int32_t);
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DECLARE_printImmSVE(uint16_t);
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DECLARE_printImmSVE(uint8_t);
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DECLARE_printImmSVE(uint64_t);
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DECLARE_printImmSVE(uint32_t);
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void printPostIncOperand(MCInst *MI, unsigned OpNo, unsigned Imm, SStream *O);
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#define DEFINE_printPostIncOperand(Amount) \
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static inline void CONCAT(printPostIncOperand, Amount)( \
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MCInst * MI, unsigned OpNo, SStream *O) \
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{ \
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add_cs_detail(MI, \
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CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
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OpNo, Amount); \
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printPostIncOperand(MI, OpNo, Amount, O); \
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}
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DEFINE_printPostIncOperand(64);
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DEFINE_printPostIncOperand(32);
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DEFINE_printPostIncOperand(16);
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DEFINE_printPostIncOperand(8);
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DEFINE_printPostIncOperand(1);
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DEFINE_printPostIncOperand(4);
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DEFINE_printPostIncOperand(2);
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DEFINE_printPostIncOperand(48);
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DEFINE_printPostIncOperand(24);
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DEFINE_printPostIncOperand(3);
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DEFINE_printPostIncOperand(12);
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DEFINE_printPostIncOperand(6);
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void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O);
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void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O);
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void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O);
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#define DECLARE_printLogicalImm(T) \
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void CONCAT(printLogicalImm, T)(MCInst * MI, unsigned OpNum, \
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SStream *O);
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DECLARE_printLogicalImm(int64_t);
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DECLARE_printLogicalImm(int32_t);
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DECLARE_printLogicalImm(int8_t);
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DECLARE_printLogicalImm(int16_t);
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void printShifter(MCInst *MI, unsigned OpNum, SStream *O);
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void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O);
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void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O);
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void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O);
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void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
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unsigned Width);
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void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
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unsigned Width);
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#define DEFINE_printMemExtend(SrcRegKind, Width) \
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static inline void CONCAT(printMemExtend, CONCAT(SrcRegKind, Width))( \
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MCInst * MI, unsigned OpNum, SStream *O) \
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{ \
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add_cs_detail( \
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MI, \
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CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
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Width), \
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OpNum, CHAR(SrcRegKind), Width); \
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printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
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}
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DEFINE_printMemExtend(w, 8);
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DEFINE_printMemExtend(x, 8);
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DEFINE_printMemExtend(w, 64);
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DEFINE_printMemExtend(x, 64);
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DEFINE_printMemExtend(w, 16);
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DEFINE_printMemExtend(x, 16);
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DEFINE_printMemExtend(w, 128);
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DEFINE_printMemExtend(x, 128);
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DEFINE_printMemExtend(w, 32);
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DEFINE_printMemExtend(x, 32);
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#define DECLARE_printRegWithShiftExtend(SignedExtend, ExtWidth, SrcRegKind, \
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Suffix) \
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void CONCAT(printRegWithShiftExtend, \
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CONCAT(SignedExtend, \
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CONCAT(ExtWidth, CONCAT(SrcRegKind, Suffix))))( \
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MCInst * MI, unsigned OpNum, SStream *O);
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DECLARE_printRegWithShiftExtend(false, 8, x, d);
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DECLARE_printRegWithShiftExtend(true, 8, w, d);
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DECLARE_printRegWithShiftExtend(false, 8, w, d);
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DECLARE_printRegWithShiftExtend(false, 8, x, 0);
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DECLARE_printRegWithShiftExtend(true, 8, w, s);
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DECLARE_printRegWithShiftExtend(false, 8, w, s);
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DECLARE_printRegWithShiftExtend(false, 64, x, d);
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DECLARE_printRegWithShiftExtend(true, 64, w, d);
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DECLARE_printRegWithShiftExtend(false, 64, w, d);
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DECLARE_printRegWithShiftExtend(false, 64, x, 0);
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DECLARE_printRegWithShiftExtend(true, 64, w, s);
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DECLARE_printRegWithShiftExtend(false, 64, w, s);
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DECLARE_printRegWithShiftExtend(false, 16, x, d);
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DECLARE_printRegWithShiftExtend(true, 16, w, d);
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DECLARE_printRegWithShiftExtend(false, 16, w, d);
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DECLARE_printRegWithShiftExtend(false, 16, x, 0);
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DECLARE_printRegWithShiftExtend(true, 16, w, s);
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DECLARE_printRegWithShiftExtend(false, 16, w, s);
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DECLARE_printRegWithShiftExtend(false, 32, x, d);
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DECLARE_printRegWithShiftExtend(true, 32, w, d);
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DECLARE_printRegWithShiftExtend(false, 32, w, d);
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DECLARE_printRegWithShiftExtend(false, 32, x, 0);
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DECLARE_printRegWithShiftExtend(true, 32, w, s);
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DECLARE_printRegWithShiftExtend(false, 32, w, s);
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DECLARE_printRegWithShiftExtend(false, 8, x, s);
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DECLARE_printRegWithShiftExtend(false, 16, x, s);
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DECLARE_printRegWithShiftExtend(false, 32, x, s);
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DECLARE_printRegWithShiftExtend(false, 64, x, s);
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DECLARE_printRegWithShiftExtend(false, 128, x, 0);
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void printCondCode(MCInst *MI, unsigned OpNum, SStream *O);
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void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O);
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void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
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SStream *O);
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void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
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void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
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#define DEFINE_printUImm12Offset(Scale) \
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static inline void CONCAT(printUImm12Offset, Scale)( \
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MCInst * MI, unsigned OpNum, SStream *O) \
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{ \
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add_cs_detail(MI, \
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CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
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OpNum, Scale); \
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printUImm12Offset(MI, OpNum, Scale, O); \
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}
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DEFINE_printUImm12Offset(1);
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DEFINE_printUImm12Offset(8);
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DEFINE_printUImm12Offset(2);
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DEFINE_printUImm12Offset(16);
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DEFINE_printUImm12Offset(4);
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void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O);
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#define DECLARE_printImmScale(Scale) \
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void CONCAT(printImmScale, Scale)(MCInst * MI, unsigned OpNum, \
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SStream *O);
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DECLARE_printImmScale(8);
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DECLARE_printImmScale(2);
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DECLARE_printImmScale(4);
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DECLARE_printImmScale(16);
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DECLARE_printImmScale(32);
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DECLARE_printImmScale(3);
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#define DECLARE_printImmRangeScale(Scale, Offset) \
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void CONCAT(printImmRangeScale, CONCAT(Scale, Offset))( \
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MCInst * MI, unsigned OpNum, SStream *O);
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DECLARE_printImmRangeScale(2, 1);
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DECLARE_printImmRangeScale(4, 3);
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#define DECLARE_printPrefetchOp(IsSVEPrefetch) \
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void CONCAT(printPrefetchOp, \
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IsSVEPrefetch)(MCInst * MI, unsigned OpNum, SStream *O);
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DECLARE_printPrefetchOp(true);
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DECLARE_printPrefetchOp(false);
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void printRPRFMOperand(MCInst *MI, unsigned OpNum, SStream *O);
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void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O);
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void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O);
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void printVectorList(MCInst *MI, unsigned OpNum, SStream *O,
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const char *LayoutSuffix);
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void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O);
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/// (i.e. attached to the instruction rather than the registers).
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/// Print a list of vector registers where the type suffix is implicit
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void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O);
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#define DECLARE_printTypedVectorList(NumLanes, LaneKind) \
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void CONCAT(printTypedVectorList, CONCAT(NumLanes, LaneKind))( \
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MCInst * MI, unsigned OpNum, SStream *O);
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DECLARE_printTypedVectorList(0, b);
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DECLARE_printTypedVectorList(0, d);
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DECLARE_printTypedVectorList(0, h);
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DECLARE_printTypedVectorList(0, s);
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DECLARE_printTypedVectorList(0, q);
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DECLARE_printTypedVectorList(16, b);
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DECLARE_printTypedVectorList(1, d);
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DECLARE_printTypedVectorList(2, d);
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DECLARE_printTypedVectorList(2, s);
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DECLARE_printTypedVectorList(4, h);
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DECLARE_printTypedVectorList(4, s);
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DECLARE_printTypedVectorList(8, b);
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DECLARE_printTypedVectorList(8, h);
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DECLARE_printTypedVectorList(0, 0);
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#define DECLARE_printVectorIndex(Scale) \
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void CONCAT(printVectorIndex, Scale)(MCInst * MI, unsigned OpNum, \
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SStream *O);
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DECLARE_printVectorIndex(1);
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DECLARE_printVectorIndex(8);
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void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
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SStream *O);
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void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O);
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void printBarriernXSOption(MCInst *MI, unsigned OpNum, SStream *O);
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void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
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void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
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void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O);
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void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O);
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#define DECLARE_printPredicateAsCounter(EltSize) \
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void CONCAT(printPredicateAsCounter, \
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EltSize)(MCInst * MI, unsigned OpNum, SStream *O);
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DECLARE_printPredicateAsCounter(8);
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DECLARE_printPredicateAsCounter(64);
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DECLARE_printPredicateAsCounter(16);
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DECLARE_printPredicateAsCounter(32);
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DECLARE_printPredicateAsCounter(0);
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#define DECLARE_printGPRSeqPairsClassOperand(size) \
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void CONCAT(printGPRSeqPairsClassOperand, \
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size)(MCInst * MI, unsigned OpNum, SStream *O);
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DECLARE_printGPRSeqPairsClassOperand(32);
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DECLARE_printGPRSeqPairsClassOperand(64);
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#define DECLARE_printImm8OptLsl(T) \
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void CONCAT(printImm8OptLsl, T)(MCInst * MI, unsigned OpNum, \
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SStream *O);
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DECLARE_printImm8OptLsl(int16_t);
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DECLARE_printImm8OptLsl(int8_t);
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DECLARE_printImm8OptLsl(int64_t);
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DECLARE_printImm8OptLsl(int32_t);
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DECLARE_printImm8OptLsl(uint16_t);
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DECLARE_printImm8OptLsl(uint8_t);
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DECLARE_printImm8OptLsl(uint64_t);
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DECLARE_printImm8OptLsl(uint32_t);
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#define DECLARE_printSVELogicalImm(T) \
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void CONCAT(printSVELogicalImm, T)(MCInst * MI, unsigned OpNum, \
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SStream *O);
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DECLARE_printSVELogicalImm(int16_t);
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DECLARE_printSVELogicalImm(int32_t);
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DECLARE_printSVELogicalImm(int64_t);
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void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O);
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void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O);
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#define DECLARE_printMatrixTileVector(IsVertical) \
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void CONCAT(printMatrixTileVector, \
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IsVertical)(MCInst * MI, unsigned OpNum, SStream *O);
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DECLARE_printMatrixTileVector(0);
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DECLARE_printMatrixTileVector(1);
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void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O);
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#define DECLARE_printMatrix(EltSize) \
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void CONCAT(printMatrix, EltSize)(MCInst * MI, unsigned OpNum, \
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SStream *O);
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DECLARE_printMatrix(64);
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DECLARE_printMatrix(32);
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DECLARE_printMatrix(16);
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DECLARE_printMatrix(0);
|
||
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|
|
||
|
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void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O);
|
||
|
|
#define DECLARE_printSVERegOp(char) \
|
||
|
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void CONCAT(printSVERegOp, char)(MCInst * MI, unsigned OpNum, \
|
||
|
|
SStream *O);
|
||
|
|
DECLARE_printSVERegOp(b);
|
||
|
|
DECLARE_printSVERegOp(d);
|
||
|
|
DECLARE_printSVERegOp(h);
|
||
|
|
DECLARE_printSVERegOp(s);
|
||
|
|
DECLARE_printSVERegOp(0);
|
||
|
|
DECLARE_printSVERegOp(q);
|
||
|
|
|
||
|
|
void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O);
|
||
|
|
void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O);
|
||
|
|
void printSyspXzrPair(MCInst *MI, unsigned OpNum, SStream *O);
|
||
|
|
#define DECLARE_printZPRasFPR(Width) \
|
||
|
|
void CONCAT(printZPRasFPR, Width)(MCInst * MI, unsigned OpNum, \
|
||
|
|
SStream *O);
|
||
|
|
DECLARE_printZPRasFPR(8);
|
||
|
|
DECLARE_printZPRasFPR(64);
|
||
|
|
DECLARE_printZPRasFPR(16);
|
||
|
|
DECLARE_printZPRasFPR(32);
|
||
|
|
DECLARE_printZPRasFPR(128);
|
||
|
|
|
||
|
|
#define DECLARE_printExactFPImm(ImmIs0, ImmIs1) \
|
||
|
|
void CONCAT(printExactFPImm, CONCAT(ImmIs0, ImmIs1))( \
|
||
|
|
MCInst * MI, unsigned OpNum, SStream *O);
|
||
|
|
DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_one);
|
||
|
|
DECLARE_printExactFPImm(AArch64ExactFPImm_zero, AArch64ExactFPImm_one);
|
||
|
|
DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_two);
|
||
|
|
|
||
|
|
#define DECLARE_printMatrixIndex(Scale) \
|
||
|
|
void CONCAT(printMatrixIndex, Scale)(MCInst * MI, unsigned OpNum, \
|
||
|
|
SStream *O);
|
||
|
|
DECLARE_printMatrixIndex(8);
|
||
|
|
DECLARE_printMatrixIndex(0);
|
||
|
|
DECLARE_printMatrixIndex(1);
|
||
|
|
|
||
|
|
// end namespace llvm
|
||
|
|
|
||
|
|
#endif // LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
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