mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
171 lines
6.3 KiB
YAML
171 lines
6.3 KiB
YAML
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test_cases:
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input:
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bytes: [ 0xa0, 0x08, 0x41, 0xf3, 0xa0, 0x08, 0x51, 0xf3, 0xa0, 0x08, 0x61, 0xf3, 0xa0, 0x08, 0x71, 0xf3, 0xa1, 0x0d, 0x60, 0xf2, 0xe2, 0x08, 0x40, 0xf3, 0xe2, 0x08, 0x50, 0xf3, 0xe2, 0x08, 0x60, 0xf3, 0xe2, 0x08, 0x70, 0xf3, 0xe2, 0x0d, 0x60, 0xf2, 0x25, 0xd8, 0x0d, 0xf3, 0x26, 0xe8, 0x1e, 0xf3, 0x27, 0xf8, 0x2f, 0xf3, 0xa8, 0x08, 0x70, 0xf3, 0xa9, 0x1d, 0x61, 0xf2, 0x64, 0x28, 0x02, 0xf3, 0x62, 0x48, 0x14, 0xf3, 0x60, 0x68, 0x26, 0xf3, 0x4e, 0x88, 0x38, 0xf3, 0x4c, 0xad, 0x2a, 0xf2, 0xa0, 0x02, 0xc1, 0xf2, 0xa0, 0x02, 0xd1, 0xf2, 0xa0, 0x02, 0xe1, 0xf2, 0xa0, 0x02, 0xc1, 0xf3, 0xa0, 0x02, 0xd1, 0xf3, 0xa0, 0x02, 0xe1, 0xf3, 0xa2, 0x03, 0xc0, 0xf2, 0xa2, 0x03, 0xd0, 0xf2, 0xa2, 0x03, 0xe0, 0xf2, 0xa2, 0x03, 0xc0, 0xf3, 0xa2, 0x03, 0xd0, 0xf3, 0xa2, 0x03, 0xe0, 0xf3, 0xa1, 0x02, 0x40, 0xf2, 0xa1, 0x02, 0x50, 0xf2, 0xa1, 0x02, 0x60, 0xf2, 0xa1, 0x02, 0x40, 0xf3, 0xa1, 0x02, 0x50, 0xf3, 0xa1, 0x02, 0x60, 0xf3, 0xe2, 0x02, 0x40, 0xf2, 0xe2, 0x02, 0x50, 0xf2, 0xe2, 0x02, 0x60, 0xf2, 0xb1, 0x02, 0x40, 0xf2, 0xb1, 0x02, 0x50, 0xf2, 0xb1, 0x02, 0x60, 0xf2, 0xb1, 0x02, 0x70, 0xf2, 0xb1, 0x02, 0x40, 0xf3, 0xb1, 0x02, 0x50, 0xf3, 0xb1, 0x02, 0x60, 0xf3, 0xb1, 0x02, 0x70, 0xf3, 0xf2, 0x02, 0x40, 0xf2, 0xf2, 0x02, 0x50, 0xf2, 0xf2, 0x02, 0x60, 0xf2, 0xf2, 0x02, 0x70, 0xf2, 0xf2, 0x02, 0x40, 0xf3, 0xf2, 0x02, 0x50, 0xf3, 0xf2, 0x02, 0x60, 0xf3, 0xf2, 0x02, 0x70, 0xf3, 0xa2, 0x06, 0xc0, 0xf2, 0xa2, 0x06, 0xd0, 0xf2, 0xa2, 0x06, 0xe0, 0xf2, 0xa2, 0x06, 0xc0, 0xf3, 0xa2, 0x06, 0xd0, 0xf3, 0xa2, 0x06, 0xe0, 0xf3, 0x28, 0xb2, 0x0b, 0xf2, 0x27, 0xc2, 0x1c, 0xf2, 0x26, 0xd2, 0x2d, 0xf2, 0x25, 0xe2, 0x0e, 0xf3, 0x24, 0xf2, 0x1f, 0xf3, 0xa3, 0x02, 0x60, 0xf3, 0x68, 0x22, 0x02, 0xf2, 0x66, 0x42, 0x14, 0xf2, 0x64, 0x62, 0x26, 0xf2, 0x62, 0x82, 0x08, 0xf3, 0x60, 0xa2, 0x1a, 0xf3, 0x4e, 0xc2, 0x2c, 0xf3, 0x05, 0xc3, 0x8c, 0xf2, 0x01, 0xe3, 0x9e, 0xf2, 0x82, 0x03, 0xe0, 0xf2, 0x05, 0xc3, 0x8c, 0xf3, 0x01, 0xe3, 0x9e, 0xf3, 0x82, 0x03, 0xe0, 0xf3 ]
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arch: "CS_ARCH_ARM"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
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expected:
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insns:
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asm_text: "vsub.i8 d16, d17, d16"
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asm_text: "vsub.i16 d16, d17, d16"
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asm_text: "vsub.i32 d16, d17, d16"
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asm_text: "vsub.i64 d16, d17, d16"
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asm_text: "vsub.f32 d16, d16, d17"
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asm_text: "vsub.i8 q8, q8, q9"
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asm_text: "vsub.i16 q8, q8, q9"
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asm_text: "vsub.i32 q8, q8, q9"
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asm_text: "vsub.i64 q8, q8, q9"
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asm_text: "vsub.f32 q8, q8, q9"
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asm_text: "vsub.i8 d13, d13, d21"
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asm_text: "vsub.i16 d14, d14, d22"
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asm_text: "vsub.i32 d15, d15, d23"
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asm_text: "vsub.i64 d16, d16, d24"
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asm_text: "vsub.f32 d17, d17, d25"
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asm_text: "vsub.i8 q1, q1, q10"
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asm_text: "vsub.i16 q2, q2, q9"
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asm_text: "vsub.i32 q3, q3, q8"
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asm_text: "vsub.i64 q4, q4, q7"
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asm_text: "vsub.f32 q5, q5, q6"
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asm_text: "vsubl.s8 q8, d17, d16"
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asm_text: "vsubl.s16 q8, d17, d16"
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asm_text: "vsubl.s32 q8, d17, d16"
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asm_text: "vsubl.u8 q8, d17, d16"
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asm_text: "vsubl.u16 q8, d17, d16"
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asm_text: "vsubl.u32 q8, d17, d16"
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asm_text: "vsubw.s8 q8, q8, d18"
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asm_text: "vsubw.s16 q8, q8, d18"
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asm_text: "vsubw.s32 q8, q8, d18"
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asm_text: "vsubw.u8 q8, q8, d18"
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asm_text: "vsubw.u16 q8, q8, d18"
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asm_text: "vsubw.u32 q8, q8, d18"
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asm_text: "vhsub.s8 d16, d16, d17"
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asm_text: "vhsub.s16 d16, d16, d17"
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asm_text: "vhsub.s32 d16, d16, d17"
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asm_text: "vhsub.u8 d16, d16, d17"
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asm_text: "vhsub.u16 d16, d16, d17"
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asm_text: "vhsub.u32 d16, d16, d17"
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asm_text: "vhsub.s8 q8, q8, q9"
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asm_text: "vhsub.s16 q8, q8, q9"
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asm_text: "vhsub.s32 q8, q8, q9"
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asm_text: "vqsub.s8 d16, d16, d17"
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asm_text: "vqsub.s16 d16, d16, d17"
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asm_text: "vqsub.s32 d16, d16, d17"
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asm_text: "vqsub.s64 d16, d16, d17"
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asm_text: "vqsub.u8 d16, d16, d17"
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asm_text: "vqsub.u16 d16, d16, d17"
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asm_text: "vqsub.u32 d16, d16, d17"
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asm_text: "vqsub.u64 d16, d16, d17"
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asm_text: "vqsub.s8 q8, q8, q9"
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asm_text: "vqsub.s16 q8, q8, q9"
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asm_text: "vqsub.s32 q8, q8, q9"
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asm_text: "vqsub.s64 q8, q8, q9"
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asm_text: "vqsub.u8 q8, q8, q9"
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asm_text: "vqsub.u16 q8, q8, q9"
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asm_text: "vqsub.u32 q8, q8, q9"
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asm_text: "vqsub.u64 q8, q8, q9"
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asm_text: "vsubhn.i16 d16, q8, q9"
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asm_text: "vsubhn.i32 d16, q8, q9"
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asm_text: "vsubhn.i64 d16, q8, q9"
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asm_text: "vrsubhn.i16 d16, q8, q9"
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asm_text: "vrsubhn.i32 d16, q8, q9"
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asm_text: "vrsubhn.i64 d16, q8, q9"
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asm_text: "vhsub.s8 d11, d11, d24"
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asm_text: "vhsub.s16 d12, d12, d23"
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asm_text: "vhsub.s32 d13, d13, d22"
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asm_text: "vhsub.u8 d14, d14, d21"
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asm_text: "vhsub.u16 d15, d15, d20"
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asm_text: "vhsub.u32 d16, d16, d19"
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asm_text: "vhsub.s8 q1, q1, q12"
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asm_text: "vhsub.s16 q2, q2, q11"
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asm_text: "vhsub.s32 q3, q3, q10"
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asm_text: "vhsub.u8 q4, q4, q9"
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asm_text: "vhsub.u16 q5, q5, q8"
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asm_text: "vhsub.u32 q6, q6, q7"
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asm_text: "vsubw.s8 q6, q6, d5"
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asm_text: "vsubw.s16 q7, q7, d1"
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asm_text: "vsubw.s32 q8, q8, d2"
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asm_text: "vsubw.u8 q6, q6, d5"
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asm_text: "vsubw.u16 q7, q7, d1"
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asm_text: "vsubw.u32 q8, q8, d2"
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