mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
137 lines
5.1 KiB
YAML
137 lines
5.1 KiB
YAML
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test_cases:
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input:
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bytes: [ 0x41, 0xef, 0xa0, 0x08, 0x51, 0xef, 0xa0, 0x08, 0x71, 0xef, 0xa0, 0x08, 0x61, 0xef, 0xa0, 0x08, 0x40, 0xef, 0xa1, 0x0d, 0x40, 0xef, 0xe2, 0x0d, 0xc1, 0xef, 0xa0, 0x00, 0xd1, 0xef, 0xa0, 0x00, 0xe1, 0xef, 0xa0, 0x00, 0xc1, 0xff, 0xa0, 0x00, 0xd1, 0xff, 0xa0, 0x00, 0xe1, 0xff, 0xa0, 0x00, 0xc0, 0xef, 0xa2, 0x01, 0xd0, 0xef, 0xa2, 0x01, 0xe0, 0xef, 0xa2, 0x01, 0xc0, 0xff, 0xa2, 0x01, 0xd0, 0xff, 0xa2, 0x01, 0xe0, 0xff, 0xa2, 0x01, 0x40, 0xef, 0xa1, 0x00, 0x50, 0xef, 0xa1, 0x00, 0x60, 0xef, 0xa1, 0x00, 0x40, 0xff, 0xa1, 0x00, 0x50, 0xff, 0xa1, 0x00, 0x60, 0xff, 0xa1, 0x00, 0x40, 0xef, 0xe2, 0x00, 0x50, 0xef, 0xe2, 0x00, 0x60, 0xef, 0xe2, 0x00, 0x40, 0xff, 0xe2, 0x00, 0x50, 0xff, 0xe2, 0x00, 0x60, 0xff, 0xe2, 0x00, 0x40, 0xef, 0xa1, 0x01, 0x50, 0xef, 0xa1, 0x01, 0x60, 0xef, 0xa1, 0x01, 0x40, 0xff, 0xa1, 0x01, 0x50, 0xff, 0xa1, 0x01, 0x60, 0xff, 0xa1, 0x01, 0x40, 0xef, 0xe2, 0x01, 0x50, 0xef, 0xe2, 0x01, 0x60, 0xef, 0xe2, 0x01, 0x40, 0xff, 0xe2, 0x01, 0x50, 0xff, 0xe2, 0x01, 0x60, 0xff, 0xe2, 0x01, 0x40, 0xef, 0xb1, 0x00, 0x50, 0xef, 0xb1, 0x00, 0x60, 0xef, 0xb1, 0x00, 0x70, 0xef, 0xb1, 0x00, 0x40, 0xff, 0xb1, 0x00, 0x50, 0xff, 0xb1, 0x00, 0x60, 0xff, 0xb1, 0x00, 0x70, 0xff, 0xb1, 0x00, 0x40, 0xef, 0xf2, 0x00, 0x50, 0xef, 0xf2, 0x00, 0x60, 0xef, 0xf2, 0x00, 0x70, 0xef, 0xf2, 0x00, 0x40, 0xff, 0xf2, 0x00, 0x50, 0xff, 0xf2, 0x00, 0x60, 0xff, 0xf2, 0x00, 0x70, 0xff, 0xf2, 0x00, 0xc0, 0xef, 0xa2, 0x04, 0xd0, 0xef, 0xa2, 0x04, 0xe0, 0xef, 0xa2, 0x04, 0xc0, 0xff, 0xa2, 0x04, 0xd0, 0xff, 0xa2, 0x04, 0xe0, 0xff, 0xa2, 0x04 ]
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arch: "CS_ARCH_ARM"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
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expected:
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insns:
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asm_text: "vadd.i8 d16, d17, d16"
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asm_text: "vadd.i16 d16, d17, d16"
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asm_text: "vadd.i64 d16, d17, d16"
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asm_text: "vadd.i32 d16, d17, d16"
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asm_text: "vadd.f32 d16, d16, d17"
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asm_text: "vadd.f32 q8, q8, q9"
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asm_text: "vaddl.s8 q8, d17, d16"
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asm_text: "vaddl.s16 q8, d17, d16"
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asm_text: "vaddl.s32 q8, d17, d16"
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asm_text: "vaddl.u8 q8, d17, d16"
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asm_text: "vaddl.u16 q8, d17, d16"
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asm_text: "vaddl.u32 q8, d17, d16"
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asm_text: "vaddw.s8 q8, q8, d18"
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asm_text: "vaddw.s16 q8, q8, d18"
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asm_text: "vaddw.s32 q8, q8, d18"
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asm_text: "vaddw.u8 q8, q8, d18"
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asm_text: "vaddw.u16 q8, q8, d18"
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asm_text: "vaddw.u32 q8, q8, d18"
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asm_text: "vhadd.s8 d16, d16, d17"
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asm_text: "vhadd.s16 d16, d16, d17"
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asm_text: "vhadd.s32 d16, d16, d17"
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asm_text: "vhadd.u8 d16, d16, d17"
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asm_text: "vhadd.u16 d16, d16, d17"
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asm_text: "vhadd.u32 d16, d16, d17"
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asm_text: "vhadd.s8 q8, q8, q9"
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asm_text: "vhadd.s16 q8, q8, q9"
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asm_text: "vhadd.s32 q8, q8, q9"
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asm_text: "vhadd.u8 q8, q8, q9"
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asm_text: "vhadd.u16 q8, q8, q9"
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asm_text: "vhadd.u32 q8, q8, q9"
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asm_text: "vrhadd.s8 d16, d16, d17"
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asm_text: "vrhadd.s16 d16, d16, d17"
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asm_text: "vrhadd.s32 d16, d16, d17"
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asm_text: "vrhadd.u8 d16, d16, d17"
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asm_text: "vrhadd.u16 d16, d16, d17"
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asm_text: "vrhadd.u32 d16, d16, d17"
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asm_text: "vrhadd.s8 q8, q8, q9"
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asm_text: "vrhadd.s16 q8, q8, q9"
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asm_text: "vrhadd.s32 q8, q8, q9"
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asm_text: "vrhadd.u8 q8, q8, q9"
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asm_text: "vrhadd.u16 q8, q8, q9"
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asm_text: "vrhadd.u32 q8, q8, q9"
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asm_text: "vqadd.s8 d16, d16, d17"
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asm_text: "vqadd.s16 d16, d16, d17"
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asm_text: "vqadd.s32 d16, d16, d17"
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asm_text: "vqadd.s64 d16, d16, d17"
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asm_text: "vqadd.u8 d16, d16, d17"
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asm_text: "vqadd.u16 d16, d16, d17"
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asm_text: "vqadd.u32 d16, d16, d17"
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asm_text: "vqadd.u64 d16, d16, d17"
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asm_text: "vqadd.s8 q8, q8, q9"
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asm_text: "vqadd.s16 q8, q8, q9"
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asm_text: "vqadd.s32 q8, q8, q9"
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asm_text: "vqadd.s64 q8, q8, q9"
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asm_text: "vqadd.u8 q8, q8, q9"
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asm_text: "vqadd.u16 q8, q8, q9"
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asm_text: "vqadd.u32 q8, q8, q9"
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asm_text: "vqadd.u64 q8, q8, q9"
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asm_text: "vaddhn.i16 d16, q8, q9"
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asm_text: "vaddhn.i32 d16, q8, q9"
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asm_text: "vaddhn.i64 d16, q8, q9"
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asm_text: "vraddhn.i16 d16, q8, q9"
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asm_text: "vraddhn.i32 d16, q8, q9"
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asm_text: "vraddhn.i64 d16, q8, q9"
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