mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
89 lines
3.3 KiB
YAML
89 lines
3.3 KiB
YAML
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test_cases:
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input:
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bytes: [ 0x42, 0xef, 0xa1, 0x09, 0x52, 0xef, 0xa1, 0x09, 0x62, 0xef, 0xa1, 0x09, 0x42, 0xef, 0xb1, 0x0d, 0x40, 0xef, 0xe4, 0x29, 0x50, 0xef, 0xe4, 0x29, 0x60, 0xef, 0xe4, 0x29, 0x40, 0xef, 0xf4, 0x2d, 0xe0, 0xff, 0xc3, 0x80, 0xc3, 0xef, 0xa2, 0x08, 0xd3, 0xef, 0xa2, 0x08, 0xe3, 0xef, 0xa2, 0x08, 0xc3, 0xff, 0xa2, 0x08, 0xd3, 0xff, 0xa2, 0x08, 0xe3, 0xff, 0xa2, 0x08, 0xa5, 0xef, 0x4a, 0x02, 0xd3, 0xef, 0xa2, 0x09, 0xe3, 0xef, 0xa2, 0x09, 0xdb, 0xef, 0x47, 0x63, 0xdb, 0xef, 0x4f, 0x63, 0xdb, 0xef, 0x67, 0x63, 0xdb, 0xef, 0x6f, 0x63, 0x42, 0xff, 0xa1, 0x09, 0x52, 0xff, 0xa1, 0x09, 0x62, 0xff, 0xa1, 0x09, 0x62, 0xef, 0xb1, 0x0d, 0x40, 0xff, 0xe4, 0x29, 0x50, 0xff, 0xe4, 0x29, 0x60, 0xff, 0xe4, 0x29, 0x60, 0xef, 0xf4, 0x2d, 0x98, 0xff, 0xe6, 0x84, 0xc3, 0xef, 0xa2, 0x0a, 0xd3, 0xef, 0xa2, 0x0a, 0xe3, 0xef, 0xa2, 0x0a, 0xc3, 0xff, 0xa2, 0x0a, 0xd3, 0xff, 0xa2, 0x0a, 0xe3, 0xff, 0xa2, 0x0a, 0xd9, 0xff, 0xe9, 0x66, 0xd3, 0xef, 0xa2, 0x0b, 0xe3, 0xef, 0xa2, 0x0b ]
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arch: "CS_ARCH_ARM"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
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expected:
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insns:
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asm_text: "vmla.i8 d16, d18, d17"
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asm_text: "vmla.i16 d16, d18, d17"
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asm_text: "vmla.i32 d16, d18, d17"
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asm_text: "vmla.f32 d16, d18, d17"
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asm_text: "vmla.i8 q9, q8, q10"
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asm_text: "vmla.i16 q9, q8, q10"
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asm_text: "vmla.i32 q9, q8, q10"
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asm_text: "vmla.f32 q9, q8, q10"
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asm_text: "vmla.i32 q12, q8, d3[0]"
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asm_text: "vmlal.s8 q8, d19, d18"
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asm_text: "vmlal.s16 q8, d19, d18"
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asm_text: "vmlal.s32 q8, d19, d18"
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asm_text: "vmlal.u8 q8, d19, d18"
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asm_text: "vmlal.u16 q8, d19, d18"
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asm_text: "vmlal.u32 q8, d19, d18"
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asm_text: "vmlal.s32 q0, d5, d10[0]"
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asm_text: "vqdmlal.s16 q8, d19, d18"
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asm_text: "vqdmlal.s32 q8, d19, d18"
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asm_text: "vqdmlal.s16 q11, d11, d7[0]"
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asm_text: "vqdmlal.s16 q11, d11, d7[1]"
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asm_text: "vqdmlal.s16 q11, d11, d7[2]"
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asm_text: "vqdmlal.s16 q11, d11, d7[3]"
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asm_text: "vmls.i8 d16, d18, d17"
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asm_text: "vmls.i16 d16, d18, d17"
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asm_text: "vmls.i32 d16, d18, d17"
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asm_text: "vmls.f32 d16, d18, d17"
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asm_text: "vmls.i8 q9, q8, q10"
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asm_text: "vmls.i16 q9, q8, q10"
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asm_text: "vmls.i32 q9, q8, q10"
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asm_text: "vmls.f32 q9, q8, q10"
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asm_text: "vmls.i16 q4, q12, d6[2]"
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asm_text: "vmlsl.s8 q8, d19, d18"
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asm_text: "vmlsl.s16 q8, d19, d18"
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asm_text: "vmlsl.s32 q8, d19, d18"
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asm_text: "vmlsl.u8 q8, d19, d18"
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asm_text: "vmlsl.u16 q8, d19, d18"
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asm_text: "vmlsl.u32 q8, d19, d18"
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asm_text: "vmlsl.u16 q11, d25, d1[3]"
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asm_text: "vqdmlsl.s16 q8, d19, d18"
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asm_text: "vqdmlsl.s32 q8, d19, d18"
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