mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
167 lines
6.3 KiB
YAML
167 lines
6.3 KiB
YAML
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test_cases:
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input:
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bytes: [ 0x40, 0xff, 0xa1, 0x04, 0x50, 0xff, 0xa1, 0x04, 0x60, 0xff, 0xa1, 0x04, 0x70, 0xff, 0xa1, 0x04, 0xcf, 0xef, 0x30, 0x05, 0xdf, 0xef, 0x30, 0x05, 0xff, 0xef, 0x30, 0x05, 0xff, 0xef, 0xb0, 0x05, 0x40, 0xff, 0xe2, 0x04, 0x50, 0xff, 0xe2, 0x04, 0x60, 0xff, 0xe2, 0x04, 0x70, 0xff, 0xe2, 0x04, 0xcf, 0xef, 0x70, 0x05, 0xdf, 0xef, 0x70, 0x05, 0xff, 0xef, 0x70, 0x05, 0xff, 0xef, 0xf0, 0x05, 0xc8, 0xff, 0x30, 0x00, 0xd0, 0xff, 0x30, 0x00, 0xe0, 0xff, 0x30, 0x00, 0xc0, 0xff, 0xb0, 0x00, 0xc8, 0xff, 0x70, 0x00, 0xd0, 0xff, 0x70, 0x00, 0xe0, 0xff, 0x70, 0x00, 0xc0, 0xff, 0xf0, 0x00, 0xc8, 0xef, 0x30, 0x00, 0xd0, 0xef, 0x30, 0x00, 0xe0, 0xef, 0x30, 0x00, 0xc0, 0xef, 0xb0, 0x00, 0xc8, 0xef, 0x70, 0x00, 0xd0, 0xef, 0x70, 0x00, 0xe0, 0xef, 0x70, 0x00, 0xc0, 0xef, 0xf0, 0x00, 0xcf, 0xef, 0x30, 0x0a, 0xdf, 0xef, 0x30, 0x0a, 0xff, 0xef, 0x30, 0x0a, 0xcf, 0xff, 0x30, 0x0a, 0xdf, 0xff, 0x30, 0x0a, 0xff, 0xff, 0x30, 0x0a, 0xf2, 0xff, 0x20, 0x03, 0xf6, 0xff, 0x20, 0x03, 0xfa, 0xff, 0x20, 0x03, 0xc8, 0xef, 0x30, 0x08, 0xd0, 0xef, 0x30, 0x08, 0xe0, 0xef, 0x30, 0x08, 0x40, 0xef, 0xa1, 0x05, 0x50, 0xef, 0xa1, 0x05, 0x60, 0xef, 0xa1, 0x05, 0x70, 0xef, 0xa1, 0x05, 0x40, 0xff, 0xa1, 0x05, 0x50, 0xff, 0xa1, 0x05, 0x60, 0xff, 0xa1, 0x05, 0x70, 0xff, 0xa1, 0x05, 0x40, 0xef, 0xe2, 0x05, 0x50, 0xef, 0xe2, 0x05, 0x60, 0xef, 0xe2, 0x05, 0x70, 0xef, 0xe2, 0x05, 0x40, 0xff, 0xe2, 0x05, 0x50, 0xff, 0xe2, 0x05, 0x60, 0xff, 0xe2, 0x05, 0x70, 0xff, 0xe2, 0x05, 0xc8, 0xef, 0x30, 0x02, 0xd0, 0xef, 0x30, 0x02, 0xe0, 0xef, 0x30, 0x02, 0xc0, 0xef, 0xb0, 0x02, 0xc8, 0xff, 0x30, 0x02, 0xd0, 0xff, 0x30, 0x02, 0xe0, 0xff, 0x30, 0x02, 0xc0, 0xff, 0xb0, 0x02, 0xc8, 0xef, 0x70, 0x02, 0xd0, 0xef, 0x70, 0x02, 0xe0, 0xef, 0x70, 0x02, 0xc0, 0xef, 0xf0, 0x02, 0xc8, 0xff, 0x70, 0x02, 0xd0, 0xff, 0x70, 0x02, 0xe0, 0xff, 0x70, 0x02, 0xc0, 0xff, 0xf0, 0x02, 0xc8, 0xef, 0x70, 0x08, 0xd0, 0xef, 0x70, 0x08, 0xe0, 0xef, 0x70, 0x08 ]
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arch: "CS_ARCH_ARM"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
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expected:
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insns:
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asm_text: "vshl.u8 d16, d17, d16"
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asm_text: "vshl.u16 d16, d17, d16"
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asm_text: "vshl.u32 d16, d17, d16"
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asm_text: "vshl.u64 d16, d17, d16"
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asm_text: "vshl.i8 d16, d16, #7"
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asm_text: "vshl.i16 d16, d16, #0xf"
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asm_text: "vshl.i32 d16, d16, #0x1f"
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asm_text: "vshl.i64 d16, d16, #0x3f"
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asm_text: "vshl.u8 q8, q9, q8"
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asm_text: "vshl.u16 q8, q9, q8"
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asm_text: "vshl.u32 q8, q9, q8"
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asm_text: "vshl.u64 q8, q9, q8"
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asm_text: "vshl.i8 q8, q8, #7"
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asm_text: "vshl.i16 q8, q8, #0xf"
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asm_text: "vshl.i32 q8, q8, #0x1f"
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asm_text: "vshl.i64 q8, q8, #0x3f"
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asm_text: "vshr.u8 d16, d16, #8"
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asm_text: "vshr.u16 d16, d16, #0x10"
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asm_text: "vshr.u32 d16, d16, #0x20"
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asm_text: "vshr.u64 d16, d16, #0x40"
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asm_text: "vshr.u8 q8, q8, #8"
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asm_text: "vshr.u16 q8, q8, #0x10"
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asm_text: "vshr.u32 q8, q8, #0x20"
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asm_text: "vshr.u64 q8, q8, #0x40"
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asm_text: "vshr.s8 d16, d16, #8"
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asm_text: "vshr.s16 d16, d16, #0x10"
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asm_text: "vshr.s32 d16, d16, #0x20"
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asm_text: "vshr.s64 d16, d16, #0x40"
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asm_text: "vshr.s8 q8, q8, #8"
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asm_text: "vshr.s16 q8, q8, #0x10"
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asm_text: "vshr.s32 q8, q8, #0x20"
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asm_text: "vshr.s64 q8, q8, #0x40"
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asm_text: "vshll.s8 q8, d16, #7"
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asm_text: "vshll.s16 q8, d16, #0xf"
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asm_text: "vshll.s32 q8, d16, #0x1f"
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asm_text: "vshll.u8 q8, d16, #7"
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asm_text: "vshll.u16 q8, d16, #0xf"
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asm_text: "vshll.u32 q8, d16, #0x1f"
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asm_text: "vshll.i8 q8, d16, #8"
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asm_text: "vshll.i16 q8, d16, #0x10"
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asm_text: "vshll.i32 q8, d16, #0x20"
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asm_text: "vshrn.i16 d16, q8, #8"
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asm_text: "vshrn.i32 d16, q8, #0x10"
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asm_text: "vshrn.i64 d16, q8, #0x20"
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asm_text: "vrshl.s8 d16, d17, d16"
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asm_text: "vrshl.s16 d16, d17, d16"
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asm_text: "vrshl.s32 d16, d17, d16"
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asm_text: "vrshl.s64 d16, d17, d16"
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asm_text: "vrshl.u8 d16, d17, d16"
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asm_text: "vrshl.u16 d16, d17, d16"
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asm_text: "vrshl.u32 d16, d17, d16"
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asm_text: "vrshl.u64 d16, d17, d16"
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asm_text: "vrshl.s8 q8, q9, q8"
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asm_text: "vrshl.s16 q8, q9, q8"
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asm_text: "vrshl.s32 q8, q9, q8"
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asm_text: "vrshl.s64 q8, q9, q8"
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asm_text: "vrshl.u8 q8, q9, q8"
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asm_text: "vrshl.u16 q8, q9, q8"
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asm_text: "vrshl.u32 q8, q9, q8"
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asm_text: "vrshl.u64 q8, q9, q8"
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asm_text: "vrshr.s8 d16, d16, #8"
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asm_text: "vrshr.s16 d16, d16, #0x10"
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asm_text: "vrshr.s32 d16, d16, #0x20"
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asm_text: "vrshr.s64 d16, d16, #0x40"
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asm_text: "vrshr.u8 d16, d16, #8"
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asm_text: "vrshr.u16 d16, d16, #0x10"
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asm_text: "vrshr.u32 d16, d16, #0x20"
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asm_text: "vrshr.u64 d16, d16, #0x40"
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asm_text: "vrshr.s8 q8, q8, #8"
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asm_text: "vrshr.s16 q8, q8, #0x10"
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asm_text: "vrshr.s32 q8, q8, #0x20"
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asm_text: "vrshr.s64 q8, q8, #0x40"
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asm_text: "vrshr.u8 q8, q8, #8"
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asm_text: "vrshr.u16 q8, q8, #0x10"
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asm_text: "vrshr.u32 q8, q8, #0x20"
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asm_text: "vrshr.u64 q8, q8, #0x40"
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asm_text: "vrshrn.i16 d16, q8, #8"
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asm_text: "vrshrn.i32 d16, q8, #0x10"
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asm_text: "vrshrn.i64 d16, q8, #0x20"
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