mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-04-19 19:01:17 +00:00
Implement more of the vector instructions.
This commit is contained in:
Skyth
parent
f4d342a623
commit
0e59052324
@ -513,6 +513,16 @@ int main(int argc, char* argv[])
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println("\tctx.fn[ctx.ctr.u32 / 4](ctx, base);");
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break;
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case PPC_INST_BDZ:
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println("\t--ctx.ctr.u64;");
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println("\tif (ctx.ctr.u32 == 0) goto loc_{:X};", insn.operands[0]);
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break;
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case PPC_INST_BDZLR:
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println("\t--ctx.ctr.u64;");
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println("\tif (ctx.ctr.u32 == 0) return;", insn.operands[0]);
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break;
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case PPC_INST_BDNZ:
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println("\t--ctx.ctr.u64;");
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println("\tif (ctx.ctr.u32 != 0) goto loc_{:X};", insn.operands[0]);
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@ -1379,12 +1389,50 @@ int main(int argc, char* argv[])
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break;
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case PPC_INST_STVEHX:
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// TODO: vectorize
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// NOTE: accounting for the full vector reversal here
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print("\tea = (");
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if (insn.operands[1] != 0)
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print("ctx.r{}.u32 + ", insn.operands[1]);
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println("ctx.r{}.u32) & ~0x1;", insn.operands[2]);
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println("\tPPC_STORE_U16(ea, ctx.v{}.u16[7 - ((ea & 0xF) >> 1)]);", insn.operands[0]);
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break;
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case PPC_INST_STVEWX:
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case PPC_INST_STVEWX128:
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// TODO: vectorize
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// NOTE: accounting for the full vector reversal here
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print("\tea = (");
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if (insn.operands[1] != 0)
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print("ctx.r{}.u32 + ", insn.operands[1]);
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println("ctx.r{}.u32) & ~0x3;", insn.operands[2]);
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println("\tPPC_STORE_U32(ea, ctx.v{}.u32[3 - ((ea & 0xF) >> 2)]);", insn.operands[0]);
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break;
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case PPC_INST_STVLX:
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case PPC_INST_STVLX128:
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// TODO: vectorize
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// NOTE: accounting for the full vector reversal here
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print("\tea = ");
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if (insn.operands[1] != 0)
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print("ctx.r{}.u32 + ", insn.operands[1]);
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println("ctx.r{}.u32;", insn.operands[2]);
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println("\tfor (size_t i = 0; i < (16 - (ea & 0xF)); i++)");
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println("\t\tPPC_STORE_U8(ea + i, ctx.v{}.u8[15 - i]);", insn.operands[0]);
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break;
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case PPC_INST_STVRX:
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case PPC_INST_STVRX128:
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// TODO: vectorize
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// NOTE: accounting for the full vector reversal here
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print("\tea = ");
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if (insn.operands[1] != 0)
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print("ctx.r{}.u32 + ", insn.operands[1]);
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println("ctx.r{}.u32;", insn.operands[2]);
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println("\tfor (size_t i = 0; i < (ea & 0xF); i++)");
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println("\t\tPPC_STORE_U8((ea & ~0xF) + i, ctx.v{}.u8[15 - ((16 - (ea & 0xF)) + i)]);", insn.operands[0]);
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break;
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case PPC_INST_STVX:
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@ -1429,7 +1477,7 @@ int main(int argc, char* argv[])
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case PPC_INST_STWUX:
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println("\tea = ctx.r{}.u32 + ctx.r{}.u32;", insn.operands[1], insn.operands[2]);
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println("\tPPC_STORE_U32(ea, ctx.r{}.u32);", insn.operands[0]);
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println("\tctx.r{}.u32 = ea;", insn.operands[2]);
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println("\tctx.r{}.u32 = ea;", insn.operands[1]);
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break;
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case PPC_INST_STWX:
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@ -1609,13 +1657,8 @@ int main(int argc, char* argv[])
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break;
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case PPC_INST_VMADDCFP128:
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// TODO: wrong argument order
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_fmadd_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32)));", insn.operands[0], insn.operands[1], insn.operands[2], insn.operands[3]);
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break;
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case PPC_INST_VMADDFP:
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case PPC_INST_VMADDFP128:
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// TODO: wrong argument order
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_fmadd_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32)));", insn.operands[0], insn.operands[1], insn.operands[2], insn.operands[3]);
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break;
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@ -1726,7 +1769,11 @@ int main(int argc, char* argv[])
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break;
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case PPC_INST_VRLIMI128:
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{
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constexpr size_t imm[] = { _MM_SHUFFLE(0, 1, 2, 3), _MM_SHUFFLE(1, 2, 3, 0), _MM_SHUFFLE(2, 3, 0, 1), _MM_SHUFFLE(3, 0, 1, 2) };
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_blend_ps(_mm_load_ps(ctx.v{}.f32), _mm_permute_ps(_mm_load_ps(ctx.v{}.f32), {}), {}));", insn.operands[0], insn.operands[0], insn.operands[1], imm[insn.operands[3]], insn.operands[2]);
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break;
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}
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case PPC_INST_VRSQRTEFP:
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case PPC_INST_VRSQRTEFP128:
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@ -1754,6 +1801,14 @@ int main(int argc, char* argv[])
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println("\tctx.v{}.u32[{}] = ctx.v{}.u32[{}] << ctx.v{}.u8[{}];", insn.operands[0], i, insn.operands[1], i, insn.operands[2], i * 4);
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break;
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case PPC_INST_VSPLTB:
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{
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// NOTE: accounting for full vector reversal here
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uint32_t perm = 15 - insn.operands[2];
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_shuffle_epi8(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_set1_epi8({})));", insn.operands[0], insn.operands[1], perm);
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break;
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}
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case PPC_INST_VSPLTH:
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{
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// NOTE: accounting for full vector reversal here
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@ -1786,6 +1841,10 @@ int main(int argc, char* argv[])
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}
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case PPC_INST_VSR:
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// TODO: vectorize
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println("\ttemp.u64 = ctx.v{}.u8[15] & 0x7;", insn.operands[2]);
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println("\tctx.v{}.u64[1] = (ctx.v{}.u64[0] << (64 - temp.u64)) | (ctx.v{}.u64[1] >> temp.u64);", insn.operands[0], insn.operands[1], insn.operands[1]);
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println("\tctx.v{}.u64[0] = ctx.v{}.u64[0] >> temp.u64;", insn.operands[0], insn.operands[1]);
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break;
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case PPC_INST_VSRAW128:
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@ -1807,6 +1866,12 @@ int main(int argc, char* argv[])
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break;
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case PPC_INST_VSUBSWS:
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// TODO: vectorize
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for (size_t i = 0; i < 4; i++)
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{
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println("\ttemp.s64 = int64_t(ctx.v{}.s32[{}]) - int64_t(ctx.v{}.s32[{}]);", insn.operands[1], i, insn.operands[2], i);
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println("\tctx.v{}.s32[{}] = temp.s64 > INT_MAX ? INT_MAX : temp.s64 < INT_MIN ? INT_MIN : temp.s64;", insn.operands[0], i);
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}
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break;
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case PPC_INST_VSUBUBS:
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@ -1818,6 +1883,22 @@ int main(int argc, char* argv[])
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break;
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case PPC_INST_VUPKD3D128:
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// TODO: vectorize somehow?
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// NOTE: for some reason with binutils 2nd operand is multiplied by 4
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// NOTE: handling vector reversal here too
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switch (insn.operands[2])
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{
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case 4: // 2 shorts
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for (size_t i = 0; i < 2; i++)
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{
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println("\ttemp.f32 = 3.0f;");
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println("\ttemp.s32 += ctx.v{}.s16[{}];", insn.operands[1], 7 - i); // TODO: not sure about the indexing here
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println("\tctx.v{}.f32[{}] = temp.f32;", insn.operands[0], 3 - i);
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}
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println("\tctx.v{}.f32[1] = 0.0f;", insn.operands[0]);
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println("\tctx.v{}.f32[0] = 1.0f;", insn.operands[0]);
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break;
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}
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break;
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case PPC_INST_VUPKHSB128:
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@ -1856,6 +1937,10 @@ int main(int argc, char* argv[])
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case PPC_INST_XORIS:
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println("\tctx.r{}.u64 = ctx.r{}.u64 ^ {};", insn.operands[0], insn.operands[1], insn.operands[2] << 16);
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break;
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default:
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std::println("Unrecognized instruction at 0x{:X}: {}", base - 4, insn.opcode->name);
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break;
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}
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}
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}
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