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https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-05 08:42:05 +00:00
Apply bitmasks in vector shift operations.
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e366e1eea9
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@ -1572,7 +1572,7 @@ bool Recompiler::Recompile(const Function& fn, uint32_t base, const ppc_insn& in
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case PPC_INST_VSLW128:
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// TODO: vectorize, ensure endianness is correct
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for (size_t i = 0; i < 4; i++)
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println("\tctx.v{}.u32[{}] = ctx.v{}.u32[{}] << ctx.v{}.u8[{}];", insn.operands[0], i, insn.operands[1], i, insn.operands[2], i * 4);
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println("\tctx.v{}.u32[{}] = ctx.v{}.u32[{}] << (ctx.v{}.u8[{}] & 0x1F);", insn.operands[0], i, insn.operands[1], i, insn.operands[2], i * 4);
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break;
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case PPC_INST_VSPLTB:
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@ -1619,14 +1619,14 @@ bool Recompiler::Recompile(const Function& fn, uint32_t base, const ppc_insn& in
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case PPC_INST_VSRAW128:
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// TODO: vectorize, ensure endianness is correct
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for (size_t i = 0; i < 4; i++)
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println("\tctx.v{}.s32[{}] = ctx.v{}.s32[{}] >> ctx.v{}.u8[{}];", insn.operands[0], i, insn.operands[1], i, insn.operands[2], i * 4);
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println("\tctx.v{}.s32[{}] = ctx.v{}.s32[{}] >> (ctx.v{}.u8[{}] & 0x1F);", insn.operands[0], i, insn.operands[1], i, insn.operands[2], i * 4);
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break;
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case PPC_INST_VSRW:
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case PPC_INST_VSRW128:
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// TODO: vectorize, ensure endianness is correct
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for (size_t i = 0; i < 4; i++)
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println("\tctx.v{}.u32[{}] = ctx.v{}.u32[{}] >> ctx.v{}.u8[{}];", insn.operands[0], i, insn.operands[1], i, insn.operands[2], i * 4);
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println("\tctx.v{}.u32[{}] = ctx.v{}.u32[{}] >> (ctx.v{}.u8[{}] & 0x1F);", insn.operands[0], i, insn.operands[1], i, insn.operands[2], i * 4);
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break;
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case PPC_INST_VSUBFP:
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