diff --git a/PowerUtils/disasm.h b/PowerUtils/disasm.h index 65c5262..3ab083e 100644 --- a/PowerUtils/disasm.h +++ b/PowerUtils/disasm.h @@ -24,4 +24,9 @@ namespace ppc { return gBigEndianDisassembler.Disassemble(code, size, base, out); } + + static int Disassemble(const void* code, uint64_t base, ppc_insn& out) + { + return Disassemble(code, 4, base, out); + } } diff --git a/thirdparty/disasm/CMakeLists.txt b/thirdparty/disasm/CMakeLists.txt index 47a5293..eae4669 100644 --- a/thirdparty/disasm/CMakeLists.txt +++ b/thirdparty/disasm/CMakeLists.txt @@ -1,4 +1,4 @@ project("disasm") -add_library(disasm "ppc-dis.c" "disasm.c") +add_library(disasm "ppc-dis.c" "disasm.c" "ppc.h") target_include_directories(disasm PUBLIC .) diff --git a/thirdparty/disasm/dis-asm.h b/thirdparty/disasm/dis-asm.h index a400c8c..77d5ec2 100644 --- a/thirdparty/disasm/dis-asm.h +++ b/thirdparty/disasm/dis-asm.h @@ -410,6 +410,9 @@ typedef struct powerpc_opcode operand table. They appear in the order which the operands must appear in assembly code, and are terminated by a zero. */ unsigned char operands[8]; + + /* The opcode ID. */ + int id; } powerpc_opcode; typedef struct ppc_insn diff --git a/thirdparty/disasm/ppc-dis.c b/thirdparty/disasm/ppc-dis.c index a3854e4..1f13638 100644 --- a/thirdparty/disasm/ppc-dis.c +++ b/thirdparty/disasm/ppc-dis.c @@ -19,6 +19,8 @@ You should have received a copy of the GNU General Public License along with this file; see the file COPYING. If not, see . */ #include "dis-asm.h" +#include "ppc.h" + #define BFD_DEFAULT_TARGET_SIZE 64 /* ppc.h -- Header file for PowerPC opcode table @@ -72,15 +74,15 @@ extern const int powerpc_num_opcodes; but it also supports many additional POWER instructions. */ #define PPC_OPCODE_601 0x20 -/* Opcode is supported in both the Power and PowerPC architectures - (ie, compiler's -mcpu=common or assembler's -mcom). */ + /* Opcode is supported in both the Power and PowerPC architectures + (ie, compiler's -mcpu=common or assembler's -mcom). */ #define PPC_OPCODE_COMMON 0x40 -/* Opcode is supported for any Power or PowerPC platform (this is - for the assembler's -many option, and it eliminates duplicates). */ + /* Opcode is supported for any Power or PowerPC platform (this is + for the assembler's -many option, and it eliminates duplicates). */ #define PPC_OPCODE_ANY 0x80 -/* Opcode is supported as part of the 64-bit bridge. */ + /* Opcode is supported as part of the 64-bit bridge. */ #define PPC_OPCODE_64_BRIDGE 0x100 /* Opcode is supported by Altivec Vector Unit */ @@ -147,52 +149,52 @@ extern const int powerpc_num_opcodes; struct powerpc_operand { - /* A bitmask of bits in the operand. */ - unsigned int bitm; + /* A bitmask of bits in the operand. */ + unsigned int bitm; - /* How far the operand is left shifted in the instruction. - -1 to indicate that BITM and SHIFT cannot be used to determine - where the operand goes in the insn. */ - int shift; + /* How far the operand is left shifted in the instruction. + -1 to indicate that BITM and SHIFT cannot be used to determine + where the operand goes in the insn. */ + int shift; - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. - If it is NULL, execute - i |= (op & o->bitm) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the operand value). + If it is NULL, execute + i |= (op & o->bitm) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the operand value). - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - unsigned long (*insert) - (unsigned long instruction, long op, int dialect, const char **errmsg); + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + unsigned long (*insert) + (unsigned long instruction, long op, int dialect, const char** errmsg); - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. - If it is NULL, compute - op = (i >> o->shift) & o->bitm; - if ((o->flags & PPC_OPERAND_SIGNED) != 0) - sign_extend (op); - (i is the instruction, o is a pointer to this structure, and op - is the result). + If it is NULL, compute + op = (i >> o->shift) & o->bitm; + if ((o->flags & PPC_OPERAND_SIGNED) != 0) + sign_extend (op); + (i is the instruction, o is a pointer to this structure, and op + is the result). - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - long (*extract) (unsigned long instruction, int dialect, int *invalid); + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + long (*extract) (unsigned long instruction, int dialect, int* invalid); - /* One bit syntax flags. */ - unsigned long flags; + /* One bit syntax flags. */ + unsigned long flags; }; /* Elements in the table are retrieved by indexing with values from @@ -212,77 +214,77 @@ extern const unsigned int num_powerpc_operands; this flag is ignored. */ #define PPC_OPERAND_SIGNOPT (0x2) -/* This operand does not actually exist in the assembler input. This - is used to support extended mnemonics such as mr, for which two - operands fields are identical. The assembler should call the - insert function with any op value. The disassembler should call - the extract function, ignore the return value, and check the value - placed in the valid argument. */ + /* This operand does not actually exist in the assembler input. This + is used to support extended mnemonics such as mr, for which two + operands fields are identical. The assembler should call the + insert function with any op value. The disassembler should call + the extract function, ignore the return value, and check the value + placed in the valid argument. */ #define PPC_OPERAND_FAKE (0x4) -/* The next operand should be wrapped in parentheses rather than - separated from this one by a comma. This is used for the load and - store instructions which want their operands to look like - reg,displacement(reg) - */ + /* The next operand should be wrapped in parentheses rather than + separated from this one by a comma. This is used for the load and + store instructions which want their operands to look like + reg,displacement(reg) + */ #define PPC_OPERAND_PARENS (0x8) -/* This operand may use the symbolic names for the CR fields, which - are - lt 0 gt 1 eq 2 so 3 un 3 - cr0 0 cr1 1 cr2 2 cr3 3 - cr4 4 cr5 5 cr6 6 cr7 7 - These may be combined arithmetically, as in cr2*4+gt. These are - only supported on the PowerPC, not the POWER. */ + /* This operand may use the symbolic names for the CR fields, which + are + lt 0 gt 1 eq 2 so 3 un 3 + cr0 0 cr1 1 cr2 2 cr3 3 + cr4 4 cr5 5 cr6 6 cr7 7 + These may be combined arithmetically, as in cr2*4+gt. These are + only supported on the PowerPC, not the POWER. */ #define PPC_OPERAND_CR (0x10) -/* This operand names a register. The disassembler uses this to print - register names with a leading 'r'. */ + /* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ #define PPC_OPERAND_GPR (0x20) -/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ + /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ #define PPC_OPERAND_GPR_0 (0x40) /* This operand names a floating point register. The disassembler prints these with a leading 'f'. */ #define PPC_OPERAND_FPR (0x80) -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ + /* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ #define PPC_OPERAND_RELATIVE (0x100) -/* This operand is an absolute branch address. The disassembler - prints these symbolically if possible. */ + /* This operand is an absolute branch address. The disassembler + prints these symbolically if possible. */ #define PPC_OPERAND_ABSOLUTE (0x200) -/* This operand is optional, and is zero if omitted. This is used for - example, in the optional BF field in the comparison instructions. The - assembler must count the number of operands remaining on the line, - and the number of operands remaining for the opcode, and decide - whether this operand is present or not. The disassembler should - print this operand out only if it is not zero. */ + /* This operand is optional, and is zero if omitted. This is used for + example, in the optional BF field in the comparison instructions. The + assembler must count the number of operands remaining on the line, + and the number of operands remaining for the opcode, and decide + whether this operand is present or not. The disassembler should + print this operand out only if it is not zero. */ #define PPC_OPERAND_OPTIONAL (0x400) -/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand - is omitted, then for the next operand use this operand value plus - 1, ignoring the next operand field for the opcode. This wretched - hack is needed because the Power rotate instructions can take - either 4 or 5 operands. The disassembler should print this operand - out regardless of the PPC_OPERAND_OPTIONAL field. */ + /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand + is omitted, then for the next operand use this operand value plus + 1, ignoring the next operand field for the opcode. This wretched + hack is needed because the Power rotate instructions can take + either 4 or 5 operands. The disassembler should print this operand + out regardless of the PPC_OPERAND_OPTIONAL field. */ #define PPC_OPERAND_NEXT (0x800) -/* This operand should be regarded as a negative number for the - purposes of overflow checking (i.e., the normal most negative - number is disallowed and one more than the normal most positive - number is allowed). This flag will only be set for a signed - operand. */ + /* This operand should be regarded as a negative number for the + purposes of overflow checking (i.e., the normal most negative + number is disallowed and one more than the normal most positive + number is allowed). This flag will only be set for a signed + operand. */ #define PPC_OPERAND_NEGATIVE (0x1000) -/* This operand names a vector unit register. The disassembler - prints these with a leading 'v'. */ + /* This operand names a vector unit register. The disassembler + prints these with a leading 'v'. */ #define PPC_OPERAND_VR (0x2000) -/* This operand is for the DS field in a DS form instruction. */ + /* This operand is for the DS field in a DS form instruction. */ #define PPC_OPERAND_DS (0x4000) /* This operand is for the DQ field in a DQ form instruction. */ @@ -297,21 +299,21 @@ extern const unsigned int num_powerpc_operands; struct powerpc_macro { - /* The macro name. */ - const char *name; + /* The macro name. */ + const char* name; - /* The number of operands the macro takes. */ - unsigned int operands; + /* The number of operands the macro takes. */ + unsigned int operands; - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The values are the - same as those for the struct powerpc_opcode flags field. */ - unsigned long flags; + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The values are the + same as those for the struct powerpc_opcode flags field. */ + unsigned long flags; - /* A format string to turn the macro into a normal instruction. - Each %N in the string is replaced with operand number N (zero - based). */ - const char *format; + /* A format string to turn the macro into a normal instruction. + Each %N in the string is replaced with operand number N (zero + based). */ + const char* format; }; extern const struct powerpc_macro powerpc_macros[]; @@ -338,54 +340,54 @@ extern const int powerpc_num_macros; along with this file; see the file COPYING. If not, see . */ -/* This file holds the PowerPC opcode table. The opcode table - includes almost all of the extended instruction mnemonics. This - permits the disassembler to use them, and simplifies the assembler - logic, at the cost of increasing the table size. The table is - strictly constant data, so the compiler should be able to put it in - the .text section. + /* This file holds the PowerPC opcode table. The opcode table + includes almost all of the extended instruction mnemonics. This + permits the disassembler to use them, and simplifies the assembler + logic, at the cost of increasing the table size. The table is + strictly constant data, so the compiler should be able to put it in + the .text section. - This file also holds the operand table. All knowledge about - inserting operands into instructions and vice-versa is kept in this - file. */ + This file also holds the operand table. All knowledge about + inserting operands into instructions and vice-versa is kept in this + file. */ -/* Local insertion and extraction functions. */ + /* Local insertion and extraction functions. */ -static unsigned long insert_bat (unsigned long, long, int, const char **); -static long extract_bat (unsigned long, int, int *); -static unsigned long insert_bba (unsigned long, long, int, const char **); -static long extract_bba (unsigned long, int, int *); -static unsigned long insert_bdm (unsigned long, long, int, const char **); -static long extract_bdm (unsigned long, int, int *); -static unsigned long insert_bdp (unsigned long, long, int, const char **); -static long extract_bdp (unsigned long, int, int *); -static unsigned long insert_bo (unsigned long, long, int, const char **); -static long extract_bo (unsigned long, int, int *); -static unsigned long insert_boe (unsigned long, long, int, const char **); -static long extract_boe (unsigned long, int, int *); -static unsigned long insert_fxm (unsigned long, long, int, const char **); -static long extract_fxm (unsigned long, int, int *); -static unsigned long insert_mbe (unsigned long, long, int, const char **); -static long extract_mbe (unsigned long, int, int *); -static unsigned long insert_mb6 (unsigned long, long, int, const char **); -static long extract_mb6 (unsigned long, int, int *); -static long extract_nb (unsigned long, int, int *); -static unsigned long insert_nsi (unsigned long, long, int, const char **); -static long extract_nsi (unsigned long, int, int *); -static unsigned long insert_ral (unsigned long, long, int, const char **); -static unsigned long insert_ram (unsigned long, long, int, const char **); -static unsigned long insert_raq (unsigned long, long, int, const char **); -static unsigned long insert_ras (unsigned long, long, int, const char **); -static unsigned long insert_rbs (unsigned long, long, int, const char **); -static long extract_rbs (unsigned long, int, int *); -static unsigned long insert_sh6 (unsigned long, long, int, const char **); -static long extract_sh6 (unsigned long, int, int *); -static unsigned long insert_spr (unsigned long, long, int, const char **); -static long extract_spr (unsigned long, int, int *); -static unsigned long insert_sprg (unsigned long, long, int, const char **); -static long extract_sprg (unsigned long, int, int *); -static unsigned long insert_tbr (unsigned long, long, int, const char **); -static long extract_tbr (unsigned long, int, int *); +static unsigned long insert_bat(unsigned long, long, int, const char**); +static long extract_bat(unsigned long, int, int*); +static unsigned long insert_bba(unsigned long, long, int, const char**); +static long extract_bba(unsigned long, int, int*); +static unsigned long insert_bdm(unsigned long, long, int, const char**); +static long extract_bdm(unsigned long, int, int*); +static unsigned long insert_bdp(unsigned long, long, int, const char**); +static long extract_bdp(unsigned long, int, int*); +static unsigned long insert_bo(unsigned long, long, int, const char**); +static long extract_bo(unsigned long, int, int*); +static unsigned long insert_boe(unsigned long, long, int, const char**); +static long extract_boe(unsigned long, int, int*); +static unsigned long insert_fxm(unsigned long, long, int, const char**); +static long extract_fxm(unsigned long, int, int*); +static unsigned long insert_mbe(unsigned long, long, int, const char**); +static long extract_mbe(unsigned long, int, int*); +static unsigned long insert_mb6(unsigned long, long, int, const char**); +static long extract_mb6(unsigned long, int, int*); +static long extract_nb(unsigned long, int, int*); +static unsigned long insert_nsi(unsigned long, long, int, const char**); +static long extract_nsi(unsigned long, int, int*); +static unsigned long insert_ral(unsigned long, long, int, const char**); +static unsigned long insert_ram(unsigned long, long, int, const char**); +static unsigned long insert_raq(unsigned long, long, int, const char**); +static unsigned long insert_ras(unsigned long, long, int, const char**); +static unsigned long insert_rbs(unsigned long, long, int, const char**); +static long extract_rbs(unsigned long, int, int*); +static unsigned long insert_sh6(unsigned long, long, int, const char**); +static long extract_sh6(unsigned long, int, int*); +static unsigned long insert_spr(unsigned long, long, int, const char**); +static long extract_spr(unsigned long, int, int*); +static unsigned long insert_sprg(unsigned long, long, int, const char**); +static long extract_sprg(unsigned long, int, int*); +static unsigned long insert_tbr(unsigned long, long, int, const char**); +static long extract_tbr(unsigned long, int, int*); /* The operands table. @@ -400,474 +402,474 @@ static long extract_tbr (unsigned long, int, int *); const struct powerpc_operand powerpc_operands[] = { - /* The zero index is used to indicate the end of the list of - operands. */ -#define UNUSED 0 - { 0, 0, NULL, NULL, 0 }, - - /* The BA field in an XL form instruction. */ -#define BA UNUSED + 1 - /* The BI field in a B form or XL form instruction. */ -#define BI BA -#define BI_MASK (0x1f << 16) - { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR }, - - /* The BA field in an XL form instruction when it must be the same - as the BT field in the same instruction. */ -#define BAT BA + 1 - { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, - - /* The BB field in an XL form instruction. */ -#define BB BAT + 1 -#define BB_MASK (0x1f << 11) - { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR }, - - /* The BB field in an XL form instruction when it must be the same - as the BA field in the same instruction. */ -#define BBA BB + 1 - { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, - - /* The BD field in a B form instruction. The lower two bits are - forced to zero. */ -#define BD BBA + 1 - { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when absolute addressing is - used. */ -#define BDA BD + 1 - { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the - modifier is used. - This sets the y bit of the BO field appropriately. */ -#define BDM BDA + 1 - { 0xfffc, 0, insert_bdm, extract_bdm, - PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the - modifier is used - and absolute address is used. */ -#define BDMA BDM + 1 - { 0xfffc, 0, insert_bdm, extract_bdm, - PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the + modifier is used. - This sets the y bit of the BO field appropriately. */ -#define BDP BDMA + 1 - { 0xfffc, 0, insert_bdp, extract_bdp, - PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the + modifier is used - and absolute addressing is used. */ -#define BDPA BDP + 1 - { 0xfffc, 0, insert_bdp, extract_bdp, - PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BF field in an X or XL form instruction. */ -#define BF BDPA + 1 - /* The CRFD field in an X form instruction. */ -#define CRFD BF - { 0x7, 23, NULL, NULL, PPC_OPERAND_CR }, - - /* The BF field in an X or XL form instruction. */ -#define BFF BF + 1 - { 0x7, 23, NULL, NULL, 0 }, - - /* An optional BF field. This is used for comparison instructions, - in which an omitted BF field is taken as zero. */ -#define OBF BFF + 1 - { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, - - /* The BFA field in an X or XL form instruction. */ -#define BFA OBF + 1 - { 0x7, 18, NULL, NULL, PPC_OPERAND_CR }, - - /* The BO field in a B form instruction. Certain values are - illegal. */ -#define BO BFA + 1 -#define BO_MASK (0x1f << 21) - { 0x1f, 21, insert_bo, extract_bo, 0 }, - - /* The BO field in a B form instruction when the + or - modifier is - used. This is like the BO field, but it must be even. */ -#define BOE BO + 1 - { 0x1e, 21, insert_boe, extract_boe, 0 }, - -#define BH BOE + 1 - { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, - - /* The BT field in an X or XL form instruction. */ -#define BT BH + 1 - { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR }, - - /* The condition register number portion of the BI field in a B form - or XL form instruction. This is used for the extended - conditional branch mnemonics, which set the lower two bits of the - BI field. This field is optional. */ -#define CR BT + 1 - { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, - - /* The CRB field in an X form instruction. */ -#define CRB CR + 1 - /* The MB field in an M form instruction. */ -#define MB CRB -#define MB_MASK (0x1f << 6) - { 0x1f, 6, NULL, NULL, 0 }, - - /* The CRFS field in an X form instruction. */ -#define CRFS CRB + 1 - { 0x7, 0, NULL, NULL, PPC_OPERAND_CR }, - - /* The CT field in an X form instruction. */ -#define CT CRFS + 1 - /* The MO field in an mbar instruction. */ -#define MO CT - { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, - - /* The D field in a D form instruction. This is a displacement off - a register, and implies that the next operand is a register in - parentheses. */ -#define D CT + 1 - { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, - - /* The DE field in a DE form instruction. This is like D, but is 12 - bits only. */ -#define DE D + 1 - { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, - - /* The DES field in a DES form instruction. This is like DS, but is 14 - bits only (12 stored.) */ -#define DES DE + 1 - { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, - - /* The DQ field in a DQ form instruction. This is like D, but the - lower four bits are forced to zero. */ -#define DQ DES + 1 - { 0xfff0, 0, NULL, NULL, - PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, - - /* The DS field in a DS form instruction. This is like D, but the - lower two bits are forced to zero. */ -#undef DS -#define DS DQ + 1 - { 0xfffc, 0, NULL, NULL, - PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, - - /* The E field in a wrteei instruction. */ -#define E DS + 1 - { 0x1, 15, NULL, NULL, 0 }, - - /* The FL1 field in a POWER SC form instruction. */ -#define FL1 E + 1 - /* The U field in an X form instruction. */ -#define U FL1 - { 0xf, 12, NULL, NULL, 0 }, - - /* The FL2 field in a POWER SC form instruction. */ -#define FL2 FL1 + 1 - { 0x7, 2, NULL, NULL, 0 }, - - /* The FLM field in an XFL form instruction. */ -#define FLM FL2 + 1 - { 0xff, 17, NULL, NULL, 0 }, - - /* The FRA field in an X or A form instruction. */ -#define FRA FLM + 1 -#define FRA_MASK (0x1f << 16) - { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, - - /* The FRB field in an X or A form instruction. */ -#define FRB FRA + 1 -#define FRB_MASK (0x1f << 11) - { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, - - /* The FRC field in an A form instruction. */ -#define FRC FRB + 1 -#define FRC_MASK (0x1f << 6) - { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, - - /* The FRS field in an X form instruction or the FRT field in a D, X - or A form instruction. */ -#define FRS FRC + 1 -#define FRT FRS - { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, - - /* The FXM field in an XFX instruction. */ -#define FXM FRS + 1 - { 0xff, 12, insert_fxm, extract_fxm, 0 }, - - /* Power4 version for mfcr. */ -#define FXM4 FXM + 1 - { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, - - /* The L field in a D or X form instruction. */ -#define L FXM4 + 1 - { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, - - /* The LEV field in a POWER SVC form instruction. */ -#define SVC_LEV L + 1 - { 0x7f, 5, NULL, NULL, 0 }, - - /* The LEV field in an SC form instruction. */ -#define LEV SVC_LEV + 1 - { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, - - /* The LI field in an I form instruction. The lower two bits are - forced to zero. */ -#define LI LEV + 1 - { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The LI field in an I form instruction when used as an absolute - address. */ -#define LIA LI + 1 - { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The LS field in an X (sync) form instruction. */ -#define LS LIA + 1 - { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, - - /* The ME field in an M form instruction. */ -#define ME LS + 1 -#define ME_MASK (0x1f << 1) - { 0x1f, 1, NULL, NULL, 0 }, - - /* The MB and ME fields in an M form instruction expressed a single - operand which is a bitmask indicating which bits to select. This - is a two operand form using PPC_OPERAND_NEXT. See the - description in opcode/ppc.h for what this means. */ -#define MBE ME + 1 - { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, - { -1, 0, insert_mbe, extract_mbe, 0 }, - - /* The MB or ME field in an MD or MDS form instruction. The high - bit is wrapped to the low end. */ -#define MB6 MBE + 2 -#define ME6 MB6 -#define MB6_MASK (0x3f << 5) - { 0x3f, 5, insert_mb6, extract_mb6, 0 }, - - /* The NB field in an X form instruction. The value 32 is stored as - 0. */ -#define NB MB6 + 1 - { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, - - /* The NSI field in a D form instruction. This is the same as the - SI field, only negated. */ -#define NSI NB + 1 - { 0xffff, 0, insert_nsi, extract_nsi, - PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, - - /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ -#define RA NSI + 1 -#define RA_MASK (0x1f << 16) - { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, - - /* As above, but 0 in the RA field means zero, not r0. */ -#define RA0 RA + 1 - { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, - - /* The RA field in the DQ form lq instruction, which has special - value restrictions. */ -#define RAQ RA0 + 1 - { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, - - /* The RA field in a D or X form instruction which is an updating - load, which means that the RA field may not be zero and may not - equal the RT field. */ -#define RAL RAQ + 1 - { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, - - /* The RA field in an lmw instruction, which has special value - restrictions. */ -#define RAM RAL + 1 - { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, - - /* The RA field in a D or X form instruction which is an updating - store or an updating floating point load, which means that the RA - field may not be zero. */ -#define RAS RAM + 1 - { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, - - /* The RA field of the tlbwe instruction, which is optional. */ -#define RAOPT RAS + 1 - { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, - - /* The RB field in an X, XO, M, or MDS form instruction. */ -#define RB RAOPT + 1 -#define RB_MASK (0x1f << 11) - { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, - - /* The RB field in an X form instruction when it must be the same as - the RS field in the instruction. This is used for extended - mnemonics like mr. */ -#define RBS RB + 1 - { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, - - /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form - instruction or the RT field in a D, DS, X, XFX or XO form - instruction. */ -#define RS RBS + 1 -#define RT RS -#define RT_MASK (0x1f << 21) - { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, - - /* The RS and RT fields of the DS form stq instruction, which have - special value restrictions. */ -#define RSQ RS + 1 -#define RTQ RSQ - { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 }, - - /* The RS field of the tlbwe instruction, which is optional. */ -#define RSO RSQ + 1 -#define RTO RSO - { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, - - /* The SH field in an X or M form instruction. */ -#define SH RSO + 1 -#define SH_MASK (0x1f << 11) - /* The other UIMM field in a EVX form instruction. */ -#define EVUIMM SH - { 0x1f, 11, NULL, NULL, 0 }, - - /* The SH field in an MD form instruction. This is split. */ -#define SH6 SH + 1 -#define SH6_MASK ((0x1f << 11) | (1 << 1)) - { 0x3f, -1, insert_sh6, extract_sh6, 0 }, - - /* The SH field of the tlbwe instruction, which is optional. */ -#define SHO SH6 + 1 - { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, - - /* The SI field in a D form instruction. */ -#define SI SHO + 1 - { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, - - /* The SI field in a D form instruction when we accept a wide range - of positive values. */ -#define SISIGNOPT SI + 1 - { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, - - /* The SPR field in an XFX form instruction. This is flipped--the - lower 5 bits are stored in the upper 5 and vice- versa. */ -#define SPR SISIGNOPT + 1 -#define PMR SPR -#define SPR_MASK (0x3ff << 11) - { 0x3ff, 11, insert_spr, extract_spr, 0 }, - - /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ -#define SPRBAT SPR + 1 -#define SPRBAT_MASK (0x3 << 17) - { 0x3, 17, NULL, NULL, 0 }, - - /* The SPRG register number in an XFX form m[ft]sprg instruction. */ -#define SPRG SPRBAT + 1 - { 0x1f, 16, insert_sprg, extract_sprg, 0 }, - - /* The SR field in an X form instruction. */ -#define SR SPRG + 1 - { 0xf, 16, NULL, NULL, 0 }, - - /* The STRM field in an X AltiVec form instruction. */ -#define STRM SR + 1 - { 0x3, 21, NULL, NULL, 0 }, - - /* The SV field in a POWER SC form instruction. */ -#define SV STRM + 1 - { 0x3fff, 2, NULL, NULL, 0 }, - - /* The TBR field in an XFX form instruction. This is like the SPR - field, but it is optional. */ -#define TBR SV + 1 - { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, - - /* The TO field in a D or X form instruction. */ -#define TO TBR + 1 -#define TO_MASK (0x1f << 21) - { 0x1f, 21, NULL, NULL, 0 }, - - /* The UI field in a D form instruction. */ -#define UI TO + 1 - { 0xffff, 0, NULL, NULL, 0 }, - - /* The VA field in a VA, VX or VXR form instruction. */ -#define VA UI + 1 - { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, - - /* The VB field in a VA, VX or VXR form instruction. */ -#define VB VA + 1 - { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, - - /* The VC field in a VA form instruction. */ -#define VC VB + 1 - { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, - - /* The VD or VS field in a VA, VX, VXR or X form instruction. */ -#define VD VC + 1 -#define VS VD - { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, - - /* The SIMM field in a VX form instruction. */ -#define SIMM VD + 1 - { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, - - /* The UIMM field in a VX form instruction, and TE in Z form. */ -#define UIMM SIMM + 1 -#define TE UIMM - { 0x1f, 16, NULL, NULL, 0 }, - - /* The SHB field in a VA form instruction. */ -#define SHB UIMM + 1 - { 0xf, 6, NULL, NULL, 0 }, - - /* The other UIMM field in a half word EVX form instruction. */ -#define EVUIMM_2 SHB + 1 - { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, - - /* The other UIMM field in a word EVX form instruction. */ -#define EVUIMM_4 EVUIMM_2 + 1 - { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, - - /* The other UIMM field in a double EVX form instruction. */ -#define EVUIMM_8 EVUIMM_4 + 1 - { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, - - /* The WS field. */ -#define WS EVUIMM_8 + 1 - { 0x7, 11, NULL, NULL, 0 }, - - /* The L field in an mtmsrd or A form instruction or W in an X form. */ -#define A_L WS + 1 -#define W A_L - { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, - -#define RMC A_L + 1 - { 0x3, 9, NULL, NULL, 0 }, - -#define R RMC + 1 - { 0x1, 16, NULL, NULL, 0 }, - -#define SP R + 1 - { 0x3, 19, NULL, NULL, 0 }, - -#define S SP + 1 - { 0x1, 20, NULL, NULL, 0 }, - - /* SH field starting at bit position 16. */ -#define SH16 S + 1 - /* The DCM and DGM fields in a Z form instruction. */ -#define DCM SH16 -#define DGM DCM - { 0x3f, 10, NULL, NULL, 0 }, - - /* The EH field in larx instruction. */ -#define EH SH16 + 1 - { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, - - /* The L field in an mtfsf or XFL form instruction. */ -#define XFL_L EH + 1 - { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, + /* The zero index is used to indicate the end of the list of + operands. */ + #define UNUSED 0 + { 0, 0, NULL, NULL, 0 }, + + /* The BA field in an XL form instruction. */ + #define BA UNUSED + 1 + /* The BI field in a B form or XL form instruction. */ + #define BI BA + #define BI_MASK (0x1f << 16) + { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR }, + + /* The BA field in an XL form instruction when it must be the same + as the BT field in the same instruction. */ + #define BAT BA + 1 + { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, + + /* The BB field in an XL form instruction. */ + #define BB BAT + 1 + #define BB_MASK (0x1f << 11) + { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR }, + + /* The BB field in an XL form instruction when it must be the same + as the BA field in the same instruction. */ + #define BBA BB + 1 + { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, + + /* The BD field in a B form instruction. The lower two bits are + forced to zero. */ + #define BD BBA + 1 + { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when absolute addressing is + used. */ + #define BDA BD + 1 + { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when the - modifier is used. + This sets the y bit of the BO field appropriately. */ + #define BDM BDA + 1 + { 0xfffc, 0, insert_bdm, extract_bdm, + PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when the - modifier is used + and absolute address is used. */ + #define BDMA BDM + 1 + { 0xfffc, 0, insert_bdm, extract_bdm, + PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when the + modifier is used. + This sets the y bit of the BO field appropriately. */ + #define BDP BDMA + 1 + { 0xfffc, 0, insert_bdp, extract_bdp, + PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when the + modifier is used + and absolute addressing is used. */ + #define BDPA BDP + 1 + { 0xfffc, 0, insert_bdp, extract_bdp, + PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + + /* The BF field in an X or XL form instruction. */ + #define BF BDPA + 1 + /* The CRFD field in an X form instruction. */ + #define CRFD BF + { 0x7, 23, NULL, NULL, PPC_OPERAND_CR }, + + /* The BF field in an X or XL form instruction. */ + #define BFF BF + 1 + { 0x7, 23, NULL, NULL, 0 }, + + /* An optional BF field. This is used for comparison instructions, + in which an omitted BF field is taken as zero. */ + #define OBF BFF + 1 + { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, + + /* The BFA field in an X or XL form instruction. */ + #define BFA OBF + 1 + { 0x7, 18, NULL, NULL, PPC_OPERAND_CR }, + + /* The BO field in a B form instruction. Certain values are + illegal. */ + #define BO BFA + 1 + #define BO_MASK (0x1f << 21) + { 0x1f, 21, insert_bo, extract_bo, 0 }, + + /* The BO field in a B form instruction when the + or - modifier is + used. This is like the BO field, but it must be even. */ + #define BOE BO + 1 + { 0x1e, 21, insert_boe, extract_boe, 0 }, + + #define BH BOE + 1 + { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The BT field in an X or XL form instruction. */ + #define BT BH + 1 + { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR }, + + /* The condition register number portion of the BI field in a B form + or XL form instruction. This is used for the extended + conditional branch mnemonics, which set the lower two bits of the + BI field. This field is optional. */ + #define CR BT + 1 + { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, + + /* The CRB field in an X form instruction. */ + #define CRB CR + 1 + /* The MB field in an M form instruction. */ + #define MB CRB + #define MB_MASK (0x1f << 6) + { 0x1f, 6, NULL, NULL, 0 }, + + /* The CRFS field in an X form instruction. */ + #define CRFS CRB + 1 + { 0x7, 0, NULL, NULL, PPC_OPERAND_CR }, + + /* The CT field in an X form instruction. */ + #define CT CRFS + 1 + /* The MO field in an mbar instruction. */ + #define MO CT + { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The D field in a D form instruction. This is a displacement off + a register, and implies that the next operand is a register in + parentheses. */ + #define D CT + 1 + { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + + /* The DE field in a DE form instruction. This is like D, but is 12 + bits only. */ + #define DE D + 1 + { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + + /* The DES field in a DES form instruction. This is like DS, but is 14 + bits only (12 stored.) */ + #define DES DE + 1 + { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + + /* The DQ field in a DQ form instruction. This is like D, but the + lower four bits are forced to zero. */ + #define DQ DES + 1 + { 0xfff0, 0, NULL, NULL, + PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, + + /* The DS field in a DS form instruction. This is like D, but the + lower two bits are forced to zero. */ + #undef DS + #define DS DQ + 1 + { 0xfffc, 0, NULL, NULL, + PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, + + /* The E field in a wrteei instruction. */ + #define E DS + 1 + { 0x1, 15, NULL, NULL, 0 }, + + /* The FL1 field in a POWER SC form instruction. */ + #define FL1 E + 1 + /* The U field in an X form instruction. */ + #define U FL1 + { 0xf, 12, NULL, NULL, 0 }, + + /* The FL2 field in a POWER SC form instruction. */ + #define FL2 FL1 + 1 + { 0x7, 2, NULL, NULL, 0 }, + + /* The FLM field in an XFL form instruction. */ + #define FLM FL2 + 1 + { 0xff, 17, NULL, NULL, 0 }, + + /* The FRA field in an X or A form instruction. */ + #define FRA FLM + 1 + #define FRA_MASK (0x1f << 16) + { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, + + /* The FRB field in an X or A form instruction. */ + #define FRB FRA + 1 + #define FRB_MASK (0x1f << 11) + { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, + + /* The FRC field in an A form instruction. */ + #define FRC FRB + 1 + #define FRC_MASK (0x1f << 6) + { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, + + /* The FRS field in an X form instruction or the FRT field in a D, X + or A form instruction. */ + #define FRS FRC + 1 + #define FRT FRS + { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, + + /* The FXM field in an XFX instruction. */ + #define FXM FRS + 1 + { 0xff, 12, insert_fxm, extract_fxm, 0 }, + + /* Power4 version for mfcr. */ + #define FXM4 FXM + 1 + { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, + + /* The L field in a D or X form instruction. */ + #define L FXM4 + 1 + { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The LEV field in a POWER SVC form instruction. */ + #define SVC_LEV L + 1 + { 0x7f, 5, NULL, NULL, 0 }, + + /* The LEV field in an SC form instruction. */ + #define LEV SVC_LEV + 1 + { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The LI field in an I form instruction. The lower two bits are + forced to zero. */ + #define LI LEV + 1 + { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The LI field in an I form instruction when used as an absolute + address. */ + #define LIA LI + 1 + { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + + /* The LS field in an X (sync) form instruction. */ + #define LS LIA + 1 + { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The ME field in an M form instruction. */ + #define ME LS + 1 + #define ME_MASK (0x1f << 1) + { 0x1f, 1, NULL, NULL, 0 }, + + /* The MB and ME fields in an M form instruction expressed a single + operand which is a bitmask indicating which bits to select. This + is a two operand form using PPC_OPERAND_NEXT. See the + description in opcode/ppc.h for what this means. */ + #define MBE ME + 1 + { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, + { -1, 0, insert_mbe, extract_mbe, 0 }, + + /* The MB or ME field in an MD or MDS form instruction. The high + bit is wrapped to the low end. */ + #define MB6 MBE + 2 + #define ME6 MB6 + #define MB6_MASK (0x3f << 5) + { 0x3f, 5, insert_mb6, extract_mb6, 0 }, + + /* The NB field in an X form instruction. The value 32 is stored as + 0. */ + #define NB MB6 + 1 + { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, + + /* The NSI field in a D form instruction. This is the same as the + SI field, only negated. */ + #define NSI NB + 1 + { 0xffff, 0, insert_nsi, extract_nsi, + PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, + + /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ + #define RA NSI + 1 + #define RA_MASK (0x1f << 16) + { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, + + /* As above, but 0 in the RA field means zero, not r0. */ + #define RA0 RA + 1 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, + + /* The RA field in the DQ form lq instruction, which has special + value restrictions. */ + #define RAQ RA0 + 1 + { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, + + /* The RA field in a D or X form instruction which is an updating + load, which means that the RA field may not be zero and may not + equal the RT field. */ + #define RAL RAQ + 1 + { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, + + /* The RA field in an lmw instruction, which has special value + restrictions. */ + #define RAM RAL + 1 + { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, + + /* The RA field in a D or X form instruction which is an updating + store or an updating floating point load, which means that the RA + field may not be zero. */ + #define RAS RAM + 1 + { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, + + /* The RA field of the tlbwe instruction, which is optional. */ + #define RAOPT RAS + 1 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, + + /* The RB field in an X, XO, M, or MDS form instruction. */ + #define RB RAOPT + 1 + #define RB_MASK (0x1f << 11) + { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, + + /* The RB field in an X form instruction when it must be the same as + the RS field in the instruction. This is used for extended + mnemonics like mr. */ + #define RBS RB + 1 + { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, + + /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form + instruction or the RT field in a D, DS, X, XFX or XO form + instruction. */ + #define RS RBS + 1 + #define RT RS + #define RT_MASK (0x1f << 21) + { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, + + /* The RS and RT fields of the DS form stq instruction, which have + special value restrictions. */ + #define RSQ RS + 1 + #define RTQ RSQ + { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 }, + + /* The RS field of the tlbwe instruction, which is optional. */ + #define RSO RSQ + 1 + #define RTO RSO + { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, + + /* The SH field in an X or M form instruction. */ + #define SH RSO + 1 + #define SH_MASK (0x1f << 11) + /* The other UIMM field in a EVX form instruction. */ + #define EVUIMM SH + { 0x1f, 11, NULL, NULL, 0 }, + + /* The SH field in an MD form instruction. This is split. */ + #define SH6 SH + 1 + #define SH6_MASK ((0x1f << 11) | (1 << 1)) + { 0x3f, -1, insert_sh6, extract_sh6, 0 }, + + /* The SH field of the tlbwe instruction, which is optional. */ + #define SHO SH6 + 1 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The SI field in a D form instruction. */ + #define SI SHO + 1 + { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, + + /* The SI field in a D form instruction when we accept a wide range + of positive values. */ + #define SISIGNOPT SI + 1 + { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, + + /* The SPR field in an XFX form instruction. This is flipped--the + lower 5 bits are stored in the upper 5 and vice- versa. */ + #define SPR SISIGNOPT + 1 + #define PMR SPR + #define SPR_MASK (0x3ff << 11) + { 0x3ff, 11, insert_spr, extract_spr, 0 }, + + /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ + #define SPRBAT SPR + 1 + #define SPRBAT_MASK (0x3 << 17) + { 0x3, 17, NULL, NULL, 0 }, + + /* The SPRG register number in an XFX form m[ft]sprg instruction. */ + #define SPRG SPRBAT + 1 + { 0x1f, 16, insert_sprg, extract_sprg, 0 }, + + /* The SR field in an X form instruction. */ + #define SR SPRG + 1 + { 0xf, 16, NULL, NULL, 0 }, + + /* The STRM field in an X AltiVec form instruction. */ + #define STRM SR + 1 + { 0x3, 21, NULL, NULL, 0 }, + + /* The SV field in a POWER SC form instruction. */ + #define SV STRM + 1 + { 0x3fff, 2, NULL, NULL, 0 }, + + /* The TBR field in an XFX form instruction. This is like the SPR + field, but it is optional. */ + #define TBR SV + 1 + { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, + + /* The TO field in a D or X form instruction. */ + #define TO TBR + 1 + #define TO_MASK (0x1f << 21) + { 0x1f, 21, NULL, NULL, 0 }, + + /* The UI field in a D form instruction. */ + #define UI TO + 1 + { 0xffff, 0, NULL, NULL, 0 }, + + /* The VA field in a VA, VX or VXR form instruction. */ + #define VA UI + 1 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, + + /* The VB field in a VA, VX or VXR form instruction. */ + #define VB VA + 1 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, + + /* The VC field in a VA form instruction. */ + #define VC VB + 1 + { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, + + /* The VD or VS field in a VA, VX, VXR or X form instruction. */ + #define VD VC + 1 + #define VS VD + { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, + + /* The SIMM field in a VX form instruction. */ + #define SIMM VD + 1 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, + + /* The UIMM field in a VX form instruction, and TE in Z form. */ + #define UIMM SIMM + 1 + #define TE UIMM + { 0x1f, 16, NULL, NULL, 0 }, + + /* The SHB field in a VA form instruction. */ + #define SHB UIMM + 1 + { 0xf, 6, NULL, NULL, 0 }, + + /* The other UIMM field in a half word EVX form instruction. */ + #define EVUIMM_2 SHB + 1 + { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, + + /* The other UIMM field in a word EVX form instruction. */ + #define EVUIMM_4 EVUIMM_2 + 1 + { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, + + /* The other UIMM field in a double EVX form instruction. */ + #define EVUIMM_8 EVUIMM_4 + 1 + { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, + + /* The WS field. */ + #define WS EVUIMM_8 + 1 + { 0x7, 11, NULL, NULL, 0 }, + + /* The L field in an mtmsrd or A form instruction or W in an X form. */ + #define A_L WS + 1 + #define W A_L + { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + #define RMC A_L + 1 + { 0x3, 9, NULL, NULL, 0 }, + + #define R RMC + 1 + { 0x1, 16, NULL, NULL, 0 }, + + #define SP R + 1 + { 0x3, 19, NULL, NULL, 0 }, + + #define S SP + 1 + { 0x1, 20, NULL, NULL, 0 }, + + /* SH field starting at bit position 16. */ + #define SH16 S + 1 + /* The DCM and DGM fields in a Z form instruction. */ + #define DCM SH16 + #define DGM DCM + { 0x3f, 10, NULL, NULL, 0 }, + + /* The EH field in larx instruction. */ + #define EH SH16 + 1 + { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The L field in an mtfsf or XFL form instruction. */ + #define XFL_L EH + 1 + { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, }; -const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) - / sizeof (powerpc_operands[0])); +const unsigned int num_powerpc_operands = (sizeof(powerpc_operands) + / sizeof(powerpc_operands[0])); /* The functions used to insert and extract complicated operands. */ @@ -878,22 +880,22 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) same. */ static unsigned long -insert_bat (unsigned long insn, - long value ATTRIBUTE_UNUSED, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +insert_bat(unsigned long insn, + long value ATTRIBUTE_UNUSED, + int dialect ATTRIBUTE_UNUSED, + const char** errmsg ATTRIBUTE_UNUSED) { - return insn | (((insn >> 21) & 0x1f) << 16); + return insn | (((insn >> 21) & 0x1f) << 16); } static long -extract_bat (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid) +extract_bat(unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int* invalid) { - if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) - *invalid = 1; - return 0; + if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) + *invalid = 1; + return 0; } /* The BB field in an XL form instruction when it must be the same as @@ -903,22 +905,22 @@ extract_bat (unsigned long insn, same. */ static unsigned long -insert_bba (unsigned long insn, - long value ATTRIBUTE_UNUSED, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +insert_bba(unsigned long insn, + long value ATTRIBUTE_UNUSED, + int dialect ATTRIBUTE_UNUSED, + const char** errmsg ATTRIBUTE_UNUSED) { - return insn | (((insn >> 16) & 0x1f) << 11); + return insn | (((insn >> 16) & 0x1f) << 11); } static long -extract_bba (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid) +extract_bba(unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int* invalid) { - if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) - *invalid = 1; - return 0; + if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) + *invalid = 1; + return 0; } /* The BD field in a B form instruction when the - modifier is used. @@ -939,44 +941,44 @@ extract_bba (unsigned long insn, be valid. */ static unsigned long -insert_bdm (unsigned long insn, - long value, - int dialect, - const char **errmsg ATTRIBUTE_UNUSED) +insert_bdm(unsigned long insn, + long value, + int dialect, + const char** errmsg ATTRIBUTE_UNUSED) { - if ((dialect & PPC_OPCODE_POWER4) == 0) + if ((dialect & PPC_OPCODE_POWER4) == 0) { - if ((value & 0x8000) != 0) - insn |= 1 << 21; + if ((value & 0x8000) != 0) + insn |= 1 << 21; } - else + else { - if ((insn & (0x14 << 21)) == (0x04 << 21)) - insn |= 0x02 << 21; - else if ((insn & (0x14 << 21)) == (0x10 << 21)) - insn |= 0x08 << 21; + if ((insn & (0x14 << 21)) == (0x04 << 21)) + insn |= 0x02 << 21; + else if ((insn & (0x14 << 21)) == (0x10 << 21)) + insn |= 0x08 << 21; } - return insn | (value & 0xfffc); + return insn | (value & 0xfffc); } static long -extract_bdm (unsigned long insn, - int dialect, - int *invalid) +extract_bdm(unsigned long insn, + int dialect, + int* invalid) { - if ((dialect & PPC_OPCODE_POWER4) == 0) + if ((dialect & PPC_OPCODE_POWER4) == 0) { - if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) - *invalid = 1; + if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) + *invalid = 1; } - else + else { - if ((insn & (0x17 << 21)) != (0x06 << 21) - && (insn & (0x1d << 21)) != (0x18 << 21)) - *invalid = 1; + if ((insn & (0x17 << 21)) != (0x06 << 21) + && (insn & (0x1d << 21)) != (0x18 << 21)) + *invalid = 1; } - return ((insn & 0xfffc) ^ 0x8000) - 0x8000; + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; } /* The BD field in a B form instruction when the + modifier is used. @@ -984,130 +986,130 @@ extract_bdm (unsigned long insn, taken. */ static unsigned long -insert_bdp (unsigned long insn, - long value, - int dialect, - const char **errmsg ATTRIBUTE_UNUSED) +insert_bdp(unsigned long insn, + long value, + int dialect, + const char** errmsg ATTRIBUTE_UNUSED) { - if ((dialect & PPC_OPCODE_POWER4) == 0) + if ((dialect & PPC_OPCODE_POWER4) == 0) { - if ((value & 0x8000) == 0) - insn |= 1 << 21; + if ((value & 0x8000) == 0) + insn |= 1 << 21; } - else + else { - if ((insn & (0x14 << 21)) == (0x04 << 21)) - insn |= 0x03 << 21; - else if ((insn & (0x14 << 21)) == (0x10 << 21)) - insn |= 0x09 << 21; + if ((insn & (0x14 << 21)) == (0x04 << 21)) + insn |= 0x03 << 21; + else if ((insn & (0x14 << 21)) == (0x10 << 21)) + insn |= 0x09 << 21; } - return insn | (value & 0xfffc); + return insn | (value & 0xfffc); } static long -extract_bdp (unsigned long insn, - int dialect, - int *invalid) +extract_bdp(unsigned long insn, + int dialect, + int* invalid) { - if ((dialect & PPC_OPCODE_POWER4) == 0) + if ((dialect & PPC_OPCODE_POWER4) == 0) { - if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) - *invalid = 1; + if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) + *invalid = 1; } - else + else { - if ((insn & (0x17 << 21)) != (0x07 << 21) - && (insn & (0x1d << 21)) != (0x19 << 21)) - *invalid = 1; + if ((insn & (0x17 << 21)) != (0x07 << 21) + && (insn & (0x1d << 21)) != (0x19 << 21)) + *invalid = 1; } - return ((insn & 0xfffc) ^ 0x8000) - 0x8000; + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; } /* Check for legal values of a BO field. */ static int -valid_bo (long value, int dialect, int extract) +valid_bo(long value, int dialect, int extract) { - if ((dialect & PPC_OPCODE_POWER4) == 0) + if ((dialect & PPC_OPCODE_POWER4) == 0) { - int valid; - /* Certain encodings have bits that are required to be zero. - These are (z must be zero, y may be anything): - 001zy - 011zy - 1z00y - 1z01y - 1z1zz - */ - switch (value & 0x14) - { - default: - case 0: - valid = 1; - break; - case 0x4: - valid = (value & 0x2) == 0; - break; - case 0x10: - valid = (value & 0x8) == 0; - break; - case 0x14: - valid = value == 0x14; - break; - } - /* When disassembling with -Many, accept power4 encodings too. */ - if (valid - || (dialect & PPC_OPCODE_ANY) == 0 - || !extract) - return valid; + int valid; + /* Certain encodings have bits that are required to be zero. + These are (z must be zero, y may be anything): + 001zy + 011zy + 1z00y + 1z01y + 1z1zz + */ + switch (value & 0x14) + { + default: + case 0: + valid = 1; + break; + case 0x4: + valid = (value & 0x2) == 0; + break; + case 0x10: + valid = (value & 0x8) == 0; + break; + case 0x14: + valid = value == 0x14; + break; + } + /* When disassembling with -Many, accept power4 encodings too. */ + if (valid + || (dialect & PPC_OPCODE_ANY) == 0 + || !extract) + return valid; } - /* Certain encodings have bits that are required to be zero. - These are (z must be zero, a & t may be anything): - 0000z - 0001z - 0100z - 0101z - 001at - 011at - 1a00t - 1a01t - 1z1zz - */ - if ((value & 0x14) == 0) - return (value & 0x1) == 0; - else if ((value & 0x14) == 0x14) - return value == 0x14; - else - return 1; + /* Certain encodings have bits that are required to be zero. + These are (z must be zero, a & t may be anything): + 0000z + 0001z + 0100z + 0101z + 001at + 011at + 1a00t + 1a01t + 1z1zz + */ + if ((value & 0x14) == 0) + return (value & 0x1) == 0; + else if ((value & 0x14) == 0x14) + return value == 0x14; + else + return 1; } /* The BO field in a B form instruction. Warn about attempts to set the field to an illegal value. */ static unsigned long -insert_bo (unsigned long insn, - long value, - int dialect, - const char **errmsg) +insert_bo(unsigned long insn, + long value, + int dialect, + const char** errmsg) { - if (!valid_bo (value, dialect, 0)) - *errmsg = _("invalid conditional option"); - return insn | ((value & 0x1f) << 21); + if (!valid_bo(value, dialect, 0)) + *errmsg = _("invalid conditional option"); + return insn | ((value & 0x1f) << 21); } static long -extract_bo (unsigned long insn, - int dialect, - int *invalid) +extract_bo(unsigned long insn, + int dialect, + int* invalid) { - long value; + long value; - value = (insn >> 21) & 0x1f; - if (!valid_bo (value, dialect, 1)) - *invalid = 1; - return value; + value = (insn >> 21) & 0x1f; + if (!valid_bo(value, dialect, 1)) + *invalid = 1; + return value; } /* The BO field in a B form instruction when the + or - modifier is @@ -1115,102 +1117,102 @@ extract_bo (unsigned long insn, extracting it, we force it to be even. */ static unsigned long -insert_boe (unsigned long insn, - long value, - int dialect, - const char **errmsg) +insert_boe(unsigned long insn, + long value, + int dialect, + const char** errmsg) { - if (!valid_bo (value, dialect, 0)) - *errmsg = _("invalid conditional option"); - else if ((value & 1) != 0) - *errmsg = _("attempt to set y bit when using + or - modifier"); + if (!valid_bo(value, dialect, 0)) + *errmsg = _("invalid conditional option"); + else if ((value & 1) != 0) + *errmsg = _("attempt to set y bit when using + or - modifier"); - return insn | ((value & 0x1f) << 21); + return insn | ((value & 0x1f) << 21); } static long -extract_boe (unsigned long insn, - int dialect, - int *invalid) +extract_boe(unsigned long insn, + int dialect, + int* invalid) { - long value; + long value; - value = (insn >> 21) & 0x1f; - if (!valid_bo (value, dialect, 1)) - *invalid = 1; - return value & 0x1e; + value = (insn >> 21) & 0x1f; + if (!valid_bo(value, dialect, 1)) + *invalid = 1; + return value & 0x1e; } /* FXM mask in mfcr and mtcrf instructions. */ static unsigned long -insert_fxm (unsigned long insn, - long value, - int dialect, - const char **errmsg) +insert_fxm(unsigned long insn, + long value, + int dialect, + const char** errmsg) { - /* If we're handling the mfocrf and mtocrf insns ensure that exactly - one bit of the mask field is set. */ - if ((insn & (1 << 20)) != 0) + /* If we're handling the mfocrf and mtocrf insns ensure that exactly + one bit of the mask field is set. */ + if ((insn & (1 << 20)) != 0) { - if (value == 0 || (value & -value) != value) - { - *errmsg = _("invalid mask field"); - value = 0; - } + if (value == 0 || (value & -value) != value) + { + *errmsg = _("invalid mask field"); + value = 0; + } } - /* If the optional field on mfcr is missing that means we want to use - the old form of the instruction that moves the whole cr. In that - case we'll have VALUE zero. There doesn't seem to be a way to - distinguish this from the case where someone writes mfcr %r3,0. */ - else if (value == 0) - ; + /* If the optional field on mfcr is missing that means we want to use + the old form of the instruction that moves the whole cr. In that + case we'll have VALUE zero. There doesn't seem to be a way to + distinguish this from the case where someone writes mfcr %r3,0. */ + else if (value == 0) + ; - /* If only one bit of the FXM field is set, we can use the new form - of the instruction, which is faster. Unlike the Power4 branch hint - encoding, this is not backward compatible. Do not generate the - new form unless -mpower4 has been given, or -many and the two - operand form of mfcr was used. */ - else if ((value & -value) == value - && ((dialect & PPC_OPCODE_POWER4) != 0 - || ((dialect & PPC_OPCODE_ANY) != 0 - && (insn & (0x3ff << 1)) == 19 << 1))) - insn |= 1 << 20; + /* If only one bit of the FXM field is set, we can use the new form + of the instruction, which is faster. Unlike the Power4 branch hint + encoding, this is not backward compatible. Do not generate the + new form unless -mpower4 has been given, or -many and the two + operand form of mfcr was used. */ + else if ((value & -value) == value + && ((dialect & PPC_OPCODE_POWER4) != 0 + || ((dialect & PPC_OPCODE_ANY) != 0 + && (insn & (0x3ff << 1)) == 19 << 1))) + insn |= 1 << 20; - /* Any other value on mfcr is an error. */ - else if ((insn & (0x3ff << 1)) == 19 << 1) + /* Any other value on mfcr is an error. */ + else if ((insn & (0x3ff << 1)) == 19 << 1) { - *errmsg = _("ignoring invalid mfcr mask"); - value = 0; + *errmsg = _("ignoring invalid mfcr mask"); + value = 0; } - return insn | ((value & 0xff) << 12); + return insn | ((value & 0xff) << 12); } static long -extract_fxm (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid) +extract_fxm(unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int* invalid) { - long mask = (insn >> 12) & 0xff; + long mask = (insn >> 12) & 0xff; - /* Is this a Power4 insn? */ - if ((insn & (1 << 20)) != 0) + /* Is this a Power4 insn? */ + if ((insn & (1 << 20)) != 0) { - /* Exactly one bit of MASK should be set. */ - if (mask == 0 || (mask & -mask) != mask) - *invalid = 1; + /* Exactly one bit of MASK should be set. */ + if (mask == 0 || (mask & -mask) != mask) + *invalid = 1; } - /* Check that non-power4 form of mfcr has a zero MASK. */ - else if ((insn & (0x3ff << 1)) == 19 << 1) + /* Check that non-power4 form of mfcr has a zero MASK. */ + else if ((insn & (0x3ff << 1)) == 19 << 1) { - if (mask != 0) - *invalid = 1; + if (mask != 0) + *invalid = 1; } - return mask; + return mask; } /* The MB and ME fields in an M form instruction expressed as a single @@ -1219,122 +1221,122 @@ extract_fxm (unsigned long insn, instruction which uses a field of this type. */ static unsigned long -insert_mbe (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) +insert_mbe(unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char** errmsg) { - unsigned long uval, mask; - int mb, me, mx, count, last; + unsigned long uval, mask; + int mb, me, mx, count, last; - uval = value; + uval = value; - if (uval == 0) + if (uval == 0) { - *errmsg = _("illegal bitmask"); - return insn; + *errmsg = _("illegal bitmask"); + return insn; } - mb = 0; - me = 32; - if ((uval & 1) != 0) - last = 1; - else - last = 0; - count = 0; - - /* mb: location of last 0->1 transition */ - /* me: location of last 1->0 transition */ - /* count: # transitions */ - - for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) - { - if ((uval & mask) && !last) - { - ++count; - mb = mx; - last = 1; - } - else if (!(uval & mask) && last) - { - ++count; - me = mx; - last = 0; - } - } - if (me == 0) + mb = 0; me = 32; + if ((uval & 1) != 0) + last = 1; + else + last = 0; + count = 0; - if (count != 2 && (count != 0 || ! last)) - *errmsg = _("illegal bitmask"); + /* mb: location of last 0->1 transition */ + /* me: location of last 1->0 transition */ + /* count: # transitions */ - return insn | (mb << 6) | ((me - 1) << 1); + for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) + { + if ((uval & mask) && !last) + { + ++count; + mb = mx; + last = 1; + } + else if (!(uval & mask) && last) + { + ++count; + me = mx; + last = 0; + } + } + if (me == 0) + me = 32; + + if (count != 2 && (count != 0 || !last)) + *errmsg = _("illegal bitmask"); + + return insn | (mb << 6) | ((me - 1) << 1); } static long -extract_mbe (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid) +extract_mbe(unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int* invalid) { - long ret; - int mb, me; - int i; + long ret; + int mb, me; + int i; - *invalid = 1; + *invalid = 1; - mb = (insn >> 6) & 0x1f; - me = (insn >> 1) & 0x1f; - if (mb < me + 1) + mb = (insn >> 6) & 0x1f; + me = (insn >> 1) & 0x1f; + if (mb < me + 1) { - ret = 0; - for (i = mb; i <= me; i++) - ret |= 1L << (31 - i); + ret = 0; + for (i = mb; i <= me; i++) + ret |= 1L << (31 - i); } - else if (mb == me + 1) - ret = ~0; - else /* (mb > me + 1) */ + else if (mb == me + 1) + ret = ~0; + else /* (mb > me + 1) */ { - ret = ~0; - for (i = me + 1; i < mb; i++) - ret &= ~(1L << (31 - i)); + ret = ~0; + for (i = me + 1; i < mb; i++) + ret &= ~(1L << (31 - i)); } - return ret; + return ret; } /* The MB or ME field in an MD or MDS form instruction. The high bit is wrapped to the low end. */ static unsigned long -insert_mb6 (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +insert_mb6(unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char** errmsg ATTRIBUTE_UNUSED) { - return insn | ((value & 0x1f) << 6) | (value & 0x20); + return insn | ((value & 0x1f) << 6) | (value & 0x20); } static long -extract_mb6 (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) +extract_mb6(unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int* invalid ATTRIBUTE_UNUSED) { - return ((insn >> 6) & 0x1f) | (insn & 0x20); + return ((insn >> 6) & 0x1f) | (insn & 0x20); } /* The NB field in an X form instruction. The value 32 is stored as 0. */ static long -extract_nb (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) +extract_nb(unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int* invalid ATTRIBUTE_UNUSED) { - long ret; + long ret; - ret = (insn >> 11) & 0x1f; - if (ret == 0) - ret = 32; - return ret; + ret = (insn >> 11) & 0x1f; + if (ret == 0) + ret = 32; + return ret; } /* The NSI field in a D form instruction. This is the same as the SI @@ -1343,21 +1345,21 @@ extract_nb (unsigned long insn, a field of this type. */ static unsigned long -insert_nsi (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +insert_nsi(unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char** errmsg ATTRIBUTE_UNUSED) { - return insn | (-value & 0xffff); + return insn | (-value & 0xffff); } static long -extract_nsi (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid) +extract_nsi(unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int* invalid) { - *invalid = 1; - return -(((insn & 0xffff) ^ 0x8000) - 0x8000); + *invalid = 1; + return -(((insn & 0xffff) ^ 0x8000) - 0x8000); } /* The RA field in a D or X form instruction which is an updating @@ -1365,45 +1367,45 @@ extract_nsi (unsigned long insn, equal the RT field. */ static unsigned long -insert_ral (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) +insert_ral(unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char** errmsg) { - if (value == 0 - || (unsigned long) value == ((insn >> 21) & 0x1f)) - *errmsg = "invalid register operand when updating"; - return insn | ((value & 0x1f) << 16); + if (value == 0 + || (unsigned long)value == ((insn >> 21) & 0x1f)) + *errmsg = "invalid register operand when updating"; + return insn | ((value & 0x1f) << 16); } /* The RA field in an lmw instruction, which has special value restrictions. */ static unsigned long -insert_ram (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) +insert_ram(unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char** errmsg) { - if ((unsigned long) value >= ((insn >> 21) & 0x1f)) - *errmsg = _("index register in load range"); - return insn | ((value & 0x1f) << 16); + if ((unsigned long)value >= ((insn >> 21) & 0x1f)) + *errmsg = _("index register in load range"); + return insn | ((value & 0x1f) << 16); } /* The RA field in the DQ form lq instruction, which has special value restrictions. */ static unsigned long -insert_raq (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) +insert_raq(unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char** errmsg) { - long rtvalue = (insn & RT_MASK) >> 21; + long rtvalue = (insn & RT_MASK) >> 21; - if (value == rtvalue) - *errmsg = _("source and target register operands must be different"); - return insn | ((value & 0x1f) << 16); + if (value == rtvalue) + *errmsg = _("source and target register operands must be different"); + return insn | ((value & 0x1f) << 16); } /* The RA field in a D or X form instruction which is an updating @@ -1411,14 +1413,14 @@ insert_raq (unsigned long insn, field may not be zero. */ static unsigned long -insert_ras (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) +insert_ras(unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char** errmsg) { - if (value == 0) - *errmsg = _("invalid register operand when updating"); - return insn | ((value & 0x1f) << 16); + if (value == 0) + *errmsg = _("invalid register operand when updating"); + return insn | ((value & 0x1f) << 16); } /* The RB field in an X form instruction when it must be the same as @@ -1428,102 +1430,102 @@ insert_ras (unsigned long insn, extraction function just checks that the fields are the same. */ static unsigned long -insert_rbs (unsigned long insn, - long value ATTRIBUTE_UNUSED, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +insert_rbs(unsigned long insn, + long value ATTRIBUTE_UNUSED, + int dialect ATTRIBUTE_UNUSED, + const char** errmsg ATTRIBUTE_UNUSED) { - return insn | (((insn >> 21) & 0x1f) << 11); + return insn | (((insn >> 21) & 0x1f) << 11); } static long -extract_rbs (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid) +extract_rbs(unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int* invalid) { - if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) - *invalid = 1; - return 0; + if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) + *invalid = 1; + return 0; } /* The SH field in an MD form instruction. This is split. */ static unsigned long -insert_sh6 (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +insert_sh6(unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char** errmsg ATTRIBUTE_UNUSED) { - return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); + return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); } static long -extract_sh6 (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) +extract_sh6(unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int* invalid ATTRIBUTE_UNUSED) { - return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); + return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); } /* The SPR field in an XFX form instruction. This is flipped--the lower 5 bits are stored in the upper 5 and vice- versa. */ static unsigned long -insert_spr (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +insert_spr(unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char** errmsg ATTRIBUTE_UNUSED) { - return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); + return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); } static long -extract_spr (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) +extract_spr(unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int* invalid ATTRIBUTE_UNUSED) { - return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); + return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); } /* Some dialects have 8 SPRG registers instead of the standard 4. */ static unsigned long -insert_sprg (unsigned long insn, - long value, - int dialect, - const char **errmsg) +insert_sprg(unsigned long insn, + long value, + int dialect, + const char** errmsg) { - /* This check uses PPC_OPCODE_403 because PPC405 is later defined - as a synonym. If ever a 405 specific dialect is added this - check should use that instead. */ - if (value > 7 - || (value > 3 - && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0)) - *errmsg = _("invalid sprg number"); + /* This check uses PPC_OPCODE_403 because PPC405 is later defined + as a synonym. If ever a 405 specific dialect is added this + check should use that instead. */ + if (value > 7 + || (value > 3 + && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0)) + *errmsg = _("invalid sprg number"); - /* If this is mfsprg4..7 then use spr 260..263 which can be read in - user mode. Anything else must use spr 272..279. */ - if (value <= 3 || (insn & 0x100) != 0) - value |= 0x10; + /* If this is mfsprg4..7 then use spr 260..263 which can be read in + user mode. Anything else must use spr 272..279. */ + if (value <= 3 || (insn & 0x100) != 0) + value |= 0x10; - return insn | ((value & 0x17) << 16); + return insn | ((value & 0x17) << 16); } static long -extract_sprg (unsigned long insn, - int dialect, - int *invalid) +extract_sprg(unsigned long insn, + int dialect, + int* invalid) { - unsigned long val = (insn >> 16) & 0x1f; + unsigned long val = (insn >> 16) & 0x1f; - /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 - If not BOOKE or 405, then both use only 272..275. */ - if (val <= 3 - || (val < 0x10 && (insn & 0x100) != 0) - || (val - 0x10 > 3 - && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0)) - *invalid = 1; - return val & 7; + /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 + If not BOOKE or 405, then both use only 272..275. */ + if (val <= 3 + || (val < 0x10 && (insn & 0x100) != 0) + || (val - 0x10 > 3 + && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0)) + *invalid = 1; + return val & 7; } /* The TBR field in an XFX instruction. This is just like SPR, but it @@ -1537,27 +1539,27 @@ extract_sprg (unsigned long insn, #define TB (268) static unsigned long -insert_tbr (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +insert_tbr(unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char** errmsg ATTRIBUTE_UNUSED) { - if (value == 0) - value = TB; - return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); + if (value == 0) + value = TB; + return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); } static long -extract_tbr (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) +extract_tbr(unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int* invalid ATTRIBUTE_UNUSED) { - long ret; + long ret; - ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); - if (ret == TB) - ret = 0; - return ret; + ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); + if (ret == TB) + ret = 0; + return ret; } /* Macros used to form opcodes. */ @@ -1572,13 +1574,13 @@ extract_tbr (unsigned long insn, #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) #define OPTO_MASK (OP_MASK | TO_MASK) -/* The main opcode combined with a comparison size bit in the L field - of a D form or X form instruction. Used for extended mnemonics for - the comparison instructions. */ + /* The main opcode combined with a comparison size bit in the L field + of a D form or X form instruction. Used for extended mnemonics for + the comparison instructions. */ #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) #define OPL_MASK OPL (0x3f,1) -/* An A form instruction. */ + /* An A form instruction. */ #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) #define A_MASK A (0x3f, 0x1f, 1) @@ -1611,13 +1613,13 @@ extract_tbr (unsigned long insn, #define BBOY_MASK (BBO_MASK &~ Y_MASK) #define BBOAT_MASK (BBO_MASK &~ AT1_MASK) -/* A B form instruction setting the BO field and the condition bits of - the BI field. */ + /* A B form instruction setting the BO field and the condition bits of + the BI field. */ #define BBOCB(op, bo, cb, aa, lk) \ (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) -/* A BBOCB_MASK with the y bit of the BO field removed. */ + /* A BBOCB_MASK with the y bit of the BO field removed. */ #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) @@ -1757,7 +1759,7 @@ extract_tbr (unsigned long insn, fixed. */ #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) -/* An X form trap instruction with the TO field specified. */ + /* An X form trap instruction with the TO field specified. */ #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) #define XTO_MASK (X_MASK | TO_MASK) @@ -1805,13 +1807,13 @@ extract_tbr (unsigned long insn, #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) #define XLYLK_MASK (XL_MASK | Y_MASK) -/* An XL form instruction which sets the BO field and the condition - bits of the BI field. */ + /* An XL form instruction which sets the BO field and the condition + bits of the BI field. */ #define XLOCB(op, bo, cb, xop, lk) \ (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) -/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ + /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ #define XLBB_MASK (XL_MASK | BB_MASK) #define XLYBB_MASK (XLYLK_MASK | BB_MASK) #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) @@ -1854,11 +1856,11 @@ extract_tbr (unsigned long insn, SPRBAT field. */ #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) -/* An XFX form instruction with the SPR field filled in except for the - SPRG field. */ + /* An XFX form instruction with the SPR field filled in except for the + SPRG field. */ #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) -/* An X form instruction with everything filled in except the E field. */ + /* An X form instruction with everything filled in except the E field. */ #define XE_MASK (0xffff7fff) /* An X form user context instruction. */ @@ -1902,7 +1904,7 @@ extract_tbr (unsigned long insn, #define CBEQ (2) #define CBSO (3) -/* The TO encodings used in extended trap mnemonics. */ + /* The TO encodings used in extended trap mnemonics. */ #define TOLGT (0x1) #define TOLLT (0x2) #define TOEQ (0x4) @@ -1960,3036 +1962,3039 @@ extract_tbr (unsigned long insn, #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64 #define PPCRFMCI PPC_OPCODE_RFMCI -/* The opcode table. + /* The opcode table. - The format of the opcode table is: + The format of the opcode table is: - NAME OPCODE MASK FLAGS { OPERANDS } + NAME OPCODE MASK FLAGS { OPERANDS } - NAME is the name of the instruction. - OPCODE is the instruction opcode. - MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. - FLAGS are flags indicated what processors support the instruction. - OPERANDS is the list of operands. + NAME is the name of the instruction. + OPCODE is the instruction opcode. + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + FLAGS are flags indicated what processors support the instruction. + OPERANDS is the list of operands. - The disassembler reads the table in order and prints the first - instruction which matches, so this table is sorted to put more - specific instructions before more general instructions. It is also - sorted by major opcode. */ + The disassembler reads the table in order and prints the first + instruction which matches, so this table is sorted to put more + specific instructions before more general instructions. It is also + sorted by major opcode. */ const struct powerpc_opcode powerpc_opcodes[] = { -{ "attn", X(0,256), X_MASK, POWER4, { 0 } }, -{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } }, - -{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, -{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, - -{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, -{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, - - /* Double-precision opcodes. */ - /* Some of these conflict with AltiVec, so move them before, since - PPCVEC includes the PPC_OPCODE_PPC set. */ -{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } }, -{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } }, -{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } }, -{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } }, -{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } }, -{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } }, -{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } }, -{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } }, -{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } }, - /* End of double-precision opcodes. */ - -{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } }, -{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } }, -{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, -{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, -{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } }, -{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } }, -{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } }, -{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } }, -{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } }, -{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } }, -{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } }, -{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } }, -{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } }, -{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } }, -{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } }, -{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } }, -{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } }, -{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } }, -{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } }, -{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, -{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, - -{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } }, -{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } }, -{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } }, -{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } }, -{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } }, -{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } }, -{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } }, -{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } }, -{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } }, -{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } }, -{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } }, - -{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } }, -{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } }, -{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, -{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, -{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, -{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, -{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } }, -{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } }, -{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } }, - -{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, -{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, -{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, -{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, -{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, -{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, -{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, -{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, -{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, -{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } }, -{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } }, -{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } }, -{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } }, - -{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } }, -{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } }, -{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } }, -{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } }, -{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } }, -{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } }, -{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } }, -{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } }, -{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } }, -{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } }, -{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } }, -{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } }, -{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } }, -{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } }, -{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } }, -{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } }, -{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } }, - -{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } }, -{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } }, -{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } }, -{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } }, - -{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } }, -{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } }, -{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } }, -{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } }, - -{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } }, - -{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, - -{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } }, - -{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } }, - -{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } }, -{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } }, -{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } }, -{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } }, - -{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, -{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, -{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, -{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, - -{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, -{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, -{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, -{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, - -{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } }, -{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } }, - -{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } }, -{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } }, - -{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, -{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } }, -{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } }, -{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } }, -{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } }, -{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } }, - -{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, -{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, -{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } }, -{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } }, -{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } }, - -{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, -{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, -{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, -{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } }, -{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, -{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, -{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, -{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } }, -{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, -{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, -{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, -{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } }, -{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, -{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, -{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, -{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } }, -{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, -{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, -{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, -{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, -{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, -{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, -{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, -{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, -{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, -{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, -{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, -{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, -{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, -{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, -{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, -{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, -{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, -{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, -{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, -{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, -{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, -{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, -{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, -{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, -{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, -{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, -{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, -{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, -{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, -{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, -{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, -{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, -{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, -{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, -{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, -{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, -{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, -{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, -{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, -{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, -{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, -{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, -{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, -{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, -{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, -{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, -{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, -{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, -{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, -{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, -{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, -{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, -{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } }, -{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } }, -{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } }, -{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } }, -{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } }, -{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } }, -{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } }, -{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } }, -{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } }, -{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } }, -{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } }, -{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, - -{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } }, -{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, -{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, -{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } }, -{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, - -{ "b", B(18,0,0), B_MASK, COM, { LI } }, -{ "bl", B(18,0,1), B_MASK, COM, { LI } }, -{ "ba", B(18,1,0), B_MASK, COM, { LIA } }, -{ "bla", B(18,1,1), B_MASK, COM, { LIA } }, - -{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } }, - -{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } }, -{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, -{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } }, -{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } }, -{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, -{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } }, -{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } }, -{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, -{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } }, -{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } }, -{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, -{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } }, -{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } }, -{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, -{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, -{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, -{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, -{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, -{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } }, -{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } }, - -{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } }, - -{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, -{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, -{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, - -{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, -{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } }, - -{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, - -{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } }, - -{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, -{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } }, - -{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } }, -{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } }, - -{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } }, - -{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, - -{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } }, - -{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, -{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, - -{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 } }, - -{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, - -{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 } }, - -{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, -{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, - -{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } }, -{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } }, - -{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, -{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, -{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } }, -{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } }, -{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } }, -{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } }, -{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } }, -{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } }, -{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, -{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, -{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, -{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, -{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, -{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, -{ "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } }, -{ "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } }, - -{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, -{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, - -{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, -{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, - -{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } }, -{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, -{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, -{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, -{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } }, -{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } }, -{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, -{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, - -{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } }, -{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } }, - -{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } }, -{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } }, -{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } }, -{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } }, - -{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, -{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, -{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, -{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } }, -{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, -{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, - -{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, -{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } }, -{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } }, -{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, -{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } }, -{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } }, -{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, - -{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, -{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, - -{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, -{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, - -{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, -{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, - -{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } }, -{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, -{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } }, -{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, - -{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, -{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, - -{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, -{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, -{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, -{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, - -{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } }, -{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } }, -{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } }, -{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } }, -{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } }, - -{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } }, -{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, - -{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } }, - -{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, - -{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } }, -{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } }, -{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } }, -{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, - -{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } }, -{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } }, -{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } }, - -{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } }, - -{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } }, - -{ "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } }, -{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, - -{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } }, -{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, - -{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } }, -{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } }, - -{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } }, -{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } }, -{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } }, -{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } }, - -{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } }, -{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } }, - -{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } }, -{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } }, - -{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } }, -{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } }, - -{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } }, - -{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } }, - -{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, -{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, -{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, -{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, - -{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, +{ "attn", X(0,256), X_MASK, POWER4, { 0 }, PPC_INST_ATTN }, +{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDLGTI }, +{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDLLTI }, +{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDEQI }, +{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDLGEI }, +{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDLNLI }, +{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDLLEI }, +{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDLNGI }, +{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDGTI }, +{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDGEI }, +{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDNLI }, +{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDLTI }, +{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDLEI }, +{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDNGI }, +{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI }, PPC_INST_TDNEI }, +{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI }, PPC_INST_TDI }, + +{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWLGTI }, +{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TLGTI }, +{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWLLTI }, +{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TLLTI }, +{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWEQI }, +{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TEQI }, +{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWLGEI }, +{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TLGEI }, +{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWLNLI }, +{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TLNLI }, +{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWLLEI }, +{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TLLEI }, +{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWLNGI }, +{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TLNGI }, +{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWGTI }, +{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TGTI }, +{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWGEI }, +{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TGEI }, +{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWNLI }, +{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TNLI }, +{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWLTI }, +{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TLTI }, +{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWLEI }, +{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TLEI }, +{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWNGI }, +{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TNGI }, +{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI }, PPC_INST_TWNEI }, +{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI }, PPC_INST_TNEI }, +{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI }, PPC_INST_TWI }, +{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI }, PPC_INST_TI }, + +{ "macchw", XO(4,172,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHW }, +{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHW }, +{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWO }, +{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWO }, +{ "macchws", XO(4,236,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWS }, +{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWS }, +{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWSO }, +{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWSO }, +{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWSU }, +{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWSU }, +{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWSUO }, +{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWSUO }, +{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWU }, +{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWU }, +{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWUO }, +{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACCHWUO }, +{ "machhw", XO(4,44,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHW }, +{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHW }, +{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWO }, +{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWO }, +{ "machhws", XO(4,108,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWS }, +{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWS }, +{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWSO }, +{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWSO }, +{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWSU }, +{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWSU }, +{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWSUO }, +{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWSUO }, +{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWU }, +{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWU }, +{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWUO }, +{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACHHWUO }, +{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHW }, +{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHW }, +{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWO }, +{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWO }, +{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWS }, +{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWS }, +{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWSO }, +{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWSO }, +{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWSU }, +{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWSU }, +{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWSUO }, +{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWSUO }, +{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWU }, +{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWU }, +{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWUO }, +{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWUO }, +{ "mulchw", XRC(4,168,0), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULCHW }, +{ "mulchw.", XRC(4,168,1), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULCHW }, +{ "mulchwu", XRC(4,136,0), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULCHWU }, +{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULCHWU }, +{ "mulhhw", XRC(4,40,0), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULHHW }, +{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULHHW }, +{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULHHWU }, +{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULHHWU }, +{ "mullhw", XRC(4,424,0), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULLHW }, +{ "mullhw.", XRC(4,424,1), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULLHW }, +{ "mullhwu", XRC(4,392,0), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULLHWU }, +{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULLHWU }, +{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACCHW }, +{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACCHW }, +{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACCHWO }, +{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACCHWO }, +{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACCHWS }, +{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACCHWS }, +{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACCHWSO }, +{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACCHWSO }, +{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACHHW }, +{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACHHW }, +{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACHHWO }, +{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACHHWO }, +{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACHHWS }, +{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACHHWS }, +{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACHHWSO }, +{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACHHWSO }, +{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACLHW }, +{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACLHW }, +{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACLHWO }, +{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACLHWO }, +{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACLHWS }, +{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACLHWS }, +{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACLHWSO }, +{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_NMACLHWSO }, +{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD }, PPC_INST_MFVSCR }, +{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB }, PPC_INST_MTVSCR }, + +/* Double-precision opcodes. */ +/* Some of these conflict with AltiVec, so move them before, since + PPCVEC includes the PPC_OPCODE_PPC set. */ +{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFSCFD }, +{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA }, PPC_INST_EFDABS }, +{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA }, PPC_INST_EFDNABS }, +{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA }, PPC_INST_EFDNEG }, +{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB }, PPC_INST_EFDADD }, +{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB }, PPC_INST_EFDSUB }, +{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB }, PPC_INST_EFDMUL }, +{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB }, PPC_INST_EFDDIV }, +{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB }, PPC_INST_EFDCMPGT }, +{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB }, PPC_INST_EFDCMPLT }, +{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB }, PPC_INST_EFDCMPEQ }, +{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB }, PPC_INST_EFDTSTGT }, +{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB }, PPC_INST_EFDTSTLT }, +{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB }, PPC_INST_EFDTSTEQ }, +{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCFSI }, +{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCFSID }, +{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCFUI }, +{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCFUID }, +{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCFSF }, +{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCFUF }, +{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCTSI }, +{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCTSIDZ }, +{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCTSIZ }, +{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCTUI }, +{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCTUIDZ }, +{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCTUIZ }, +{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCTSF }, +{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCTUF }, +{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFDCFS }, +/* End of double-precision opcodes. */ + +{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VADDCUW }, +{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VADDFP }, +{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VADDSBS }, +{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VADDSHS }, +{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VADDSWS }, +{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VADDUBM }, +{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VADDUBS }, +{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VADDUHM }, +{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VADDUHS }, +{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VADDUWM }, +{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VADDUWS }, +{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VAND }, +{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VANDC }, +{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VAVGSB }, +{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VAVGSH }, +{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VAVGSW }, +{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VAVGUB }, +{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VAVGUH }, +{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VAVGUW }, +{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM }, PPC_INST_VCFSX }, +{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM }, PPC_INST_VCFUX }, +{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPBFP }, +{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPBFP }, +{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPEQFP }, +{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPEQFP }, +{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPEQUB }, +{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPEQUB }, +{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPEQUH }, +{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPEQUH }, +{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPEQUW }, +{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPEQUW }, +{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGEFP }, +{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGEFP }, +{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTFP }, +{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTFP }, +{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTSB }, +{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTSB }, +{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTSH }, +{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTSH }, +{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTSW }, +{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTSW }, +{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTUB }, +{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTUB }, +{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTUH }, +{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTUH }, +{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTUW }, +{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VCMPGTUW }, +{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM }, PPC_INST_VCTSXS }, +{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM }, PPC_INST_VCTUXS }, +{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VEXPTEFP }, +{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VLOGEFP }, +{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB }, PPC_INST_VMADDFP }, +{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMAXFP }, +{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMAXSB }, +{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMAXSH }, +{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMAXSW }, +{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMAXUB }, +{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMAXUH }, +{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMAXUW }, +{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC }, PPC_INST_VMHADDSHS }, +{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC }, PPC_INST_VMHRADDSHS }, +{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMINFP }, +{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMINSB }, +{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMINSH }, +{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMINSW }, +{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMINUB }, +{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMINUH }, +{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMINUW }, +{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC }, PPC_INST_VMLADDUHM }, +{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMRGHB }, +{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMRGHH }, +{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMRGHW }, +{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMRGLB }, +{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMRGLH }, +{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMRGLW }, +{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC }, PPC_INST_VMSUMMBM }, +{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC }, PPC_INST_VMSUMSHM }, +{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC }, PPC_INST_VMSUMSHS }, +{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC }, PPC_INST_VMSUMUBM }, +{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC }, PPC_INST_VMSUMUHM }, +{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC }, PPC_INST_VMSUMUHS }, +{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMULESB }, +{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMULESH }, +{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMULEUB }, +{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMULEUH }, +{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMULOSB }, +{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMULOSH }, +{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMULOUB }, +{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VMULOUH }, +{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB }, PPC_INST_VNMSUBFP }, +{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VNOR }, +{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VOR }, +{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC }, PPC_INST_VPERM }, +{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VPKPX }, +{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VPKSHSS }, +{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VPKSHUS }, +{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VPKSWSS }, +{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VPKSWUS }, +{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VPKUHUM }, +{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VPKUHUS }, +{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VPKUWUM }, +{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VPKUWUS }, +{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VREFP }, +{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VRFIM }, +{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VRFIN }, +{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VRFIP }, +{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VRFIZ }, +{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VRLB }, +{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VRLH }, +{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VRLW }, +{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VRSQRTEFP }, +{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC }, PPC_INST_VSEL }, +{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSL }, +{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSLB }, +{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB }, PPC_INST_VSLDOI }, +{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSLH }, +{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSLO }, +{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSLW }, +{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM }, PPC_INST_VSPLTB }, +{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM }, PPC_INST_VSPLTH }, +{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM }, PPC_INST_VSPLTISB }, +{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM }, PPC_INST_VSPLTISH }, +{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM }, PPC_INST_VSPLTISW }, +{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM }, PPC_INST_VSPLTW }, +{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSR }, +{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSRAB }, +{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSRAH }, +{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSRAW }, +{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSRB }, +{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSRH }, +{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSRO }, +{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSRW }, +{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUBCUW }, +{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUBFP }, +{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUBSBS }, +{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUBSHS }, +{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUBSWS }, +{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUBUBM }, +{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUBUBS }, +{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUBUHM }, +{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUBUHS }, +{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUBUWM }, +{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUBUWS }, +{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUMSWS }, +{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUM2SWS }, +{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUM4SBS }, +{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUM4SHS }, +{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VSUM4UBS }, +{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VUPKHPX }, +{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VUPKHSB }, +{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VUPKHSH }, +{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VUPKLPX }, +{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VUPKLSB }, +{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB }, PPC_INST_VUPKLSH }, +{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB }, PPC_INST_VXOR }, + +{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVADDW }, +{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM }, PPC_INST_EVADDIW }, +{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVSUBFW }, +{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA }, PPC_INST_EVSUBW }, +{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB }, PPC_INST_EVSUBIFW }, +{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM }, PPC_INST_EVSUBIW }, +{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVABS }, +{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVNEG }, +{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVEXTSB }, +{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVEXTSH }, +{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVRNDW }, +{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVCNTLZW }, +{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVCNTLSW }, + +{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_BRINC }, + +{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVAND }, +{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVANDC }, +{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA }, PPC_INST_EVMR }, +{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVOR }, +{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVORC }, +{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVXOR }, +{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVEQV }, +{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVNAND }, +{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA }, PPC_INST_EVNOT }, +{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVNOR }, + +{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVRLW }, +{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM }, PPC_INST_EVRLWI }, +{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVSLW }, +{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM }, PPC_INST_EVSLWI }, +{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVSRWS }, +{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVSRWU }, +{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM }, PPC_INST_EVSRWIS }, +{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM }, PPC_INST_EVSRWIU }, +{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM }, PPC_INST_EVSPLATI }, +{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM }, PPC_INST_EVSPLATFI }, +{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMERGEHI }, +{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMERGELO }, +{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMERGEHILO }, +{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMERGELOHI }, + +{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB }, PPC_INST_EVCMPGTS }, +{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB }, PPC_INST_EVCMPGTU }, +{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB }, PPC_INST_EVCMPLTS }, +{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB }, PPC_INST_EVCMPLTU }, +{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB }, PPC_INST_EVCMPEQ }, +{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS }, PPC_INST_EVSEL }, + +{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA }, PPC_INST_EVLDD }, +{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVLDDX }, +{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA }, PPC_INST_EVLDW }, +{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVLDWX }, +{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA }, PPC_INST_EVLDH }, +{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVLDHX }, +{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA }, PPC_INST_EVLWHE }, +{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVLWHEX }, +{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA }, PPC_INST_EVLWHOU }, +{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVLWHOUX }, +{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA }, PPC_INST_EVLWHOS }, +{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVLWHOSX }, +{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA }, PPC_INST_EVLWWSPLAT }, +{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVLWWSPLATX }, +{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA }, PPC_INST_EVLWHSPLAT }, +{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVLWHSPLATX }, +{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA }, PPC_INST_EVLHHESPLAT }, +{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVLHHESPLATX }, +{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA }, PPC_INST_EVLHHOUSPLAT }, +{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVLHHOUSPLATX }, +{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA }, PPC_INST_EVLHHOSSPLAT }, +{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVLHHOSSPLATX }, + +{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA }, PPC_INST_EVSTDD }, +{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVSTDDX }, +{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA }, PPC_INST_EVSTDW }, +{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVSTDWX }, +{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA }, PPC_INST_EVSTDH }, +{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVSTDHX }, +{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA }, PPC_INST_EVSTWWE }, +{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVSTWWEX }, +{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA }, PPC_INST_EVSTWWO }, +{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVSTWWOX }, +{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA }, PPC_INST_EVSTWHE }, +{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVSTWHEX }, +{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA }, PPC_INST_EVSTWHO }, +{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVSTWHOX }, + +{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVFSABS }, +{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVFSNABS }, +{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVFSNEG }, +{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVFSADD }, +{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVFSSUB }, +{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVFSMUL }, +{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVFSDIV }, +{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB }, PPC_INST_EVFSCMPGT }, +{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB }, PPC_INST_EVFSCMPLT }, +{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB }, PPC_INST_EVFSCMPEQ }, +{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB }, PPC_INST_EVFSTSTGT }, +{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB }, PPC_INST_EVFSTSTLT }, +{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB }, PPC_INST_EVFSTSTEQ }, +{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB }, PPC_INST_EVFSCFUI }, +{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB }, PPC_INST_EVFSCTUIZ }, +{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB }, PPC_INST_EVFSCFSI }, +{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB }, PPC_INST_EVFSCFUF }, +{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB }, PPC_INST_EVFSCFSF }, +{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB }, PPC_INST_EVFSCTUI }, +{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB }, PPC_INST_EVFSCTSI }, +{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB }, PPC_INST_EVFSCTSIZ }, +{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB }, PPC_INST_EVFSCTUF }, +{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB }, PPC_INST_EVFSCTSF }, + +{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA }, PPC_INST_EFSABS }, +{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA }, PPC_INST_EFSNABS }, +{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA }, PPC_INST_EFSNEG }, +{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB }, PPC_INST_EFSADD }, +{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB }, PPC_INST_EFSSUB }, +{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB }, PPC_INST_EFSMUL }, +{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB }, PPC_INST_EFSDIV }, +{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB }, PPC_INST_EFSCMPGT }, +{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB }, PPC_INST_EFSCMPLT }, +{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB }, PPC_INST_EFSCMPEQ }, +{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB }, PPC_INST_EFSTSTGT }, +{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB }, PPC_INST_EFSTSTLT }, +{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB }, PPC_INST_EFSTSTEQ }, +{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFSCFUI }, +{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFSCTUIZ }, +{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFSCFSI }, +{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFSCFUF }, +{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFSCFSF }, +{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFSCTUI }, +{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFSCTSI }, +{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFSCTSIZ }, +{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFSCTUF }, +{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB }, PPC_INST_EFSCTSF }, + +{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSSF }, +{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSSFA }, +{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSMF }, +{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSMFA }, +{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSMI }, +{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSMIA }, +{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOUMI }, +{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOUMIA }, +{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESSF }, +{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESSFA }, +{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESMF }, +{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESMFA }, +{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESMI }, +{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESMIA }, +{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHEUMI }, +{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHEUMIA }, + +{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSSFAAW }, +{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSSIAAW }, +{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSMFAAW }, +{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSMIAAW }, +{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOUSIAAW }, +{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOUMIAAW }, +{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESSFAAW }, +{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESSIAAW }, +{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESMFAAW }, +{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESMIAAW }, +{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHEUSIAAW }, +{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHEUMIAAW }, + +{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSSFANW }, +{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSSIANW }, +{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSMFANW }, +{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOSMIANW }, +{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOUSIANW }, +{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOUMIANW }, +{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESSFANW }, +{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESSIANW }, +{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESMFANW }, +{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHESMIANW }, +{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHEUSIANW }, +{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHEUMIANW }, + +{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOGSMFAA }, +{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOGSMIAA }, +{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOGUMIAA }, +{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHEGSMFAA }, +{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHEGSMIAA }, +{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHEGUMIAA }, + +{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOGSMFAN }, +{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOGSMIAN }, +{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHOGUMIAN }, +{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHEGSMFAN }, +{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHEGSMIAN }, +{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMHEGUMIAN }, + +{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWHSSF }, +{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWHSSFA }, +{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWHSMF }, +{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWHSMFA }, +{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWHSMI }, +{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWHSMIA }, +{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWHUMI }, +{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWHUMIA }, + +{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWLUMI }, +{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWLUMIA }, + +{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWLSSIAAW }, +{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWLSMIAAW }, +{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWLUSIAAW }, +{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWLUMIAAW }, + +{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWLSSIANW }, +{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWLSMIANW }, +{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWLUSIANW }, +{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWLUMIANW }, + +{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWSSF }, +{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWSSFA }, +{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWSMF }, +{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWSMFA }, +{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWSMI }, +{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWSMIA }, +{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWUMI }, +{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWUMIA }, + +{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWSSFAA }, +{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWSMFAA }, +{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWSMIAA }, +{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWUMIAA }, + +{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWSSFAN }, +{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWSMFAN }, +{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWSMIAN }, +{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVMWUMIAN }, + +{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVADDSSIAAW }, +{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVADDSMIAAW }, +{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVADDUSIAAW }, +{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVADDUMIAAW }, + +{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVSUBFSSIAAW }, +{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVSUBFSMIAAW }, +{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVSUBFUSIAAW }, +{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVSUBFUMIAAW }, + +{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA }, PPC_INST_EVMRA }, + +{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVDIVWS }, +{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVDIVWU }, + +{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI }, PPC_INST_MULLI }, +{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI }, PPC_INST_MULI }, + +{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI }, PPC_INST_SUBFIC }, +{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI }, PPC_INST_SFI }, + +{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI }, PPC_INST_DOZI }, + +{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD }, PPC_INST_BCE }, +{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD }, PPC_INST_BCEL }, +{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA }, PPC_INST_BCEA }, +{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA }, PPC_INST_BCELA }, + +{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI }, PPC_INST_CMPLWI }, +{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI }, PPC_INST_CMPLDI }, +{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI }, PPC_INST_CMPLI }, +{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI }, PPC_INST_CMPLI }, + +{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI }, PPC_INST_CMPWI }, +{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI }, PPC_INST_CMPDI }, +{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI }, PPC_INST_CMPI }, +{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI }, PPC_INST_CMPI }, + +{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI }, PPC_INST_ADDIC }, +{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI }, PPC_INST_AI }, +{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI }, PPC_INST_SUBIC }, + +{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI }, PPC_INST_ADDIC }, +{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI }, PPC_INST_AI }, +{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI }, PPC_INST_SUBIC }, + +{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI }, PPC_INST_LI }, +{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI }, PPC_INST_LIL }, +{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI }, PPC_INST_ADDI }, +{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 }, PPC_INST_CAL }, +{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI }, PPC_INST_SUBI }, +{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 }, PPC_INST_LA }, + +{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT }, PPC_INST_LIS }, +{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT }, PPC_INST_LIU }, +{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT }, PPC_INST_ADDIS }, +{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT }, PPC_INST_CAU }, +{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI }, PPC_INST_SUBIS }, + +{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM }, PPC_INST_BDNZ }, +{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP }, PPC_INST_BDNZ }, +{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD }, PPC_INST_BDNZ }, +{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD }, PPC_INST_BDN }, +{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM }, PPC_INST_BDNZL }, +{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP }, PPC_INST_BDNZL }, +{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD }, PPC_INST_BDNZL }, +{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD }, PPC_INST_BDNL }, +{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA }, PPC_INST_BDNZA }, +{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA }, PPC_INST_BDNZA }, +{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA }, PPC_INST_BDNZA }, +{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA }, PPC_INST_BDNA }, +{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA }, PPC_INST_BDNZLA }, +{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA }, PPC_INST_BDNZLA }, +{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA }, PPC_INST_BDNZLA }, +{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA }, PPC_INST_BDNLA }, +{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM }, PPC_INST_BDZ }, +{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP }, PPC_INST_BDZ }, +{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD }, PPC_INST_BDZ }, +{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM }, PPC_INST_BDZL }, +{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP }, PPC_INST_BDZL }, +{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD }, PPC_INST_BDZL }, +{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA }, PPC_INST_BDZA }, +{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA }, PPC_INST_BDZA }, +{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA }, PPC_INST_BDZA }, +{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA }, PPC_INST_BDZLA }, +{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA }, PPC_INST_BDZLA }, +{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA }, PPC_INST_BDZLA }, +{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BLT }, +{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BLT }, +{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BLT }, +{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BLTL }, +{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BLTL }, +{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BLTL }, +{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BLTA }, +{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BLTA }, +{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BLTA }, +{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BLTLA }, +{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BLTLA }, +{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BLTLA }, +{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BGT }, +{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BGT }, +{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BGT }, +{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BGTL }, +{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BGTL }, +{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BGTL }, +{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BGTA }, +{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BGTA }, +{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BGTA }, +{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BGTLA }, +{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BGTLA }, +{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BGTLA }, +{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BEQ }, +{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BEQ }, +{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BEQ }, +{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BEQL }, +{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BEQL }, +{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BEQL }, +{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BEQA }, +{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BEQA }, +{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BEQA }, +{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BEQLA }, +{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BEQLA }, +{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BEQLA }, +{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BSO }, +{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BSO }, +{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BSO }, +{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BSOL }, +{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BSOL }, +{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BSOL }, +{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BSOA }, +{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BSOA }, +{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BSOA }, +{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BSOLA }, +{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BSOLA }, +{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BSOLA }, +{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BUN }, +{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BUN }, +{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD }, PPC_INST_BUN }, +{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BUNL }, +{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BUNL }, +{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD }, PPC_INST_BUNL }, +{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BUNA }, +{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BUNA }, +{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA }, PPC_INST_BUNA }, +{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BUNLA }, +{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BUNLA }, +{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA }, PPC_INST_BUNLA }, +{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BGE }, +{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BGE }, +{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BGE }, +{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BGEL }, +{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BGEL }, +{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BGEL }, +{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BGEA }, +{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BGEA }, +{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BGEA }, +{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BGELA }, +{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BGELA }, +{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BGELA }, +{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BNL }, +{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BNL }, +{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BNL }, +{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BNLL }, +{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BNLL }, +{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BNLL }, +{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BNLA }, +{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BNLA }, +{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BNLA }, +{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BNLLA }, +{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BNLLA }, +{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BNLLA }, +{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BLE }, +{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BLE }, +{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BLE }, +{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BLEL }, +{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BLEL }, +{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BLEL }, +{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BLEA }, +{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BLEA }, +{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BLEA }, +{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BLELA }, +{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BLELA }, +{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BLELA }, +{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BNG }, +{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BNG }, +{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BNG }, +{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BNGL }, +{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BNGL }, +{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BNGL }, +{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BNGA }, +{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BNGA }, +{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BNGA }, +{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BNGLA }, +{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BNGLA }, +{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BNGLA }, +{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BNE }, +{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BNE }, +{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BNE }, +{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BNEL }, +{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BNEL }, +{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BNEL }, +{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BNEA }, +{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BNEA }, +{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BNEA }, +{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BNELA }, +{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BNELA }, +{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BNELA }, +{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BNS }, +{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BNS }, +{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BNS }, +{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BNSL }, +{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BNSL }, +{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD }, PPC_INST_BNSL }, +{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BNSA }, +{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BNSA }, +{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BNSA }, +{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BNSLA }, +{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BNSLA }, +{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA }, PPC_INST_BNSLA }, +{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BNU }, +{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BNU }, +{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD }, PPC_INST_BNU }, +{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM }, PPC_INST_BNUL }, +{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP }, PPC_INST_BNUL }, +{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD }, PPC_INST_BNUL }, +{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BNUA }, +{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BNUA }, +{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA }, PPC_INST_BNUA }, +{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA }, PPC_INST_BNULA }, +{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA }, PPC_INST_BNULA }, +{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA }, PPC_INST_BNULA }, +{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM }, PPC_INST_BDNZT }, +{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP }, PPC_INST_BDNZT }, +{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD }, PPC_INST_BDNZT }, +{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM }, PPC_INST_BDNZTL }, +{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP }, PPC_INST_BDNZTL }, +{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD }, PPC_INST_BDNZTL }, +{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA }, PPC_INST_BDNZTA }, +{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA }, PPC_INST_BDNZTA }, +{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA }, PPC_INST_BDNZTA }, +{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA }, PPC_INST_BDNZTLA }, +{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA }, PPC_INST_BDNZTLA }, +{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA }, PPC_INST_BDNZTLA }, +{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM }, PPC_INST_BDNZF }, +{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP }, PPC_INST_BDNZF }, +{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD }, PPC_INST_BDNZF }, +{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM }, PPC_INST_BDNZFL }, +{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP }, PPC_INST_BDNZFL }, +{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD }, PPC_INST_BDNZFL }, +{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA }, PPC_INST_BDNZFA }, +{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA }, PPC_INST_BDNZFA }, +{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA }, PPC_INST_BDNZFA }, +{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA }, PPC_INST_BDNZFLA }, +{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA }, PPC_INST_BDNZFLA }, +{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA }, PPC_INST_BDNZFLA }, +{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM }, PPC_INST_BT }, +{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP }, PPC_INST_BT }, +{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD }, PPC_INST_BT }, +{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD }, PPC_INST_BBT }, +{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM }, PPC_INST_BTL }, +{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP }, PPC_INST_BTL }, +{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD }, PPC_INST_BTL }, +{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD }, PPC_INST_BBTL }, +{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA }, PPC_INST_BTA }, +{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA }, PPC_INST_BTA }, +{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA }, PPC_INST_BTA }, +{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA }, PPC_INST_BBTA }, +{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA }, PPC_INST_BTLA }, +{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA }, PPC_INST_BTLA }, +{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA }, PPC_INST_BTLA }, +{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA }, PPC_INST_BBTLA }, +{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM }, PPC_INST_BF }, +{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP }, PPC_INST_BF }, +{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD }, PPC_INST_BF }, +{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD }, PPC_INST_BBF }, +{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM }, PPC_INST_BFL }, +{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP }, PPC_INST_BFL }, +{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD }, PPC_INST_BFL }, +{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD }, PPC_INST_BBFL }, +{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA }, PPC_INST_BFA }, +{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA }, PPC_INST_BFA }, +{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA }, PPC_INST_BFA }, +{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA }, PPC_INST_BBFA }, +{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA }, PPC_INST_BFLA }, +{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA }, PPC_INST_BFLA }, +{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA }, PPC_INST_BFLA }, +{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA }, PPC_INST_BBFLA }, +{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM }, PPC_INST_BDZT }, +{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP }, PPC_INST_BDZT }, +{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD }, PPC_INST_BDZT }, +{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM }, PPC_INST_BDZTL }, +{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP }, PPC_INST_BDZTL }, +{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD }, PPC_INST_BDZTL }, +{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA }, PPC_INST_BDZTA }, +{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA }, PPC_INST_BDZTA }, +{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA }, PPC_INST_BDZTA }, +{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA }, PPC_INST_BDZTLA }, +{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA }, PPC_INST_BDZTLA }, +{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA }, PPC_INST_BDZTLA }, +{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM }, PPC_INST_BDZF }, +{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP }, PPC_INST_BDZF }, +{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD }, PPC_INST_BDZF }, +{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM }, PPC_INST_BDZFL }, +{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP }, PPC_INST_BDZFL }, +{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD }, PPC_INST_BDZFL }, +{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA }, PPC_INST_BDZFA }, +{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA }, PPC_INST_BDZFA }, +{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA }, PPC_INST_BDZFA }, +{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA }, PPC_INST_BDZFLA }, +{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA }, PPC_INST_BDZFLA }, +{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA }, PPC_INST_BDZFLA }, +{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM }, PPC_INST_BC }, +{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP }, PPC_INST_BC }, +{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD }, PPC_INST_BC }, +{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM }, PPC_INST_BCL }, +{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP }, PPC_INST_BCL }, +{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD }, PPC_INST_BCL }, +{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA }, PPC_INST_BCA }, +{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA }, PPC_INST_BCA }, +{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA }, PPC_INST_BCA }, +{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA }, PPC_INST_BCLA }, +{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA }, PPC_INST_BCLA }, +{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA }, PPC_INST_BCLA }, + +{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV }, PPC_INST_SC }, +{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 }, PPC_INST_SVC }, +{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 }, PPC_INST_SVCL }, +{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV }, PPC_INST_SVCA }, +{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV }, PPC_INST_SVCLA }, + +{ "b", B(18,0,0), B_MASK, COM, { LI }, PPC_INST_B }, +{ "bl", B(18,0,1), B_MASK, COM, { LI }, PPC_INST_BL }, +{ "ba", B(18,1,0), B_MASK, COM, { LIA }, PPC_INST_BA }, +{ "bla", B(18,1,1), B_MASK, COM, { LIA }, PPC_INST_BLA }, + +{ "mcrf", XL(19,0), XLBB_MASK | (3 << 21) | (3 << 16), COM, { BF, BFA }, PPC_INST_MCRF }, + +{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 }, PPC_INST_BLR }, +{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 }, PPC_INST_BR }, +{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 }, PPC_INST_BLRL }, +{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 }, PPC_INST_BRL }, +{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 }, PPC_INST_BDNZLR }, +{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 }, PPC_INST_BDNZLR }, +{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 }, PPC_INST_BDNZLR }, +{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 }, PPC_INST_BDNZLR }, +{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 }, PPC_INST_BDNZLR }, +{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 }, PPC_INST_BDNZLRL }, +{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 }, PPC_INST_BDNZLRL }, +{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 }, PPC_INST_BDNZLRL }, +{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 }, PPC_INST_BDNZLRL }, +{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 }, PPC_INST_BDNZLRL }, +{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 }, PPC_INST_BDZLR }, +{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 }, PPC_INST_BDZLR }, +{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 }, PPC_INST_BDZLR }, +{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 }, PPC_INST_BDZLR }, +{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 }, PPC_INST_BDZLR }, +{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 }, PPC_INST_BDZLRL }, +{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 }, PPC_INST_BDZLRL }, +{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 }, PPC_INST_BDZLRL }, +{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 }, PPC_INST_BDZLRL }, +{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 }, PPC_INST_BDZLRL }, +{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BLTLR }, +{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLTLR }, +{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLTLR }, +{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLTLR }, +{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLTLR }, +{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BLTR }, +{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BLTLRL }, +{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLTLRL }, +{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLTLRL }, +{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLTLRL }, +{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLTLRL }, +{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BLTRL }, +{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BGTLR }, +{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGTLR }, +{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGTLR }, +{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGTLR }, +{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGTLR }, +{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BGTR }, +{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BGTLRL }, +{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGTLRL }, +{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGTLRL }, +{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGTLRL }, +{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGTLRL }, +{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BGTRL }, +{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BEQLR }, +{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BEQLR }, +{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BEQLR }, +{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BEQLR }, +{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BEQLR }, +{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BEQR }, +{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BEQLRL }, +{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BEQLRL }, +{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BEQLRL }, +{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BEQLRL }, +{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BEQLRL }, +{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BEQRL }, +{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BSOLR }, +{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BSOLR }, +{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BSOLR }, +{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BSOLR }, +{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BSOLR }, +{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BSOR }, +{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BSOLRL }, +{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BSOLRL }, +{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BSOLRL }, +{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BSOLRL }, +{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BSOLRL }, +{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BSORL }, +{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BUNLR }, +{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BUNLR }, +{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BUNLR }, +{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BUNLR }, +{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BUNLR }, +{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BUNLRL }, +{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BUNLRL }, +{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BUNLRL }, +{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BUNLRL }, +{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BUNLRL }, +{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BGELR }, +{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGELR }, +{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGELR }, +{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGELR }, +{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGELR }, +{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BGER }, +{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BGELRL }, +{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGELRL }, +{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGELRL }, +{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGELRL }, +{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGELRL }, +{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BGERL }, +{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNLLR }, +{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNLLR }, +{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNLLR }, +{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNLLR }, +{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNLLR }, +{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BNLR }, +{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNLLRL }, +{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNLLRL }, +{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNLLRL }, +{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNLLRL }, +{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNLLRL }, +{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BNLRL }, +{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BLELR }, +{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLELR }, +{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLELR }, +{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLELR }, +{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLELR }, +{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BLER }, +{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BLELRL }, +{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLELRL }, +{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLELRL }, +{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLELRL }, +{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLELRL }, +{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BLERL }, +{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNGLR }, +{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNGLR }, +{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNGLR }, +{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNGLR }, +{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNGLR }, +{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BNGR }, +{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNGLRL }, +{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNGLRL }, +{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNGLRL }, +{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNGLRL }, +{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNGLRL }, +{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BNGRL }, +{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNELR }, +{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNELR }, +{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNELR }, +{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNELR }, +{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNELR }, +{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BNER }, +{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNELRL }, +{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNELRL }, +{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNELRL }, +{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNELRL }, +{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNELRL }, +{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BNERL }, +{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNSLR }, +{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNSLR }, +{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNSLR }, +{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNSLR }, +{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNSLR }, +{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BNSR }, +{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNSLRL }, +{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNSLRL }, +{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNSLRL }, +{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNSLRL }, +{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNSLRL }, +{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR }, PPC_INST_BNSRL }, +{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNULR }, +{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNULR }, +{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNULR }, +{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNULR }, +{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNULR }, +{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNULRL }, +{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNULRL }, +{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNULRL }, +{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNULRL }, +{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNULRL }, +{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BTLR }, +{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BTLR }, +{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BTLR }, +{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BTLR }, +{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BTLR }, +{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI }, PPC_INST_BBTR }, +{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BTLRL }, +{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BTLRL }, +{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BTLRL }, +{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BTLRL }, +{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BTLRL }, +{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI }, PPC_INST_BBTRL }, +{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BFLR }, +{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BFLR }, +{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BFLR }, +{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BFLR }, +{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BFLR }, +{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI }, PPC_INST_BBFR }, +{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BFLRL }, +{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BFLRL }, +{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BFLRL }, +{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BFLRL }, +{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BFLRL }, +{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI }, PPC_INST_BBFRL }, +{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BDNZTLR }, +{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDNZTLR }, +{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDNZTLR }, +{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BDNZTLRL }, +{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDNZTLRL }, +{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDNZTLRL }, +{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BDNZFLR }, +{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDNZFLR }, +{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDNZFLR }, +{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BDNZFLRL }, +{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDNZFLRL }, +{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDNZFLRL }, +{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BDZTLR }, +{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDZTLR }, +{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDZTLR }, +{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BDZTLRL }, +{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDZTLRL }, +{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDZTLRL }, +{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BDZFLR }, +{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDZFLR }, +{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDZFLR }, +{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BDZFLRL }, +{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDZFLRL }, +{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BDZFLRL }, +{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI }, PPC_INST_BCLR }, +{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI }, PPC_INST_BCLRL }, +{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI }, PPC_INST_BCLR }, +{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI }, PPC_INST_BCLRL }, +{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH }, PPC_INST_BCLR }, +{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH }, PPC_INST_BCLRL }, +{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI }, PPC_INST_BCR }, +{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI }, PPC_INST_BCRL }, +{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI }, PPC_INST_BCLRE }, +{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI }, PPC_INST_BCLREL }, + +{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 }, PPC_INST_RFID }, + +{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA }, PPC_INST_CRNOT }, +{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB }, PPC_INST_CRNOR }, +{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 }, PPC_INST_RFMCI }, + +{ "rfi", XL(19,50), 0xffffffff, COM, { 0 }, PPC_INST_RFI }, +{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 }, PPC_INST_RFCI }, + +{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 }, PPC_INST_RFSVC }, + +{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB }, PPC_INST_CRANDC }, + +{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 }, PPC_INST_ISYNC }, +{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 }, PPC_INST_ICS }, + +{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA }, PPC_INST_CRCLR }, +{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB }, PPC_INST_CRXOR }, + +{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB }, PPC_INST_CRNAND }, + +{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB }, PPC_INST_CRAND }, + +{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 }, PPC_INST_HRFID }, + +{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA }, PPC_INST_CRSET }, +{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB }, PPC_INST_CREQV }, + +{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 }, PPC_INST_DOZE }, + +{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB }, PPC_INST_CRORC }, + +{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 }, PPC_INST_NAP }, + +{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA }, PPC_INST_CRMOVE }, +{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB }, PPC_INST_CROR }, + +{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 }, PPC_INST_SLEEP }, +{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 }, PPC_INST_RVWINKLE }, + +{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 }, PPC_INST_BCTR }, +{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 }, PPC_INST_BCTRL }, +{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BLTCTR }, +{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLTCTR }, +{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLTCTR }, +{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLTCTR }, +{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLTCTR }, +{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BLTCTRL }, +{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLTCTRL }, +{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLTCTRL }, +{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLTCTRL }, +{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLTCTRL }, +{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BGTCTR }, +{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGTCTR }, +{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGTCTR }, +{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGTCTR }, +{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGTCTR }, +{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BGTCTRL }, +{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGTCTRL }, +{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGTCTRL }, +{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGTCTRL }, +{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGTCTRL }, +{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BEQCTR }, +{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BEQCTR }, +{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BEQCTR }, +{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BEQCTR }, +{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BEQCTR }, +{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BEQCTRL }, +{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BEQCTRL }, +{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BEQCTRL }, +{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BEQCTRL }, +{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BEQCTRL }, +{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BSOCTR }, +{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BSOCTR }, +{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BSOCTR }, +{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BSOCTR }, +{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BSOCTR }, +{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BSOCTRL }, +{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BSOCTRL }, +{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BSOCTRL }, +{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BSOCTRL }, +{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BSOCTRL }, +{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BUNCTR }, +{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BUNCTR }, +{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BUNCTR }, +{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BUNCTR }, +{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BUNCTR }, +{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BUNCTRL }, +{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BUNCTRL }, +{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BUNCTRL }, +{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BUNCTRL }, +{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BUNCTRL }, +{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BGECTR }, +{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGECTR }, +{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGECTR }, +{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGECTR }, +{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGECTR }, +{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BGECTRL }, +{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGECTRL }, +{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGECTRL }, +{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BGECTRL }, +{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BGECTRL }, +{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNLCTR }, +{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNLCTR }, +{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNLCTR }, +{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNLCTR }, +{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNLCTR }, +{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNLCTRL }, +{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNLCTRL }, +{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNLCTRL }, +{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNLCTRL }, +{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNLCTRL }, +{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BLECTR }, +{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLECTR }, +{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLECTR }, +{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLECTR }, +{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLECTR }, +{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BLECTRL }, +{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLECTRL }, +{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLECTRL }, +{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BLECTRL }, +{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BLECTRL }, +{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNGCTR }, +{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNGCTR }, +{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNGCTR }, +{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNGCTR }, +{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNGCTR }, +{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNGCTRL }, +{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNGCTRL }, +{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNGCTRL }, +{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNGCTRL }, +{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNGCTRL }, +{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNECTR }, +{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNECTR }, +{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNECTR }, +{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNECTR }, +{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNECTR }, +{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNECTRL }, +{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNECTRL }, +{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNECTRL }, +{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNECTRL }, +{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNECTRL }, +{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNSCTR }, +{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNSCTR }, +{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNSCTR }, +{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNSCTR }, +{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNSCTR }, +{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNSCTRL }, +{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNSCTRL }, +{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNSCTRL }, +{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNSCTRL }, +{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNSCTRL }, +{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNUCTR }, +{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNUCTR }, +{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNUCTR }, +{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNUCTR }, +{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNUCTR }, +{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR }, PPC_INST_BNUCTRL }, +{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNUCTRL }, +{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNUCTRL }, +{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR }, PPC_INST_BNUCTRL }, +{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR }, PPC_INST_BNUCTRL }, +{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BTCTR }, +{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BTCTR }, +{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BTCTR }, +{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BTCTR }, +{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BTCTR }, +{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BTCTRL }, +{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BTCTRL }, +{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BTCTRL }, +{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BTCTRL }, +{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BTCTRL }, +{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BFCTR }, +{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BFCTR }, +{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BFCTR }, +{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BFCTR }, +{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BFCTR }, +{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI }, PPC_INST_BFCTRL }, +{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BFCTRL }, +{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BFCTRL }, +{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI }, PPC_INST_BFCTRL }, +{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI }, PPC_INST_BFCTRL }, +{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI }, PPC_INST_BCCTR }, +{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI }, PPC_INST_BCCTR }, +{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI }, PPC_INST_BCCTRL }, +{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI }, PPC_INST_BCCTRL }, +{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH }, PPC_INST_BCCTR }, +{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH }, PPC_INST_BCCTRL }, +{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI }, PPC_INST_BCC }, +{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI }, PPC_INST_BCCL }, +{ "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI }, PPC_INST_BCCTRE }, +{ "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI }, PPC_INST_BCCTREL }, + +{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME }, PPC_INST_RLWIMI }, +{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME }, PPC_INST_RLIMI }, + +{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME }, PPC_INST_RLWIMI }, +{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME }, PPC_INST_RLIMI }, + +{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH }, PPC_INST_ROTLWI }, +{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB }, PPC_INST_CLRLWI }, +{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME }, PPC_INST_RLWINM }, +{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME }, PPC_INST_RLINM }, +{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH }, PPC_INST_ROTLWI }, +{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB }, PPC_INST_CLRLWI }, +{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME }, PPC_INST_RLWINM }, +{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME }, PPC_INST_RLINM }, + +{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME }, PPC_INST_RLMI }, +{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME }, PPC_INST_RLMI }, + +{ "be", B(22,0,0), B_MASK, BOOKE64, { LI }, PPC_INST_BE }, +{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI }, PPC_INST_BEL }, +{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA }, PPC_INST_BEA }, +{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA }, PPC_INST_BELA }, + +{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB }, PPC_INST_ROTLW }, +{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME }, PPC_INST_RLWNM }, +{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME }, PPC_INST_RLNM }, +{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB }, PPC_INST_ROTLW }, +{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME }, PPC_INST_RLWNM }, +{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME }, PPC_INST_RLNM }, + +{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 }, PPC_INST_NOP }, +{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI }, PPC_INST_ORI }, +{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI }, PPC_INST_ORIL }, + +{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI }, PPC_INST_ORIS }, +{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI }, PPC_INST_ORIU }, + +{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI }, PPC_INST_XORI }, +{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI }, PPC_INST_XORIL }, + +{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI }, PPC_INST_XORIS }, +{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI }, PPC_INST_XORIU }, + +{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI }, PPC_INST_ANDI }, +{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI }, PPC_INST_ANDIL }, + +{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI }, PPC_INST_ANDIS }, +{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI }, PPC_INST_ANDIU }, + +{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 }, PPC_INST_ROTLDI }, +{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 }, PPC_INST_CLRLDI }, +{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 }, PPC_INST_RLDICL }, +{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 }, PPC_INST_ROTLDI }, +{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 }, PPC_INST_CLRLDI }, +{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 }, PPC_INST_RLDICL }, + +{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 }, PPC_INST_RLDICR }, +{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 }, PPC_INST_RLDICR }, + +{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 }, PPC_INST_RLDIC }, +{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 }, PPC_INST_RLDIC }, + +{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 }, PPC_INST_RLDIMI }, +{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 }, PPC_INST_RLDIMI }, + +{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB }, PPC_INST_ROTLD }, +{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 }, PPC_INST_RLDCL }, +{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB }, PPC_INST_ROTLD }, +{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 }, PPC_INST_RLDCL }, + +{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 }, PPC_INST_RLDCR }, +{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 }, PPC_INST_RLDCR }, + +{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB }, PPC_INST_CMPW }, +{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB }, PPC_INST_CMPD }, +{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB }, PPC_INST_CMP }, +{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB }, PPC_INST_CMP }, + +{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWLGT }, +{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TLGT }, +{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWLLT }, +{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TLLT }, +{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWEQ }, +{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TEQ }, +{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWLGE }, +{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TLGE }, +{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWLNL }, +{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TLNL }, +{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWLLE }, +{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TLLE }, +{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWLNG }, +{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TLNG }, +{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWGT }, +{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TGT }, +{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWGE }, +{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TGE }, +{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWNL }, +{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TNL }, +{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWLT }, +{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TLT }, +{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWLE }, +{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TLE }, +{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWNG }, +{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TNG }, +{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB }, PPC_INST_TWNE }, +{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB }, PPC_INST_TNE }, +{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 }, PPC_INST_TRAP }, +{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB }, PPC_INST_TW }, +{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB }, PPC_INST_T }, + +{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_SUBFC }, +{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_SF }, +{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA }, PPC_INST_SUBC }, +{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_SUBFC }, +{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_SF }, +{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA }, PPC_INST_SUBC }, +{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_SUBFCO }, +{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_SFO }, +{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA }, PPC_INST_SUBCO }, +{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_SUBFCO }, +{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_SFO }, +{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA }, PPC_INST_SUBCO }, + +{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_MULHDU }, +{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_MULHDU }, + +{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_ADDC }, +{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_A }, +{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_ADDC }, +{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_A }, +{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_ADDCO }, +{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_AO }, +{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_ADDCO }, +{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_AO }, + +{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_MULHWU }, +{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_MULHWU }, + +{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB }, PPC_INST_ISELLT }, +{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB }, PPC_INST_ISELGT }, +{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB }, PPC_INST_ISELEQ }, +{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB }, PPC_INST_ISEL }, + +{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM }, PPC_INST_MFOCRF }, +{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT }, PPC_INST_MFCR }, +{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 }, PPC_INST_MFCR }, + +{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH }, PPC_INST_LWARX }, + +{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB }, PPC_INST_LDX }, + +{ "icbt", X(31,22), X_MASK, BOOKE | PPCE300, { CT, RA, RB }, PPC_INST_ICBT }, +{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB }, PPC_INST_ICBT }, + +{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB }, PPC_INST_LWZX }, +{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_LX }, + +{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB }, PPC_INST_SLW }, +{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB }, PPC_INST_SL }, +{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB }, PPC_INST_SLW }, +{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB }, PPC_INST_SL }, + +{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS }, PPC_INST_CNTLZW }, +{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS }, PPC_INST_CNTLZ }, +{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS }, PPC_INST_CNTLZW }, +{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS }, PPC_INST_CNTLZ }, + +{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB }, PPC_INST_SLD }, +{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB }, PPC_INST_SLD }, + +{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB }, PPC_INST_AND }, +{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB }, PPC_INST_AND }, + +{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB }, PPC_INST_MASKG }, +{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB }, PPC_INST_MASKG }, + +{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB }, PPC_INST_ICBTE }, + +{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB }, PPC_INST_LWZXE }, + +{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB }, PPC_INST_CMPLW }, +{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB }, PPC_INST_CMPLD }, +{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB }, PPC_INST_CMPL }, +{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB }, PPC_INST_CMPL }, + +{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_SUBF }, +{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA }, PPC_INST_SUB }, +{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_SUBF }, +{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA }, PPC_INST_SUB }, +{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_SUBFO }, +{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA }, PPC_INST_SUBO }, +{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_SUBFO }, +{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA }, PPC_INST_SUBO }, -{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } }, +{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB }, PPC_INST_LDUX }, -{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, +{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB }, PPC_INST_DCBST }, -{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, -{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } }, +{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB }, PPC_INST_LWZUX }, +{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_LUX }, -{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } }, +{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB }, PPC_INST_DCBSTE }, -{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } }, +{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB }, PPC_INST_LWZUXE }, -{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } }, -{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } }, +{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS }, PPC_INST_CNTLZD }, +{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS }, PPC_INST_CNTLZD }, -{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, -{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, +{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB }, PPC_INST_ANDC }, +{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB }, PPC_INST_ANDC }, -{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } }, -{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } }, -{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } }, -{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } }, -{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } }, -{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } }, -{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } }, -{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } }, -{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } }, -{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } }, +{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDLGT }, +{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDLLT }, +{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDEQ }, +{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDLGE }, +{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDLNL }, +{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDLLE }, +{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDLNG }, +{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDGT }, +{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDGE }, +{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDNL }, +{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDLT }, +{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDLE }, +{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDNG }, +{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB }, PPC_INST_TDNE }, +{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB }, PPC_INST_TD }, -{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } }, +{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_MULHD }, +{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_MULHD }, -{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, +{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_MULHW }, +{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_MULHW }, -{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } }, -{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } }, +{ "dlmzb", XRC(31,78,0), X_MASK, PPC403 | PPC440, { RA, RS, RB }, PPC_INST_DLMZB }, +{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403 | PPC440, { RA, RS, RB }, PPC_INST_DLMZB }, -{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } }, +{ "mtsrd", X(31,82), XRB_MASK | (1 << 20), PPC64, { SR, RS }, PPC_INST_MTSRD }, -{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, +{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT }, PPC_INST_MFMSR }, -{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } }, +{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH }, PPC_INST_LDARX }, -{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } }, -{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } }, +{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB }, PPC_INST_DCBFL }, +{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L }, PPC_INST_DCBF }, -{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } }, +{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB }, PPC_INST_LBZX }, -{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } }, +{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB }, PPC_INST_DCBFE }, -{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } }, +{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB }, PPC_INST_LBZXE }, -{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, -{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, -{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } }, -{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } }, +{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA }, PPC_INST_NEG }, +{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA }, PPC_INST_NEG }, +{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA }, PPC_INST_NEGO }, +{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA }, PPC_INST_NEGO }, -{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } }, -{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } }, -{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } }, -{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } }, +{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB }, PPC_INST_MUL }, +{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB }, PPC_INST_MUL }, +{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB }, PPC_INST_MULO }, +{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB }, PPC_INST_MULO }, -{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } }, +{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB }, PPC_INST_MTSRDIN }, -{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } }, +{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB }, PPC_INST_CLF }, -{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } }, +{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB }, PPC_INST_LBZUX }, -{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } }, +{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS }, PPC_INST_POPCNTB }, -{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, -{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } }, -{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, -{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, +{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS }, PPC_INST_NOT }, +{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB }, PPC_INST_NOR }, +{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS }, PPC_INST_NOT }, +{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB }, PPC_INST_NOR }, -{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } }, +{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB }, PPC_INST_LWARXE }, -{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, +{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB }, PPC_INST_LBZUXE }, -{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } }, +{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS }, PPC_INST_WRTEE }, -{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }}, +{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }, PPC_INST_DCBTSTLS }, -{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_SUBFE }, +{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_SFE }, +{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_SUBFE }, +{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_SFE }, +{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_SUBFEO }, +{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_SFEO }, +{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_SUBFEO }, +{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_SFEO }, -{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_ADDE }, +{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_AE }, +{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_ADDE }, +{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_AE }, +{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_ADDEO }, +{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_AEO }, +{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_ADDEO }, +{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_AEO }, -{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }}, +{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }, PPC_INST_DCBTSTLSE }, -{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } }, -{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }}, -{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, +{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS }, PPC_INST_MTOCRF }, +{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }, PPC_INST_MTCR }, +{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS }, PPC_INST_MTCRF }, -{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, +{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS }, PPC_INST_MTMSR }, -{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } }, +{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB }, PPC_INST_STDX }, -{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } }, +{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB }, PPC_INST_STWCX }, -{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } }, -{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, +{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB }, PPC_INST_STWX }, +{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB }, PPC_INST_STX }, -{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } }, +{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB }, PPC_INST_STWCXE }, -{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } }, +{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB }, PPC_INST_STWXE }, -{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, -{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, +{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB }, PPC_INST_SLQ }, +{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB }, PPC_INST_SLQ }, -{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, -{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, +{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB }, PPC_INST_SLE }, +{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB }, PPC_INST_SLE }, -{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } }, +{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS }, PPC_INST_PRTYW }, -{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, +{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E }, PPC_INST_WRTEEI }, -{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, -{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }}, +{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }, PPC_INST_DCBTLS }, +{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }, PPC_INST_DCBTLSE }, -{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } }, +{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L }, PPC_INST_MTMSRD }, -{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, +{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB }, PPC_INST_STDUX }, -{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, -{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } }, +{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB }, PPC_INST_STWUX }, +{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB }, PPC_INST_STUX }, -{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, -{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, +{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH }, PPC_INST_SLIQ }, +{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH }, PPC_INST_SLIQ }, -{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } }, +{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS }, PPC_INST_PRTYD }, -{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, +{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB }, PPC_INST_STWUXE }, -{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } }, +{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_SUBFZE }, +{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_SFZE }, +{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_SUBFZE }, +{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_SFZE }, +{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_SUBFZEO }, +{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_SFZEO }, +{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_SUBFZEO }, +{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_SFZEO }, -{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } }, +{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_ADDZE }, +{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_AZE }, +{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_ADDZE }, +{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_AZE }, +{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_ADDZEO }, +{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_AZEO }, +{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_ADDZEO }, +{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_AZEO }, -{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, +{ "mtsr", X(31,210), XRB_MASK | (1 << 20), COM32, { SR, RS }, PPC_INST_MTSR }, -{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } }, +{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB }, PPC_INST_STDCX }, -{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } }, +{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB }, PPC_INST_STBX }, -{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, -{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, +{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB }, PPC_INST_SLLQ }, +{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB }, PPC_INST_SLLQ }, -{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, -{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } }, +{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB }, PPC_INST_SLEQ }, +{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB }, PPC_INST_SLEQ }, -{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } }, +{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB }, PPC_INST_STBXE }, -{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }}, +{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }, PPC_INST_ICBLC }, -{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } }, +{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_SUBFME }, +{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_SFME }, +{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_SUBFME }, +{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_SFME }, +{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_SUBFMEO }, +{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_SFMEO }, +{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_SUBFMEO }, +{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_SFMEO }, -{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } }, +{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_MULLD }, +{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_MULLD }, +{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_MULLDO }, +{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_MULLDO }, -{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } }, +{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_ADDME }, +{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_AME }, +{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_ADDME }, +{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_AME }, +{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_ADDMEO }, +{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_AMEO }, +{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA }, PPC_INST_ADDMEO }, +{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA }, PPC_INST_AMEO }, -{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_MULLW }, +{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_MULS }, +{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_MULLW }, +{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_MULS }, +{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_MULLWO }, +{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_MULSO }, +{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_MULLWO }, +{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_MULSO }, -{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }}, -{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, -{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, +{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }, PPC_INST_ICBLCE }, +{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB }, PPC_INST_MTSRIN }, +{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB }, PPC_INST_MTSRI }, -{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } }, +{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB }, PPC_INST_DCBTST }, -{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, - -{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } }, -{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } }, - -{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } }, - -{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } }, - -{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } }, - -{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } }, -{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } }, -{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } }, -{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } }, - -{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, - -{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } }, - -{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } }, - -{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, -{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, - -{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } }, - -{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } }, - -{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, -{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, - -{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } }, - -{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } }, - -{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } }, -{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } }, - -{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, - -{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } }, - -{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } }, -{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } }, - -{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } }, - -{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } }, -{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } }, -{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } }, -{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } }, -{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } }, -{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } }, -{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } }, -{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } }, -{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } }, -{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } }, -{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } }, -{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } }, -{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } }, -{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } }, -{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } }, -{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } }, -{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } }, -{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } }, -{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } }, -{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } }, -{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, -{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } }, - -{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } }, -{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } }, -{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } }, -{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } }, - -{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }}, - -{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } }, -{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } }, -{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, -{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } }, -{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, -{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, -{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } }, -{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } }, -{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, -{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } }, -{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } }, -{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, -{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, -{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, -{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, -{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } }, -{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } }, -{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, -{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } }, -{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } }, -{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } }, -{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, -{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } }, -{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, -{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } }, -{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } }, -{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } }, -{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } }, -{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } }, -{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } }, -{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } }, -{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } }, -{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } }, -{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } }, -{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, -{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } }, -{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } }, -{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } }, -{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, -{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } }, -{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, -{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } }, -{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } }, -{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } }, -{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, -{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, -{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, -{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, -{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } }, -{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } }, -{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } }, -{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } }, -{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, -{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, -{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } }, -{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, -{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } }, -{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, -{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } }, -{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } }, -{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } }, -{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } }, -{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } }, -{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } }, -{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, -{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } }, -{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, -{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } }, -{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } }, -{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } }, -{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } }, -{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } }, -{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, -{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } }, -{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, -{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } }, -{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } }, -{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } }, -{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } }, -{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } }, -{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, -{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } }, -{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, -{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } }, -{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } }, -{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } }, -{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } }, -{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } }, -{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } }, -{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } }, -{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } }, -{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } }, -{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } }, -{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, -{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, -{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, -{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, -{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, -{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, -{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, -{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, -{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, -{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, -{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } }, -{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } }, -{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } }, -{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } }, -{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } }, -{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, -{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } }, -{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } }, -{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } }, -{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } }, -{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } }, -{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } }, -{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } }, -{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } }, -{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } }, -{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } }, -{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } }, -{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } }, -{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } }, -{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } }, -{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } }, -{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } }, -{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } }, -{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } }, -{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } }, -{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } }, -{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } }, -{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, -{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } }, -{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } }, -{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } }, -{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } }, -{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } }, -{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } }, -{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } }, -{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } }, -{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } }, -{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } }, -{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } }, - -{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } }, - -{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, -{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, - -{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } }, - -{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } }, - -{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, -{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, - -{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } }, - -{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, -{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } }, -{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } }, -{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } }, - -{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } }, -{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } }, -{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } }, -{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } }, - -{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, - -{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } }, - -{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } }, - -{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } }, - -{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } }, - -{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }}, - -{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, -{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, - -{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, -{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, - -{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }}, - -{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } }, - -{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } }, - -{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } }, - -{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, - -{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } }, - -{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, - -{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, - -{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } }, - -{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, - -{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, -{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } }, - -{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } }, -{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } }, - -{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } }, - -{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } }, - -{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, - -{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } }, - -{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } }, - -{ "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }}, -{ "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }}, -{ "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }}, -{ "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }}, -{ "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }}, -{ "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }}, -{ "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }}, -{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, -{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, -{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, -{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } }, - -{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } }, -{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } }, -{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } }, -{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } }, -{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } }, -{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } }, -{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } }, -{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } }, -{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } }, -{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } }, -{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } }, -{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } }, -{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } }, -{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } }, -{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } }, -{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } }, -{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } }, -{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } }, -{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } }, -{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } }, -{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } }, -{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } }, -{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } }, -{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } }, -{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } }, -{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } }, -{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } }, - -{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } }, -{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } }, - -{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } }, - -{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } }, -{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } }, - -{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } }, -{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } }, -{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } }, -{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } }, -{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, -{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } }, -{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } }, -{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } }, -{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } }, -{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } }, -{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, -{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, -{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, -{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, -{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } }, -{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } }, -{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } }, -{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } }, -{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } }, -{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } }, -{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } }, -{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } }, -{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } }, -{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } }, -{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } }, -{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } }, -{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } }, -{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } }, -{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } }, -{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } }, -{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } }, -{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } }, -{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } }, -{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } }, -{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } }, -{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } }, -{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } }, -{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } }, -{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } }, -{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } }, -{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } }, -{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } }, -{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } }, -{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } }, -{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } }, -{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } }, -{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } }, -{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } }, -{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } }, -{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } }, -{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } }, -{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } }, -{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } }, -{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, -{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, -{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, -{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } }, -{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } }, -{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } }, -{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } }, -{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } }, -{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } }, -{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } }, -{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } }, -{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } }, -{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } }, -{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } }, -{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } }, -{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } }, -{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } }, -{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } }, -{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } }, -{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } }, -{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } }, -{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } }, -{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } }, -{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } }, -{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } }, -{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } }, -{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } }, -{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } }, -{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } }, -{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } }, -{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } }, -{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } }, -{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } }, -{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } }, -{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } }, -{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } }, -{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } }, -{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } }, -{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, -{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, -{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } }, -{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } }, -{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } }, -{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } }, -{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } }, -{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } }, -{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } }, -{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } }, -{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } }, -{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } }, -{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } }, -{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } }, -{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } }, -{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } }, -{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } }, -{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } }, -{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } }, -{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } }, -{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } }, -{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } }, -{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } }, -{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } }, -{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } }, -{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } }, -{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } }, -{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } }, -{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } }, -{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } }, -{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } }, -{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } }, -{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } }, -{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } }, -{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } }, -{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } }, -{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } }, -{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } }, -{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } }, -{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } }, -{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } }, -{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } }, -{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } }, - -{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, - -{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } }, -{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } }, - -{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } }, - -{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }}, - -{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }}, - -{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }}, - -{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } }, -{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } }, -{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } }, -{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } }, -{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } }, -{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } }, - -{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } }, - -{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } }, -{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } }, - -{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, +{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB }, PPC_INST_STBUX }, + +{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH }, PPC_INST_SLLIQ }, +{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH }, PPC_INST_SLLIQ }, + +{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB }, PPC_INST_DCBTSTE }, + +{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB }, PPC_INST_STBUXE }, + +{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA }, PPC_INST_MFDCRX }, + +{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB }, PPC_INST_DOZ }, +{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB }, PPC_INST_DOZ }, +{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB }, PPC_INST_DOZO }, +{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB }, PPC_INST_DOZO }, + +{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_ADD }, +{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_CAX }, +{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_ADD }, +{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_CAX }, +{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_ADDO }, +{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_CAXO }, +{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB }, PPC_INST_ADDO }, +{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_CAXO }, + +{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L }, PPC_INST_TLBIEL }, + +{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA }, PPC_INST_MFAPIDI }, + +{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB }, PPC_INST_LSCBX }, +{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB }, PPC_INST_LSCBX }, + +{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB }, PPC_INST_DCBT }, + +{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB }, PPC_INST_LHZX }, + +{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB }, PPC_INST_EQV }, +{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB }, PPC_INST_EQV }, + +{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB }, PPC_INST_DCBTE }, + +{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB }, PPC_INST_LHZXE }, + +{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L }, PPC_INST_TLBIE }, +{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB }, PPC_INST_TLBI }, + +{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB }, PPC_INST_ECIWX }, + +{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB }, PPC_INST_LHZUX }, + +{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB }, PPC_INST_XOR }, +{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB }, PPC_INST_XOR }, + +{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB }, PPC_INST_LHZUXE }, + +{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT }, PPC_INST_MFEXISR }, +{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT }, PPC_INST_MFEXIER }, +{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT }, PPC_INST_MFBR0 }, +{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT }, PPC_INST_MFBR1 }, +{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT }, PPC_INST_MFBR2 }, +{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT }, PPC_INST_MFBR3 }, +{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT }, PPC_INST_MFBR4 }, +{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT }, PPC_INST_MFBR5 }, +{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT }, PPC_INST_MFBR6 }, +{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT }, PPC_INST_MFBR7 }, +{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT }, PPC_INST_MFBEAR }, +{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT }, PPC_INST_MFBESR }, +{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT }, PPC_INST_MFIOCR }, +{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMACR0 }, +{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMACT0 }, +{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMADA0 }, +{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMASA0 }, +{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMACC0 }, +{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMACR1 }, +{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMACT1 }, +{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMADA1 }, +{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMASA1 }, +{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMACC1 }, +{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMACR2 }, +{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMACT2 }, +{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMADA2 }, +{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMASA2 }, +{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMACC2 }, +{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMACR3 }, +{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMACT3 }, +{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMADA3 }, +{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMASA3 }, +{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMACC3 }, +{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDMASR }, +{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR }, PPC_INST_MFDCR }, + +{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB }, PPC_INST_DIV }, +{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB }, PPC_INST_DIV }, +{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB }, PPC_INST_DIVO }, +{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB }, PPC_INST_DIVO }, + +{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }, PPC_INST_MFPMR }, + +{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT }, PPC_INST_MFMQ }, +{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT }, PPC_INST_MFXER }, +{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT }, PPC_INST_MFRTCU }, +{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT }, PPC_INST_MFRTCL }, +{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT }, PPC_INST_MFDEC }, +{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT }, PPC_INST_MFDEC }, +{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT }, PPC_INST_MFLR }, +{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT }, PPC_INST_MFCTR }, +{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT }, PPC_INST_MFTID }, +{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT }, PPC_INST_MFDSISR }, +{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT }, PPC_INST_MFDAR }, +{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT }, PPC_INST_MFSDR0 }, +{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT }, PPC_INST_MFSDR1 }, +{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT }, PPC_INST_MFSRR0 }, +{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT }, PPC_INST_MFSRR1 }, +{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT }, PPC_INST_MFCFAR }, +{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFPID }, +{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT }, PPC_INST_MFPID }, +{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFCSRR0 }, +{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFCSRR1 }, +{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFDEAR }, +{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDEAR }, +{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFESR }, +{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT }, PPC_INST_MFESR }, +{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVPR }, +{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT }, PPC_INST_MFCMPA }, +{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT }, PPC_INST_MFCMPB }, +{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT }, PPC_INST_MFCMPC }, +{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT }, PPC_INST_MFCMPD }, +{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT }, PPC_INST_MFICR }, +{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT }, PPC_INST_MFDER }, +{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT }, PPC_INST_MFCOUNTA }, +{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT }, PPC_INST_MFCOUNTB }, +{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT }, PPC_INST_MFCMPE }, +{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT }, PPC_INST_MFCMPF }, +{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT }, PPC_INST_MFCMPG }, +{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT }, PPC_INST_MFCMPH }, +{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT }, PPC_INST_MFLCTRL1 }, +{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT }, PPC_INST_MFLCTRL2 }, +{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT }, PPC_INST_MFICTRL }, +{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT }, PPC_INST_MFBAR }, +{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT }, PPC_INST_MFVRSAVE }, +{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFUSPRG0 }, +{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR }, PPC_INST_MFTB }, +{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFTB }, +{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT }, PPC_INST_MFTBL }, +{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFTBL }, +{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT }, PPC_INST_MFTBU }, +{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFTBU }, +{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG }, PPC_INST_MFSPRG }, +{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT }, PPC_INST_MFSPRG0 }, +{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT }, PPC_INST_MFSPRG1 }, +{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT }, PPC_INST_MFSPRG2 }, +{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT }, PPC_INST_MFSPRG3 }, +{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT }, PPC_INST_MFSPRG4 }, +{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT }, PPC_INST_MFSPRG5 }, +{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT }, PPC_INST_MFSPRG6 }, +{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT }, PPC_INST_MFSPRG7 }, +{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT }, PPC_INST_MFASR }, +{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT }, PPC_INST_MFEAR }, +{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFPIR }, +{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT }, PPC_INST_MFPVR }, +{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFDBSR }, +{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDBSR }, +{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFDBCR0 }, +{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT }, PPC_INST_MFDBCR0 }, +{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFDBCR1 }, +{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT }, PPC_INST_MFDBCR1 }, +{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFDBCR2 }, +{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIAC1 }, +{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT }, PPC_INST_MFIAC1 }, +{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIAC2 }, +{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT }, PPC_INST_MFIAC2 }, +{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIAC3 }, +{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT }, PPC_INST_MFIAC3 }, +{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIAC4 }, +{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT }, PPC_INST_MFIAC4 }, +{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFDAC1 }, +{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDAC1 }, +{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFDAC2 }, +{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDAC2 }, +{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFDVC1 }, +{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT }, PPC_INST_MFDVC1 }, +{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFDVC2 }, +{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT }, PPC_INST_MFDVC2 }, +{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFTSR }, +{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT }, PPC_INST_MFTSR }, +{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFTCR }, +{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT }, PPC_INST_MFTCR }, +{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR0 }, +{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR1 }, +{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR2 }, +{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR3 }, +{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR4 }, +{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR5 }, +{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR6 }, +{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR7 }, +{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR8 }, +{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR9 }, +{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR10 }, +{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR11 }, +{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR12 }, +{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR13 }, +{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR14 }, +{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT }, PPC_INST_MFIVOR15 }, +{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT }, PPC_INST_MFSPEFSCR }, +{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT }, PPC_INST_MFBBEAR }, +{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT }, PPC_INST_MFBBTAR }, +{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT }, PPC_INST_MFIVOR32 }, +{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT }, PPC_INST_MFIVOR33 }, +{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT }, PPC_INST_MFIVOR34 }, +{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT }, PPC_INST_MFIVOR35 }, +{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT }, PPC_INST_MFIBATU }, +{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT }, PPC_INST_MFIBATL }, +{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT }, PPC_INST_MFDBATU }, +{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT }, PPC_INST_MFDBATL }, +{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT }, PPC_INST_MFIC_CST }, +{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT }, PPC_INST_MFIC_ADR }, +{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT }, PPC_INST_MFIC_DAT }, +{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT }, PPC_INST_MFDC_CST }, +{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT }, PPC_INST_MFDC_ADR }, +{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT }, PPC_INST_MFMCSRR0 }, +{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT }, PPC_INST_MFDC_DAT }, +{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT }, PPC_INST_MFMCSRR1 }, +{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT }, PPC_INST_MFMCSR }, +{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT }, PPC_INST_MFMCAR }, +{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT }, PPC_INST_MFDPDR }, +{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT }, PPC_INST_MFDPIR }, +{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT }, PPC_INST_MFIMMR }, +{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMI_CTR }, +{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMI_AP }, +{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMI_EPN }, +{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMI_TWC }, +{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMI_RPN }, +{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMD_CTR }, +{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT }, PPC_INST_MFM_CASID }, +{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMD_AP }, +{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMD_EPN }, +{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMD_TWB }, +{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMD_TWC }, +{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMD_RPN }, +{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT }, PPC_INST_MFM_TW }, +{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMI_DBCAM }, +{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMI_DBRAM0 }, +{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMI_DBRAM1 }, +{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMD_DBCAM }, +{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMD_DBRAM0 }, +{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT }, PPC_INST_MFMD_DBRAM1 }, +{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT }, PPC_INST_MFUMMCR0 }, +{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT }, PPC_INST_MFUPMC1 }, +{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT }, PPC_INST_MFUPMC2 }, +{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT }, PPC_INST_MFUSIA }, +{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT }, PPC_INST_MFUMMCR1 }, +{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT }, PPC_INST_MFUPMC3 }, +{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT }, PPC_INST_MFUPMC4 }, +{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT }, PPC_INST_MFZPR }, +{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT }, PPC_INST_MFCCR0 }, +{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT }, PPC_INST_MFMMCR0 }, +{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT }, PPC_INST_MFPMC1 }, +{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT }, PPC_INST_MFSGR }, +{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT }, PPC_INST_MFPMC2 }, +{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDCWR }, +{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT }, PPC_INST_MFSIA }, +{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT }, PPC_INST_MFSLER }, +{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT }, PPC_INST_MFMMCR1 }, +{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT }, PPC_INST_MFSU0R }, +{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT }, PPC_INST_MFPMC3 }, +{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT }, PPC_INST_MFPMC4 }, +{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT }, PPC_INST_MFICDBDR }, +{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT }, PPC_INST_MFEVPR }, +{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT }, PPC_INST_MFCDBCR }, +{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT }, PPC_INST_MFPIT }, +{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT }, PPC_INST_MFTBHI }, +{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT }, PPC_INST_MFTBLO }, +{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT }, PPC_INST_MFSRR2 }, +{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT }, PPC_INST_MFSRR3 }, +{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT }, PPC_INST_MFL2CR }, +{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT }, PPC_INST_MFDCCR }, +{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT }, PPC_INST_MFICCR }, +{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT }, PPC_INST_MFICTC }, +{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT }, PPC_INST_MFPBL1 }, +{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT }, PPC_INST_MFTHRM1 }, +{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT }, PPC_INST_MFPBU1 }, +{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT }, PPC_INST_MFTHRM2 }, +{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT }, PPC_INST_MFPBL2 }, +{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT }, PPC_INST_MFTHRM3 }, +{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT }, PPC_INST_MFPBU2 }, +{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR }, PPC_INST_MFSPR }, + +{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB }, PPC_INST_LWAX }, + +{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM }, PPC_INST_DST }, +{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM }, PPC_INST_DSTT }, + +{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB }, PPC_INST_LHAX }, + +{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB }, PPC_INST_LHAXE }, + +{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM }, PPC_INST_DSTST }, +{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM }, PPC_INST_DSTSTT }, + +{ "dccci", X(31,454), XRT_MASK, PPC403 | PPC440, { RA, RB }, PPC_INST_DCCCI }, + +{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA }, PPC_INST_ABS }, +{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA }, PPC_INST_ABS }, +{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA }, PPC_INST_ABSO }, +{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA }, PPC_INST_ABSO }, + +{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB }, PPC_INST_DIVS }, +{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB }, PPC_INST_DIVS }, +{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB }, PPC_INST_DIVSO }, +{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB }, PPC_INST_DIVSO }, + +{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 }, PPC_INST_TLBIA }, + +{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB }, PPC_INST_LWAUX }, + +{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB }, PPC_INST_LHAUX }, + +{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB }, PPC_INST_LHAUXE }, + +{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS }, PPC_INST_MTDCRX }, + +{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }, PPC_INST_DCBLC }, + +{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB }, PPC_INST_SUBFE64 }, +{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB }, PPC_INST_SUBFE64O }, + +{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB }, PPC_INST_ADDE64 }, +{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB }, PPC_INST_ADDE64O }, + +{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }, PPC_INST_DCBLCE }, + +{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB }, PPC_INST_SLBMTE }, + +{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB }, PPC_INST_STHX }, + +{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB }, PPC_INST_CMPB }, + +{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB }, PPC_INST_LFQX }, + +{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB }, PPC_INST_LFDPX }, + +{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB }, PPC_INST_LFQUX }, + +{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB }, PPC_INST_STFQX }, + +{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB }, PPC_INST_STFDPX }, + +{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB }, PPC_INST_STFQUX }, + +{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB }, PPC_INST_ORC }, +{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB }, PPC_INST_ORC }, + +{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 }, PPC_INST_SRADI }, +{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 }, PPC_INST_SRADI }, + +{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB }, PPC_INST_STHXE }, + +{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB }, PPC_INST_SLBIE }, + +{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB }, PPC_INST_ECOWX }, + +{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB }, PPC_INST_STHUX }, + +{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB }, PPC_INST_STHUXE }, + +{ "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }, PPC_INST_CCTPL }, +{ "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }, PPC_INST_CCTPM }, +{ "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }, PPC_INST_CCTPH }, +{ "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }, PPC_INST_DB8CYC }, +{ "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }, PPC_INST_DB10CYC }, +{ "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }, PPC_INST_DB12CYC }, +{ "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }, PPC_INST_DB16CYC }, +{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS }, PPC_INST_MR }, +{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB }, PPC_INST_OR }, +{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS }, PPC_INST_MR }, +{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB }, PPC_INST_OR }, + +{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS }, PPC_INST_MTEXISR }, +{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS }, PPC_INST_MTEXIER }, +{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS }, PPC_INST_MTBR0 }, +{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS }, PPC_INST_MTBR1 }, +{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS }, PPC_INST_MTBR2 }, +{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS }, PPC_INST_MTBR3 }, +{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS }, PPC_INST_MTBR4 }, +{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS }, PPC_INST_MTBR5 }, +{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS }, PPC_INST_MTBR6 }, +{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS }, PPC_INST_MTBR7 }, +{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS }, PPC_INST_MTBEAR }, +{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS }, PPC_INST_MTBESR }, +{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS }, PPC_INST_MTIOCR }, +{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMACR0 }, +{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMACT0 }, +{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMADA0 }, +{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMASA0 }, +{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMACC0 }, +{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMACR1 }, +{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMACT1 }, +{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMADA1 }, +{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMASA1 }, +{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMACC1 }, +{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMACR2 }, +{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMACT2 }, +{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMADA2 }, +{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMASA2 }, +{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMACC2 }, +{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMACR3 }, +{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMACT3 }, +{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMADA3 }, +{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMASA3 }, +{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMACC3 }, +{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDMASR }, +{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS }, PPC_INST_MTDCR }, + +{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA }, PPC_INST_SUBFZE64 }, +{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA }, PPC_INST_SUBFZE64O }, + +{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_DIVDU }, +{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_DIVDU }, +{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_DIVDUO }, +{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_DIVDUO }, + +{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA }, PPC_INST_ADDZE64 }, +{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA }, PPC_INST_ADDZE64O }, + +{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_DIVWU }, +{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_DIVWU }, +{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_DIVWUO }, +{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_DIVWUO }, + +{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS }, PPC_INST_MTMQ }, +{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS }, PPC_INST_MTXER }, +{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS }, PPC_INST_MTLR }, +{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS }, PPC_INST_MTCTR }, +{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS }, PPC_INST_MTTID }, +{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS }, PPC_INST_MTDSISR }, +{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS }, PPC_INST_MTDAR }, +{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS }, PPC_INST_MTRTCU }, +{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS }, PPC_INST_MTRTCL }, +{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS }, PPC_INST_MTDEC }, +{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS }, PPC_INST_MTSDR0 }, +{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS }, PPC_INST_MTSDR1 }, +{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS }, PPC_INST_MTSRR0 }, +{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS }, PPC_INST_MTSRR1 }, +{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS }, PPC_INST_MTCFAR }, +{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTPID }, +{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS }, PPC_INST_MTPID }, +{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTDECAR }, +{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTCSRR0 }, +{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTCSRR1 }, +{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTDEAR }, +{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDEAR }, +{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTESR }, +{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS }, PPC_INST_MTESR }, +{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVPR }, +{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS }, PPC_INST_MTCMPA }, +{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS }, PPC_INST_MTCMPB }, +{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS }, PPC_INST_MTCMPC }, +{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS }, PPC_INST_MTCMPD }, +{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS }, PPC_INST_MTICR }, +{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS }, PPC_INST_MTDER }, +{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS }, PPC_INST_MTCOUNTA }, +{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS }, PPC_INST_MTCOUNTB }, +{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS }, PPC_INST_MTCMPE }, +{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS }, PPC_INST_MTCMPF }, +{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS }, PPC_INST_MTCMPG }, +{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS }, PPC_INST_MTCMPH }, +{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS }, PPC_INST_MTLCTRL1 }, +{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS }, PPC_INST_MTLCTRL2 }, +{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS }, PPC_INST_MTICTRL }, +{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS }, PPC_INST_MTBAR }, +{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS }, PPC_INST_MTVRSAVE }, +{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTUSPRG0 }, +{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS }, PPC_INST_MTSPRG }, +{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS }, PPC_INST_MTSPRG0 }, +{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS }, PPC_INST_MTSPRG1 }, +{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS }, PPC_INST_MTSPRG2 }, +{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS }, PPC_INST_MTSPRG3 }, +{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS }, PPC_INST_MTSPRG4 }, +{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS }, PPC_INST_MTSPRG5 }, +{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS }, PPC_INST_MTSPRG6 }, +{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS }, PPC_INST_MTSPRG7 }, +{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS }, PPC_INST_MTASR }, +{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS }, PPC_INST_MTEAR }, +{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS }, PPC_INST_MTTBL }, +{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS }, PPC_INST_MTTBU }, +{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTDBSR }, +{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDBSR }, +{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTDBCR0 }, +{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS }, PPC_INST_MTDBCR0 }, +{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTDBCR1 }, +{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS }, PPC_INST_MTDBCR1 }, +{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTDBCR2 }, +{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIAC1 }, +{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS }, PPC_INST_MTIAC1 }, +{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIAC2 }, +{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS }, PPC_INST_MTIAC2 }, +{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIAC3 }, +{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS }, PPC_INST_MTIAC3 }, +{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIAC4 }, +{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS }, PPC_INST_MTIAC4 }, +{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTDAC1 }, +{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDAC1 }, +{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTDAC2 }, +{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDAC2 }, +{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTDVC1 }, +{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS }, PPC_INST_MTDVC1 }, +{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTDVC2 }, +{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS }, PPC_INST_MTDVC2 }, +{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTTSR }, +{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS }, PPC_INST_MTTSR }, +{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTTCR }, +{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS }, PPC_INST_MTTCR }, +{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR0 }, +{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR1 }, +{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR2 }, +{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR3 }, +{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR4 }, +{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR5 }, +{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR6 }, +{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR7 }, +{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR8 }, +{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR9 }, +{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR10 }, +{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR11 }, +{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR12 }, +{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR13 }, +{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR14 }, +{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS }, PPC_INST_MTIVOR15 }, +{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS }, PPC_INST_MTSPEFSCR }, +{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS }, PPC_INST_MTBBEAR }, +{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS }, PPC_INST_MTBBTAR }, +{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS }, PPC_INST_MTIVOR32 }, +{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS }, PPC_INST_MTIVOR33 }, +{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS }, PPC_INST_MTIVOR34 }, +{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS }, PPC_INST_MTIVOR35 }, +{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS }, PPC_INST_MTIBATU }, +{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS }, PPC_INST_MTIBATL }, +{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS }, PPC_INST_MTDBATU }, +{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS }, PPC_INST_MTDBATL }, +{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS }, PPC_INST_MTMCSRR0 }, +{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS }, PPC_INST_MTMCSRR1 }, +{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS }, PPC_INST_MTMCSR }, +{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS }, PPC_INST_MTUMMCR0 }, +{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS }, PPC_INST_MTUPMC1 }, +{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS }, PPC_INST_MTUPMC2 }, +{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS }, PPC_INST_MTUSIA }, +{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS }, PPC_INST_MTUMMCR1 }, +{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS }, PPC_INST_MTUPMC3 }, +{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS }, PPC_INST_MTUPMC4 }, +{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS }, PPC_INST_MTZPR }, +{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS }, PPC_INST_MTCCR0 }, +{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS }, PPC_INST_MTMMCR0 }, +{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS }, PPC_INST_MTSGR }, +{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS }, PPC_INST_MTPMC1 }, +{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDCWR }, +{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS }, PPC_INST_MTPMC2 }, +{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS }, PPC_INST_MTSLER }, +{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS }, PPC_INST_MTSIA }, +{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS }, PPC_INST_MTSU0R }, +{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS }, PPC_INST_MTMMCR1 }, +{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS }, PPC_INST_MTPMC3 }, +{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS }, PPC_INST_MTPMC4 }, +{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS }, PPC_INST_MTICDBDR }, +{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS }, PPC_INST_MTEVPR }, +{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS }, PPC_INST_MTCDBCR }, +{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS }, PPC_INST_MTPIT }, +{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS }, PPC_INST_MTTBHI }, +{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS }, PPC_INST_MTTBLO }, +{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS }, PPC_INST_MTSRR2 }, +{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS }, PPC_INST_MTSRR3 }, +{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS }, PPC_INST_MTL2CR }, +{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS }, PPC_INST_MTDCCR }, +{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS }, PPC_INST_MTICCR }, +{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS }, PPC_INST_MTICTC }, +{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS }, PPC_INST_MTPBL1 }, +{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS }, PPC_INST_MTTHRM1 }, +{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS }, PPC_INST_MTPBU1 }, +{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS }, PPC_INST_MTTHRM2 }, +{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS }, PPC_INST_MTPBL2 }, +{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS }, PPC_INST_MTTHRM3 }, +{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS }, PPC_INST_MTPBU2 }, +{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS }, PPC_INST_MTSPR }, + +{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB }, PPC_INST_DCBI }, + +{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB }, PPC_INST_NAND }, +{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB }, PPC_INST_NAND }, + +{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB }, PPC_INST_DCBIE }, + +{ "dcread", X(31,486), X_MASK, PPC403 | PPC440, { RT, RA, RB }, PPC_INST_DCREAD }, + +{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }, PPC_INST_MTPMR }, + +{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }, PPC_INST_ICBTLS }, + +{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA }, PPC_INST_NABS }, +{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA }, PPC_INST_SUBFME64 }, +{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA }, PPC_INST_NABS }, +{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA }, PPC_INST_NABSO }, +{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA }, PPC_INST_SUBFME64O }, +{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA }, PPC_INST_NABSO }, + +{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_DIVD }, +{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_DIVD }, +{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_DIVDO }, +{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB }, PPC_INST_DIVDO }, + +{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA }, PPC_INST_ADDME64 }, +{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA }, PPC_INST_ADDME64O }, + +{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_DIVW }, +{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_DIVW }, +{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_DIVWO }, +{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB }, PPC_INST_DIVWO }, -{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }}, +{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }, PPC_INST_ICBTLSE }, -{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } }, +{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 }, PPC_INST_SLBIA }, -{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, +{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA }, PPC_INST_CLI }, -{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } }, +{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB }, PPC_INST_STDCXE }, -{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, +{ "mcrxr", X(31,512), XRARB_MASK | (3 << 21), COM, { BF }, PPC_INST_MCRXR }, -{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }}, -{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } }, +{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }, PPC_INST_BBLELS }, +{ "mcrxr64", X(31,544), XRARB_MASK | (3 << 21), BOOKE64, { BF }, PPC_INST_MCRXR64 }, -{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, +{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA }, PPC_INST_CLCS }, -{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } }, +{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB }, PPC_INST_LDBRX }, -{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, -{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, +{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB }, PPC_INST_LSWX }, +{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_LSX }, -{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } }, -{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, +{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB }, PPC_INST_LWBRX }, +{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_LBRX }, -{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, +{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB }, PPC_INST_LFSX }, -{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } }, -{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } }, +{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB }, PPC_INST_SRW }, +{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB }, PPC_INST_SR }, +{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB }, PPC_INST_SRW }, +{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB }, PPC_INST_SR }, -{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } }, -{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } }, +{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB }, PPC_INST_RRIB }, +{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB }, PPC_INST_RRIB }, -{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } }, -{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } }, +{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB }, PPC_INST_SRD }, +{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB }, PPC_INST_SRD }, -{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, -{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, +{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB }, PPC_INST_MASKIR }, +{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB }, PPC_INST_MASKIR }, -{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } }, +{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB }, PPC_INST_LWBRXE }, -{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } }, +{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB }, PPC_INST_LFSXE }, -{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }}, +{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }, PPC_INST_BBELR }, -{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, +{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 }, PPC_INST_TLBSYNC }, -{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, +{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB }, PPC_INST_LFSUX }, -{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } }, +{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB }, PPC_INST_LFSUXE }, -{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, +{ "mfsr", X(31,595), XRB_MASK | (1 << 20), COM32, { RT, SR }, PPC_INST_MFSR }, -{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } }, -{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } }, +{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB }, PPC_INST_LSWI }, +{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB }, PPC_INST_LSI }, -{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } }, -{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, -{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } }, -{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, -{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } }, +{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 }, PPC_INST_LWSYNC }, +{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 }, PPC_INST_PTESYNC }, +{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 }, PPC_INST_MSYNC }, +{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS }, PPC_INST_SYNC }, +{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 }, PPC_INST_DCS }, -{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } }, +{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB }, PPC_INST_LFDX }, -{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } }, +{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB }, PPC_INST_LFDXE }, -{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } }, +{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB }, PPC_INST_MFFGPR }, -{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, +{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_MFSRI }, -{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, +{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA }, PPC_INST_DCLST }, -{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } }, +{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB }, PPC_INST_LFDUX }, -{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } }, +{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB }, PPC_INST_LFDUXE }, -{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, +{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB }, PPC_INST_MFSRIN }, -{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } }, +{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB }, PPC_INST_STDBRX }, -{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, -{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } }, +{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB }, PPC_INST_STSWX }, +{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB }, PPC_INST_STSX }, -{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } }, -{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } }, +{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB }, PPC_INST_STWBRX }, +{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB }, PPC_INST_STBRX }, -{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } }, +{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB }, PPC_INST_STFSX }, -{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, -{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } }, +{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB }, PPC_INST_SRQ }, +{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB }, PPC_INST_SRQ }, -{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, -{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, +{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB }, PPC_INST_SRE }, +{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB }, PPC_INST_SRE }, -{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } }, +{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB }, PPC_INST_STWBRXE }, -{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } }, +{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB }, PPC_INST_STFSXE }, -{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, +{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB }, PPC_INST_STFSUX }, -{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } }, -{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } }, +{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH }, PPC_INST_SRIQ }, +{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH }, PPC_INST_SRIQ }, -{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } }, +{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB }, PPC_INST_STFSUXE }, -{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } }, -{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } }, +{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB }, PPC_INST_STSWI }, +{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB }, PPC_INST_STSI }, -{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } }, +{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB }, PPC_INST_STFDX }, -{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, -{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, +{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB }, PPC_INST_SRLQ }, +{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB }, PPC_INST_SRLQ }, -{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, -{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } }, +{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB }, PPC_INST_SREQ }, +{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB }, PPC_INST_SREQ }, -{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } }, +{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB }, PPC_INST_STFDXE }, -{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } }, +{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB }, PPC_INST_MFTGPR }, -{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, +{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB }, PPC_INST_DCBA }, -{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, +{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB }, PPC_INST_STFDUX }, -{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } }, -{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } }, +{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH }, PPC_INST_SRLIQ }, +{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH }, PPC_INST_SRLIQ }, -{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } }, +{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB }, PPC_INST_DCBAE }, -{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } }, +{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB }, PPC_INST_STFDUXE }, -{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, -{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } }, +{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB }, PPC_INST_TLBIVAX }, +{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB }, PPC_INST_TLBIVAXE }, -{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } }, +{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB }, PPC_INST_LWZCIX }, -{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } }, +{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB }, PPC_INST_LHBRX }, -{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, -{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } }, +{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB }, PPC_INST_SRAW }, +{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB }, PPC_INST_SRA }, +{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB }, PPC_INST_SRAW }, +{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB }, PPC_INST_SRA }, -{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, -{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, +{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB }, PPC_INST_SRAD }, +{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB }, PPC_INST_SRAD }, -{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } }, +{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB }, PPC_INST_LHBRXE }, -{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } }, -{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } }, +{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB }, PPC_INST_LDXE }, +{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB }, PPC_INST_LDUXE }, -{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, +{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB }, PPC_INST_RAC }, -{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } }, +{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB }, PPC_INST_LHZCIX }, -{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, -{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, +{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM }, PPC_INST_DSS }, +{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 }, PPC_INST_DSSALL }, -{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, -{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, -{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } }, -{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } }, +{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH }, PPC_INST_SRAWI }, +{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH }, PPC_INST_SRAI }, +{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH }, PPC_INST_SRAWI }, +{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH }, PPC_INST_SRAI }, -{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, +{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB }, PPC_INST_SLBMFEV }, -{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } }, +{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB }, PPC_INST_LBZCIX }, -{ "mbar", X(31,854), X_MASK, BOOKE, { MO } }, -{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, +{ "mbar", X(31,854), X_MASK, BOOKE, { MO }, PPC_INST_MBAR }, +{ "eieio", X(31,854), 0xffffffff, PPC, { 0 }, PPC_INST_EIEIO }, -{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } }, +{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB }, PPC_INST_LFIWAX }, -{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } }, +{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB }, PPC_INST_LDCIX }, -{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, -{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, -{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } }, -{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } }, +{ "tlbsx", XRC(31,914,0), X_MASK, PPC403 | BOOKE, { RTO, RA, RB }, PPC_INST_TLBSX }, +{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403 | BOOKE, { RTO, RA, RB }, PPC_INST_TLBSX }, +{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB }, PPC_INST_TLBSXE }, +{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB }, PPC_INST_TLBSXE }, -{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, +{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB }, PPC_INST_SLBMFEE }, -{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } }, +{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB }, PPC_INST_STWCIX }, -{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } }, +{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB }, PPC_INST_STHBRX }, -{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, -{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } }, +{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB }, PPC_INST_SRAQ }, +{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB }, PPC_INST_SRAQ }, -{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } }, -{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } }, +{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB }, PPC_INST_SREA }, +{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB }, PPC_INST_SREA }, -{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } }, -{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } }, -{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, -{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, +{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS }, PPC_INST_EXTSH }, +{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS }, PPC_INST_EXTS }, +{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS }, PPC_INST_EXTSH }, +{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS }, PPC_INST_EXTS }, -{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } }, +{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB }, PPC_INST_STHBRXE }, -{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } }, +{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB }, PPC_INST_STDXE }, -{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, -{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, -{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, +{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA }, PPC_INST_TLBREHI }, +{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA }, PPC_INST_TLBRELO }, +{ "tlbre", X(31,946), X_MASK, PPC403 | BOOKE, { RSO, RAOPT, SHO }, PPC_INST_TLBRE }, -{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } }, +{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB }, PPC_INST_STHCIX }, -{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, -{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, +{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH }, PPC_INST_SRAIQ }, +{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH }, PPC_INST_SRAIQ }, -{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, -{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, +{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS}, PPC_INST_EXTSB }, +{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS}, PPC_INST_EXTSB }, -{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } }, +{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB }, PPC_INST_STDUXE }, -{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } }, +{ "iccci", X(31,966), XRT_MASK, PPC403 | PPC440, { RA, RB }, PPC_INST_ICCCI }, -{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, -{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, -{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, -{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, +{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA }, PPC_INST_TLBWEHI }, +{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA }, PPC_INST_TLBWELO }, +{ "tlbwe", X(31,978), X_MASK, PPC403 | BOOKE, { RSO, RAOPT, SHO }, PPC_INST_TLBWE }, +{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB }, PPC_INST_TLBLD }, -{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } }, +{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB }, PPC_INST_STBCIX }, -{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, +{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB }, PPC_INST_ICBI }, -{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } }, +{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB }, PPC_INST_STFIWX }, -{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } }, -{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } }, +{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS }, PPC_INST_EXTSW }, +{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS }, PPC_INST_EXTSW }, -{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } }, +{ "icread", X(31,998), XRT_MASK, PPC403 | PPC440, { RA, RB }, PPC_INST_ICREAD }, -{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, -{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } }, +{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB }, PPC_INST_ICBIE }, +{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB }, PPC_INST_STFIWXE }, -{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, +{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB }, PPC_INST_TLBLI }, -{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } }, +{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB }, PPC_INST_STDCIX }, -{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } }, -{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, -{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, +{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB }, PPC_INST_DCBZL }, +{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB }, PPC_INST_DCBZ }, +{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB }, PPC_INST_DCLZ }, -{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } }, +{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB }, PPC_INST_DCBZE }, -{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } }, -{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } }, -{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } }, -{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, -{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, +{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB }, PPC_INST_LVEBX }, +{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB }, PPC_INST_LVEHX }, +{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB }, PPC_INST_LVEWX }, +{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB }, PPC_INST_LVSL }, +{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB }, PPC_INST_LVSR }, +{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB }, PPC_INST_LVX }, +{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB }, PPC_INST_LVXL }, +{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB }, PPC_INST_STVEBX }, +{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB }, PPC_INST_STVEHX }, +{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB }, PPC_INST_STVEWX }, +{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB }, PPC_INST_STVX }, +{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB }, PPC_INST_STVXL }, /* New load/store left/right index vector instructions that are in the Cell only. */ -{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } }, -{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } }, -{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } }, -{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } }, -{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } }, -{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } }, -{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } }, -{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } }, +{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB }, PPC_INST_LVLX }, +{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB }, PPC_INST_LVLXL }, +{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB }, PPC_INST_LVRX }, +{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB }, PPC_INST_LVRXL }, +{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB }, PPC_INST_STVLX }, +{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB }, PPC_INST_STVLXL }, +{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB }, PPC_INST_STVRX }, +{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB }, PPC_INST_STVRXL }, -{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, -{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } }, +{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 }, PPC_INST_LWZ }, +{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 }, PPC_INST_L }, -{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, -{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } }, +{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL }, PPC_INST_LWZU }, +{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 }, PPC_INST_LU }, -{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } }, +{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 }, PPC_INST_LBZ }, -{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, +{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL }, PPC_INST_LBZU }, -{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } }, -{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } }, +{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 }, PPC_INST_STW }, +{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 }, PPC_INST_ST }, -{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, -{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } }, +{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS }, PPC_INST_STWU }, +{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 }, PPC_INST_STU }, -{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } }, +{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 }, PPC_INST_STB }, -{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, +{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS }, PPC_INST_STBU }, -{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } }, +{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 }, PPC_INST_LHZ }, -{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, +{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL }, PPC_INST_LHZU }, -{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } }, +{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 }, PPC_INST_LHA }, -{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, +{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL }, PPC_INST_LHAU }, -{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } }, +{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 }, PPC_INST_STH }, -{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, +{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS }, PPC_INST_STHU }, -{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, -{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } }, +{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM }, PPC_INST_LMW }, +{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 }, PPC_INST_LM }, -{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } }, -{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } }, +{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 }, PPC_INST_STMW }, +{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 }, PPC_INST_STM }, -{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, +{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 }, PPC_INST_LFS }, -{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, +{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS }, PPC_INST_LFSU }, -{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, +{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 }, PPC_INST_LFD }, -{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, +{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS }, PPC_INST_LFDU }, -{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } }, +{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 }, PPC_INST_STFS }, -{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, +{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS }, PPC_INST_STFSU }, -{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } }, +{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 }, PPC_INST_STFD }, -{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, +{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS }, PPC_INST_STFDU }, -{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } }, +{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ }, PPC_INST_LQ }, -{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, +{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 }, PPC_INST_LFQ }, -{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, +{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 }, PPC_INST_LFQU }, -{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } }, +{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 }, PPC_INST_LFDP }, -{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } }, -{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } }, -{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } }, -{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } }, -{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } }, -{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } }, -{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } }, -{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } }, -{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } }, -{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } }, -{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } }, -{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } }, -{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } }, -{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } }, +{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 }, PPC_INST_LBZE }, +{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL }, PPC_INST_LBZUE }, +{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 }, PPC_INST_LHZE }, +{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL }, PPC_INST_LHZUE }, +{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 }, PPC_INST_LHAE }, +{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL }, PPC_INST_LHAUE }, +{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 }, PPC_INST_LWZE }, +{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL }, PPC_INST_LWZUE }, +{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 }, PPC_INST_STBE }, +{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS }, PPC_INST_STBUE }, +{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 }, PPC_INST_STHE }, +{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS }, PPC_INST_STHUE }, +{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 }, PPC_INST_STWE }, +{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS }, PPC_INST_STWUE }, -{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } }, +{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 }, PPC_INST_LD }, -{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, +{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL }, PPC_INST_LDU }, -{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } }, +{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 }, PPC_INST_LWA }, -{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, -{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DADD }, +{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DADD }, -{ "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, -{ "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, +{ "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC }, PPC_INST_DQUA }, +{ "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC }, PPC_INST_DQUA }, -{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, +{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB }, PPC_INST_FDIVS }, +{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB }, PPC_INST_FDIVS }, -{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, +{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB }, PPC_INST_FSUBS }, +{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB }, PPC_INST_FSUBS }, -{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, +{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB }, PPC_INST_FADDS }, +{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB }, PPC_INST_FADDS }, -{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, +{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB }, PPC_INST_FSQRTS }, +{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB }, PPC_INST_FSQRTS }, -{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, -{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, +{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L }, PPC_INST_FRES }, +{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L }, PPC_INST_FRES }, -{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, -{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, +{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC }, PPC_INST_FMULS }, +{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC }, PPC_INST_FMULS }, -{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, -{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, +{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L }, PPC_INST_FRSQRTES }, +{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L }, PPC_INST_FRSQRTES }, -{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, +{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB }, PPC_INST_FMSUBS }, +{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB }, PPC_INST_FMSUBS }, -{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, +{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB }, PPC_INST_FMADDS }, +{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB }, PPC_INST_FMADDS }, -{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, +{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB }, PPC_INST_FNMSUBS }, +{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB }, PPC_INST_FNMSUBS }, -{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, +{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB }, PPC_INST_FNMADDS }, +{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB }, PPC_INST_FNMADDS }, -{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, -{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DMUL }, +{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DMUL }, -{ "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, -{ "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, +{ "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC }, PPC_INST_DRRND }, +{ "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC }, PPC_INST_DRRND }, -{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, -{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, +{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 }, PPC_INST_DSCLI }, +{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 }, PPC_INST_DSCLI }, -{ "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, -{ "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, +{ "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC }, PPC_INST_DQUAI }, +{ "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC }, PPC_INST_DQUAI }, -{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, -{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, +{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 }, PPC_INST_DSCRI }, +{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 }, PPC_INST_DSCRI }, -{ "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, -{ "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, +{ "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC }, PPC_INST_DRINTX }, +{ "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC }, PPC_INST_DRINTX }, -{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } }, +{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB }, PPC_INST_DCMPO }, -{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } }, -{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } }, -{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } }, +{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB }, PPC_INST_DTSTEX }, +{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM }, PPC_INST_DTSTDC }, +{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM }, PPC_INST_DTSTDG }, -{ "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, -{ "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, +{ "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC }, PPC_INST_DRINTN }, +{ "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC }, PPC_INST_DRINTN }, -{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } }, -{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } }, +{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DCTDP }, +{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DCTDP }, -{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } }, -{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } }, +{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DCTFIX }, +{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DCTFIX }, -{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, -{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } }, +{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB }, PPC_INST_DDEDPD }, +{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB }, PPC_INST_DDEDPD }, -{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } }, -{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } }, +{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DXEX }, +{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DXEX }, -{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, -{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DSUB }, +{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DSUB }, -{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, -{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DDIV }, +{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DDIV }, -{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } }, +{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB }, PPC_INST_DCMPU }, -{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } }, +{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB }, PPC_INST_DTSTSF }, -{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } }, -{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } }, +{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DRSP }, +{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DRSP }, -{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } }, -{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } }, +{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DCFFIX }, +{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DCFFIX }, -{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } }, -{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } }, +{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB }, PPC_INST_DENBCD }, +{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB }, PPC_INST_DENBCD }, -{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, -{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DIEX }, +{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DIEX }, -{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, +{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA }, PPC_INST_STFQ }, -{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, +{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA }, PPC_INST_STFQU }, -{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } }, +{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 }, PPC_INST_STFDP }, -{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } }, -{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } }, -{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, -{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } }, -{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, -{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } }, -{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } }, -{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } }, -{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, -{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } }, -{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, -{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } }, +{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 }, PPC_INST_LDE }, +{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 }, PPC_INST_LDUE }, +{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 }, PPC_INST_LFSE }, +{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS }, PPC_INST_LFSUE }, +{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 }, PPC_INST_LFDE }, +{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS }, PPC_INST_LFDUE }, +{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 }, PPC_INST_STDE }, +{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS }, PPC_INST_STDUE }, +{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 }, PPC_INST_STFSE }, +{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS }, PPC_INST_STFSUE }, +{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 }, PPC_INST_STFDE }, +{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS }, PPC_INST_STFDUE }, -{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } }, +{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 }, PPC_INST_STD }, -{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, +{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS }, PPC_INST_STDU }, -{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } }, +{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 }, PPC_INST_STQ }, -{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, +{ "fcmpu", X(63,0), X_MASK | (3 << 21), COM, { BF, FRA, FRB }, PPC_INST_FCMPU }, -{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, -{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DADDQ }, +{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DADDQ }, -{ "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, -{ "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, +{ "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC }, PPC_INST_DQUAQ }, +{ "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC }, PPC_INST_DQUAQ }, -{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } }, -{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_FCPSGN }, +{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_FCPSGN }, -{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, -{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, +{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB }, PPC_INST_FRSP }, +{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB }, PPC_INST_FRSP }, -{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } }, -{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, -{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } }, -{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, +{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB }, PPC_INST_FCTIW }, +{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB }, PPC_INST_FCIR }, +{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB }, PPC_INST_FCTIW }, +{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB }, PPC_INST_FCIR }, -{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, -{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, -{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } }, -{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, +{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB }, PPC_INST_FCTIWZ }, +{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB }, PPC_INST_FCIRZ }, +{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB }, PPC_INST_FCTIWZ }, +{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB }, PPC_INST_FCIRZ }, -{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, -{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, +{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB }, PPC_INST_FDIV }, +{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB }, PPC_INST_FD }, +{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB }, PPC_INST_FDIV }, +{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB }, PPC_INST_FD }, -{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, -{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, +{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB }, PPC_INST_FSUB }, +{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB }, PPC_INST_FS }, +{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB }, PPC_INST_FSUB }, +{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB }, PPC_INST_FS }, -{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, -{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, +{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB }, PPC_INST_FADD }, +{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB }, PPC_INST_FA }, +{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB }, PPC_INST_FADD }, +{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB }, PPC_INST_FA }, -{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, -{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, +{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB }, PPC_INST_FSQRT }, +{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB }, PPC_INST_FSQRT }, -{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, +{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB }, PPC_INST_FSEL }, +{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB }, PPC_INST_FSEL }, -{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, -{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, +{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L }, PPC_INST_FRE }, +{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L }, PPC_INST_FRE }, -{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, -{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, -{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, -{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, +{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC }, PPC_INST_FMUL }, +{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC }, PPC_INST_FM }, +{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC }, PPC_INST_FMUL }, +{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC }, PPC_INST_FM }, -{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, -{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, +{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L }, PPC_INST_FRSQRTE }, +{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L }, PPC_INST_FRSQRTE }, -{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, -{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, +{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FMSUB }, +{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FMS }, +{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FMSUB }, +{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FMS }, -{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, -{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, +{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FMADD }, +{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FMA }, +{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FMADD }, +{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FMA }, -{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, -{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, +{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FNMSUB }, +{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FNMS }, +{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FNMSUB }, +{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FNMS }, -{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, -{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, +{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FNMADD }, +{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FNMA }, +{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FNMADD }, +{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB }, PPC_INST_FNMA }, -{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, +{ "fcmpo", X(63,32), X_MASK | (3 << 21), COM, { BF, FRA, FRB }, PPC_INST_FCMPO }, -{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, -{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DMULQ }, +{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DMULQ }, -{ "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, -{ "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, +{ "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC }, PPC_INST_DRRNDQ }, +{ "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC }, PPC_INST_DRRNDQ }, -{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, -{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, +{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT }, PPC_INST_MTFSB1 }, +{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT }, PPC_INST_MTFSB1 }, -{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } }, -{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } }, +{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB }, PPC_INST_FNEG }, +{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB }, PPC_INST_FNEG }, -{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, +{ "mcrfs", X(63,64), XRB_MASK | (3 << 21) | (3 << 16), COM, { BF, BFA }, PPC_INST_MCRFS }, -{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, -{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, +{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 }, PPC_INST_DSCLIQ }, +{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 }, PPC_INST_DSCLIQ }, -{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, -{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, +{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC }, PPC_INST_DQUAIQ }, +{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC }, PPC_INST_DQUAIQ }, -{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, -{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, +{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT }, PPC_INST_MTFSB0 }, +{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT }, PPC_INST_MTFSB0 }, -{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, -{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, +{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB }, PPC_INST_FMR }, +{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB }, PPC_INST_FMR }, -{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, -{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, +{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 }, PPC_INST_DSCRIQ }, +{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 }, PPC_INST_DSCRIQ }, -{ "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, -{ "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, +{ "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC }, PPC_INST_DRINTXQ }, +{ "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC }, PPC_INST_DRINTXQ }, -{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } }, +{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB }, PPC_INST_DCMPOQ }, -{ "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } }, -{ "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } }, +{ "mtfsfi", XRC(63,134,0), XWRA_MASK | (3 << 21) | (1 << 11), COM, { BFF, U, W }, PPC_INST_MTFSFI }, +{ "mtfsfi.", XRC(63,134,1), XWRA_MASK | (3 << 21) | (1 << 11), COM, { BFF, U, W }, PPC_INST_MTFSFI }, -{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, -{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, +{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB }, PPC_INST_FNABS }, +{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB }, PPC_INST_FNABS }, -{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } }, -{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } }, -{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } }, +{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB }, PPC_INST_DTSTEXQ }, +{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM }, PPC_INST_DTSTDCQ }, +{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM }, PPC_INST_DTSTDGQ }, -{ "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, -{ "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, +{ "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC }, PPC_INST_DRINTNQ }, +{ "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC }, PPC_INST_DRINTNQ }, -{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } }, -{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } }, +{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DCTQPQ }, +{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DCTQPQ }, -{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, -{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, +{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB }, PPC_INST_FABS }, +{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB }, PPC_INST_FABS }, -{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } }, -{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } }, +{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DCTFIXQ }, +{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DCTFIXQ }, -{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, -{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } }, +{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB }, PPC_INST_DDEDPDQ }, +{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB }, PPC_INST_DDEDPDQ }, -{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } }, -{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } }, +{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DXEXQ }, +{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DXEXQ }, -{ "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } }, -{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } }, -{ "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } }, -{ "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } }, -{ "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } }, -{ "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } }, -{ "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } }, -{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } }, +{ "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB }, PPC_INST_FRIN }, +{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB }, PPC_INST_FRIN }, +{ "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB }, PPC_INST_FRIZ }, +{ "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB }, PPC_INST_FRIZ }, +{ "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB }, PPC_INST_FRIP }, +{ "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB }, PPC_INST_FRIP }, +{ "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB }, PPC_INST_FRIM }, +{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB }, PPC_INST_FRIM }, -{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, -{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DSUBQ }, +{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DSUBQ }, -{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, -{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DDIVQ }, +{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DDIVQ }, -{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, -{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, +{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT }, PPC_INST_MFFS }, +{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT }, PPC_INST_MFFS }, -{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } }, +{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB }, PPC_INST_DCMPUQ }, -{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } }, +{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB }, PPC_INST_DTSTSFQ }, -{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } }, -{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } }, +{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W }, PPC_INST_MTFSF }, +{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W }, PPC_INST_MTFSF }, -{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } }, -{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } }, +{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DRDPQ }, +{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DRDPQ }, -{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } }, -{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } }, +{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DCFFIXQ }, +{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB }, PPC_INST_DCFFIXQ }, -{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, -{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, +{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB }, PPC_INST_FCTID }, +{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB }, PPC_INST_FCTID }, -{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, -{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, +{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB }, PPC_INST_FCTIDZ }, +{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB }, PPC_INST_FCTIDZ }, -{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } }, -{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } }, +{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB }, PPC_INST_DENBCDQ }, +{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB }, PPC_INST_DENBCDQ }, -{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, -{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, +{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB }, PPC_INST_FCFID }, +{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB }, PPC_INST_FCFID }, -{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, -{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DIEXQ }, +{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB }, PPC_INST_DIEXQ }, }; +// (.+?")(.+)?(".+?)(\},) +// $1$2$3, POWERPC_INSTRUCTION_\U$2 $4 + const int powerpc_num_opcodes = - sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); +sizeof(powerpc_opcodes) / sizeof(powerpc_opcodes[0]); /* The macro table. This is only used by the assembler. */ @@ -5046,7 +5051,7 @@ const struct powerpc_macro powerpc_macros[] = { }; const int powerpc_num_macros = - sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); +sizeof(powerpc_macros) / sizeof(powerpc_macros[0]); /* This file provides several disassembler functions, all of which use @@ -5055,7 +5060,7 @@ const int powerpc_num_macros = in both big and little endian mode and also for the POWER (RS/6000) chip. */ -static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int); +static int print_insn_powerpc(bfd_vma, struct disassemble_info*, int, int); static int decode_insn_powerpc(bfd_vma memaddr, disassemble_info* info, int bigendian, int dialect, ppc_insn* oinsn); /* Determine which set of machines to disassemble for. PPC403/601 or @@ -5063,68 +5068,68 @@ static int decode_insn_powerpc(bfd_vma memaddr, disassemble_info* info, int bige by the AltiVec vector unit. */ static int -powerpc_dialect (struct disassemble_info *info) +powerpc_dialect(struct disassemble_info* info) { - int dialect = PPC_OPCODE_PPC; + int dialect = PPC_OPCODE_PPC; - if (BFD_DEFAULT_TARGET_SIZE == 64) - dialect |= PPC_OPCODE_64; + if (BFD_DEFAULT_TARGET_SIZE == 64) + dialect |= PPC_OPCODE_64; - if (info->disassembler_options - && strstr (info->disassembler_options, "booke") != NULL) - dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64; - else if ((info->mach == bfd_mach_ppc_e500) - || (info->disassembler_options - && strstr (info->disassembler_options, "e500") != NULL)) - dialect |= (PPC_OPCODE_BOOKE - | PPC_OPCODE_SPE | PPC_OPCODE_ISEL - | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK - | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK - | PPC_OPCODE_RFMCI); - else if (info->disassembler_options - && strstr (info->disassembler_options, "efs") != NULL) - dialect |= PPC_OPCODE_EFS; - else if (info->disassembler_options - && strstr (info->disassembler_options, "e300") != NULL) - dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON; - else if (info->disassembler_options - && strstr (info->disassembler_options, "440") != NULL) - dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32 - | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI; - else - dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC - | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC); + if (info->disassembler_options + && strstr(info->disassembler_options, "booke") != NULL) + dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64; + else if ((info->mach == bfd_mach_ppc_e500) + || (info->disassembler_options + && strstr(info->disassembler_options, "e500") != NULL)) + dialect |= (PPC_OPCODE_BOOKE + | PPC_OPCODE_SPE | PPC_OPCODE_ISEL + | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK + | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK + | PPC_OPCODE_RFMCI); + else if (info->disassembler_options + && strstr(info->disassembler_options, "efs") != NULL) + dialect |= PPC_OPCODE_EFS; + else if (info->disassembler_options + && strstr(info->disassembler_options, "e300") != NULL) + dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON; + else if (info->disassembler_options + && strstr(info->disassembler_options, "440") != NULL) + dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32 + | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI; + else + dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC + | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC); - if (info->disassembler_options - && strstr (info->disassembler_options, "power4") != NULL) - dialect |= PPC_OPCODE_POWER4; + if (info->disassembler_options + && strstr(info->disassembler_options, "power4") != NULL) + dialect |= PPC_OPCODE_POWER4; - if (info->disassembler_options - && strstr (info->disassembler_options, "power5") != NULL) - dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5; + if (info->disassembler_options + && strstr(info->disassembler_options, "power5") != NULL) + dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5; - if (info->disassembler_options - && strstr (info->disassembler_options, "cell") != NULL) - dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC; + if (info->disassembler_options + && strstr(info->disassembler_options, "cell") != NULL) + dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC; - if (info->disassembler_options - && strstr (info->disassembler_options, "power6") != NULL) - dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC; + if (info->disassembler_options + && strstr(info->disassembler_options, "power6") != NULL) + dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC; - if (info->disassembler_options - && strstr (info->disassembler_options, "any") != NULL) - dialect |= PPC_OPCODE_ANY; + if (info->disassembler_options + && strstr(info->disassembler_options, "any") != NULL) + dialect |= PPC_OPCODE_ANY; - if (info->disassembler_options) + if (info->disassembler_options) { - if (strstr (info->disassembler_options, "32") != NULL) - dialect &= ~PPC_OPCODE_64; - else if (strstr (info->disassembler_options, "64") != NULL) - dialect |= PPC_OPCODE_64; + if (strstr(info->disassembler_options, "32") != NULL) + dialect &= ~PPC_OPCODE_64; + else if (strstr(info->disassembler_options, "64") != NULL) + dialect |= PPC_OPCODE_64; } - info->private_data = (char *) 0 + dialect; - return dialect; + info->private_data = (char*)0 + dialect; + return dialect; } int decode_insn_ppc(bfd_vma memaddr, disassemble_info* info, ppc_insn* oinsn) @@ -5135,261 +5140,261 @@ int decode_insn_ppc(bfd_vma memaddr, disassemble_info* info, ppc_insn* oinsn) /* Qemu default */ int -print_insn_ppc (bfd_vma memaddr, struct disassemble_info *info) +print_insn_ppc(bfd_vma memaddr, struct disassemble_info* info) { - int dialect = (char *) info->private_data - (char *) 0; - return print_insn_powerpc (memaddr, info, 1, dialect); + int dialect = (char*)info->private_data - (char*)0; + return print_insn_powerpc(memaddr, info, 1, dialect); } /* Print a big endian PowerPC instruction. */ int -print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) +print_insn_big_powerpc(bfd_vma memaddr, struct disassemble_info* info) { - int dialect = (char *) info->private_data - (char *) 0; - return print_insn_powerpc (memaddr, info, 1, dialect); + int dialect = (char*)info->private_data - (char*)0; + return print_insn_powerpc(memaddr, info, 1, dialect); } /* Print a little endian PowerPC instruction. */ int -print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) +print_insn_little_powerpc(bfd_vma memaddr, struct disassemble_info* info) { - int dialect = (char *) info->private_data - (char *) 0; - return print_insn_powerpc (memaddr, info, 0, dialect); + int dialect = (char*)info->private_data - (char*)0; + return print_insn_powerpc(memaddr, info, 0, dialect); } /* Print a POWER (RS/6000) instruction. */ int -print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) +print_insn_rs6000(bfd_vma memaddr, struct disassemble_info* info) { - return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); + return print_insn_powerpc(memaddr, info, 1, PPC_OPCODE_POWER); } /* Extract the operand value from the PowerPC or POWER instruction. */ static long -operand_value_powerpc (const struct powerpc_operand *operand, - unsigned long insn, int dialect) +operand_value_powerpc(const struct powerpc_operand* operand, + unsigned long insn, int dialect) { - long value; - int invalid; - /* Extract the value from the instruction. */ - if (operand->extract) - value = (*operand->extract) (insn, dialect, &invalid); - else + long value; + int invalid; + /* Extract the value from the instruction. */ + if (operand->extract) + value = (*operand->extract) (insn, dialect, &invalid); + else { - value = (insn >> operand->shift) & operand->bitm; - if ((operand->flags & PPC_OPERAND_SIGNED) != 0) - { - /* BITM is always some number of zeros followed by some - number of ones, followed by some numer of zeros. */ - unsigned long top = operand->bitm; - /* top & -top gives the rightmost 1 bit, so this - fills in any trailing zeros. */ - top |= (top & -top) - 1; - top &= ~(top >> 1); - value = (value ^ top) - top; - } + value = (insn >> operand->shift) & operand->bitm; + if ((operand->flags & PPC_OPERAND_SIGNED) != 0) + { + /* BITM is always some number of zeros followed by some + number of ones, followed by some numer of zeros. */ + unsigned long top = operand->bitm; + /* top & -top gives the rightmost 1 bit, so this + fills in any trailing zeros. */ + top |= (top & -top) - 1; + top &= ~(top >> 1); + value = (value ^ top) - top; + } } - return value; + return value; } /* Determine whether the optional operand(s) should be printed. */ static int -skip_optional_operands (const unsigned char *opindex, - unsigned long insn, int dialect) +skip_optional_operands(const unsigned char* opindex, + unsigned long insn, int dialect) { - const struct powerpc_operand *operand; + const struct powerpc_operand* operand; - for (; *opindex != 0; opindex++) + for (; *opindex != 0; opindex++) { - operand = &powerpc_operands[*opindex]; - if ((operand->flags & PPC_OPERAND_NEXT) != 0 - || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 - && operand_value_powerpc (operand, insn, dialect) != 0)) - return 0; + operand = &powerpc_operands[*opindex]; + if ((operand->flags & PPC_OPERAND_NEXT) != 0 + || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 + && operand_value_powerpc(operand, insn, dialect) != 0)) + return 0; } - return 1; + return 1; } /* Print a PowerPC or POWER instruction. */ static int -print_insn_powerpc (bfd_vma memaddr, - struct disassemble_info *info, - int bigendian, - int dialect) +print_insn_powerpc(bfd_vma memaddr, + struct disassemble_info* info, + int bigendian, + int dialect) { - bfd_byte buffer[4]; - int status; - unsigned long insn; - const struct powerpc_opcode *opcode; - const struct powerpc_opcode *opcode_end; - unsigned long op; + bfd_byte buffer[4]; + int status; + unsigned long insn; + const struct powerpc_opcode* opcode; + const struct powerpc_opcode* opcode_end; + unsigned long op; - if (dialect == 0) - dialect = powerpc_dialect (info); + if (dialect == 0) + dialect = powerpc_dialect(info); - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) { - (*info->memory_error_func) (status, memaddr, info); - return -1; + (*info->memory_error_func) (status, memaddr, info); + return -1; } - if (bigendian) - insn = bfd_getb32 (buffer); - else - insn = bfd_getl32 (buffer); + if (bigendian) + insn = bfd_getb32(buffer); + else + insn = bfd_getl32(buffer); - /* Get the major opcode of the instruction. */ - op = PPC_OP (insn); + /* Get the major opcode of the instruction. */ + op = PPC_OP(insn); - /* Find the first match in the opcode table. We could speed this up - a bit by doing a binary search on the major opcode. */ - opcode_end = powerpc_opcodes + powerpc_num_opcodes; - again: - for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++) + /* Find the first match in the opcode table. We could speed this up + a bit by doing a binary search on the major opcode. */ + opcode_end = powerpc_opcodes + powerpc_num_opcodes; +again: + for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++) { - unsigned long table_op; - const unsigned char *opindex; - const struct powerpc_operand *operand; - int invalid; - int need_comma; - int need_paren; - int skip_optional; + unsigned long table_op; + const unsigned char* opindex; + const struct powerpc_operand* operand; + int invalid; + int need_comma; + int need_paren; + int skip_optional; - table_op = PPC_OP (opcode->opcode); - if (op < table_op) - break; - if (op > table_op) - continue; + table_op = PPC_OP(opcode->opcode); + if (op < table_op) + break; + if (op > table_op) + continue; - if ((insn & opcode->mask) != opcode->opcode - || (opcode->flags & dialect) == 0) - continue; + if ((insn & opcode->mask) != opcode->opcode + || (opcode->flags & dialect) == 0) + continue; - /* Make two passes over the operands. First see if any of them - have extraction functions, and, if they do, make sure the - instruction is valid. */ - invalid = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - operand = powerpc_operands + *opindex; - if (operand->extract) - (*operand->extract) (insn, dialect, &invalid); - } - if (invalid) - continue; - - /* The instruction is valid. */ - if (opcode->operands[0] != 0) - (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); - else - (*info->fprintf_func) (info->stream, "%s", opcode->name); - - /* Now extract and print the operands. */ - need_comma = 0; - need_paren = 0; - skip_optional = -1; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - long value; - - operand = powerpc_operands + *opindex; - - /* Operands that are marked FAKE are simply ignored. We - already made sure that the extract function considered - the instruction to be valid. */ - if ((operand->flags & PPC_OPERAND_FAKE) != 0) - continue; - - /* If all of the optional operands have the value zero, - then don't print any of them. */ - if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) + /* Make two passes over the operands. First see if any of them + have extraction functions, and, if they do, make sure the + instruction is valid. */ + invalid = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) { - if (skip_optional < 0) - skip_optional = skip_optional_operands (opindex, insn, - dialect); - if (skip_optional) - continue; + operand = powerpc_operands + *opindex; + if (operand->extract) + (*operand->extract) (insn, dialect, &invalid); + } + if (invalid) + continue; + + /* The instruction is valid. */ + if (opcode->operands[0] != 0) + (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); + else + (*info->fprintf_func) (info->stream, "%s", opcode->name); + + /* Now extract and print the operands. */ + need_comma = 0; + need_paren = 0; + skip_optional = -1; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + long value; + + operand = powerpc_operands + *opindex; + + /* Operands that are marked FAKE are simply ignored. We + already made sure that the extract function considered + the instruction to be valid. */ + if ((operand->flags & PPC_OPERAND_FAKE) != 0) + continue; + + /* If all of the optional operands have the value zero, + then don't print any of them. */ + if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) + { + if (skip_optional < 0) + skip_optional = skip_optional_operands(opindex, insn, + dialect); + if (skip_optional) + continue; + } + + value = operand_value_powerpc(operand, insn, dialect); + + if (need_comma) + { + (*info->fprintf_func) (info->stream, ","); + need_comma = 0; + } + + /* Print the operand as directed by the flags. */ + if ((operand->flags & PPC_OPERAND_GPR) != 0 + || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) + (*info->fprintf_func) (info->stream, "r%ld", value); + else if ((operand->flags & PPC_OPERAND_FPR) != 0) + (*info->fprintf_func) (info->stream, "f%ld", value); + else if ((operand->flags & PPC_OPERAND_VR) != 0) + (*info->fprintf_func) (info->stream, "v%ld", value); + else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) + (*info->print_address_func) (memaddr + value, info); + else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) + (*info->print_address_func) ((bfd_vma)value & 0xffffffff, info); + else if ((operand->flags & PPC_OPERAND_CR) == 0 + || (dialect & PPC_OPCODE_PPC) == 0) + (*info->fprintf_func) (info->stream, "%ld", value); + else + { + if (operand->bitm == 7) + (*info->fprintf_func) (info->stream, "cr%ld", value); + else + { + static const char* cbnames[4] = { "lt", "gt", "eq", "so" }; + int cr; + int cc; + + cr = value >> 2; + if (cr != 0) + (*info->fprintf_func) (info->stream, "4*cr%d+", cr); + cc = value & 3; + (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); + } + } + + if (need_paren) + { + (*info->fprintf_func) (info->stream, ")"); + need_paren = 0; + } + + if ((operand->flags & PPC_OPERAND_PARENS) == 0) + need_comma = 1; + else + { + (*info->fprintf_func) (info->stream, "("); + need_paren = 1; + } } - value = operand_value_powerpc (operand, insn, dialect); - - if (need_comma) - { - (*info->fprintf_func) (info->stream, ","); - need_comma = 0; - } - - /* Print the operand as directed by the flags. */ - if ((operand->flags & PPC_OPERAND_GPR) != 0 - || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) - (*info->fprintf_func) (info->stream, "r%ld", value); - else if ((operand->flags & PPC_OPERAND_FPR) != 0) - (*info->fprintf_func) (info->stream, "f%ld", value); - else if ((operand->flags & PPC_OPERAND_VR) != 0) - (*info->fprintf_func) (info->stream, "v%ld", value); - else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) - (*info->print_address_func) (memaddr + value, info); - else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); - else if ((operand->flags & PPC_OPERAND_CR) == 0 - || (dialect & PPC_OPCODE_PPC) == 0) - (*info->fprintf_func) (info->stream, "%ld", value); - else - { - if (operand->bitm == 7) - (*info->fprintf_func) (info->stream, "cr%ld", value); - else - { - static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; - int cr; - int cc; - - cr = value >> 2; - if (cr != 0) - (*info->fprintf_func) (info->stream, "4*cr%d+", cr); - cc = value & 3; - (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); - } - } - - if (need_paren) - { - (*info->fprintf_func) (info->stream, ")"); - need_paren = 0; - } - - if ((operand->flags & PPC_OPERAND_PARENS) == 0) - need_comma = 1; - else - { - (*info->fprintf_func) (info->stream, "("); - need_paren = 1; - } + /* We have found and printed an instruction; return. */ + return 4; } - /* We have found and printed an instruction; return. */ - return 4; - } - - if ((dialect & PPC_OPCODE_ANY) != 0) + if ((dialect & PPC_OPCODE_ANY) != 0) { - dialect = ~PPC_OPCODE_ANY; - goto again; + dialect = ~PPC_OPCODE_ANY; + goto again; } - /* We could not find a match. */ - (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); + /* We could not find a match. */ + (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); - return 4; + return 4; } static int decode_insn_powerpc(bfd_vma memaddr, disassemble_info* info, int bigendian, int dialect, ppc_insn* oinsn) diff --git a/thirdparty/disasm/ppc.h b/thirdparty/disasm/ppc.h new file mode 100644 index 0000000..dc96eef --- /dev/null +++ b/thirdparty/disasm/ppc.h @@ -0,0 +1,1771 @@ +#pragma once + +#define PPC_INST_ATTN 0 +#define PPC_INST_TDLGTI 1 +#define PPC_INST_TDLLTI 2 +#define PPC_INST_TDEQI 3 +#define PPC_INST_TDLGEI 4 +#define PPC_INST_TDLNLI 5 +#define PPC_INST_TDLLEI 6 +#define PPC_INST_TDLNGI 7 +#define PPC_INST_TDGTI 8 +#define PPC_INST_TDGEI 9 +#define PPC_INST_TDNLI 10 +#define PPC_INST_TDLTI 11 +#define PPC_INST_TDLEI 12 +#define PPC_INST_TDNGI 13 +#define PPC_INST_TDNEI 14 +#define PPC_INST_TDI 15 +#define PPC_INST_TWLGTI 16 +#define PPC_INST_TLGTI 17 +#define PPC_INST_TWLLTI 18 +#define PPC_INST_TLLTI 19 +#define PPC_INST_TWEQI 20 +#define PPC_INST_TEQI 21 +#define PPC_INST_TWLGEI 22 +#define PPC_INST_TLGEI 23 +#define PPC_INST_TWLNLI 24 +#define PPC_INST_TLNLI 25 +#define PPC_INST_TWLLEI 26 +#define PPC_INST_TLLEI 27 +#define PPC_INST_TWLNGI 28 +#define PPC_INST_TLNGI 29 +#define PPC_INST_TWGTI 30 +#define PPC_INST_TGTI 31 +#define PPC_INST_TWGEI 32 +#define PPC_INST_TGEI 33 +#define PPC_INST_TWNLI 34 +#define PPC_INST_TNLI 35 +#define PPC_INST_TWLTI 36 +#define PPC_INST_TLTI 37 +#define PPC_INST_TWLEI 38 +#define PPC_INST_TLEI 39 +#define PPC_INST_TWNGI 40 +#define PPC_INST_TNGI 41 +#define PPC_INST_TWNEI 42 +#define PPC_INST_TNEI 43 +#define PPC_INST_TWI 44 +#define PPC_INST_TI 45 +#define PPC_INST_MACCHW 46 +#define PPC_INST_MACCHWO 47 +#define PPC_INST_MACCHWS 48 +#define PPC_INST_MACCHWSO 49 +#define PPC_INST_MACCHWSU 50 +#define PPC_INST_MACCHWSUO 51 +#define PPC_INST_MACCHWU 52 +#define PPC_INST_MACCHWUO 53 +#define PPC_INST_MACHHW 54 +#define PPC_INST_MACHHWO 55 +#define PPC_INST_MACHHWS 56 +#define PPC_INST_MACHHWSO 57 +#define PPC_INST_MACHHWSU 58 +#define PPC_INST_MACHHWSUO 59 +#define PPC_INST_MACHHWU 60 +#define PPC_INST_MACHHWUO 61 +#define PPC_INST_MACLHW 62 +#define PPC_INST_MACLHWO 63 +#define PPC_INST_MACLHWS 64 +#define PPC_INST_MACLHWSO 65 +#define PPC_INST_MACLHWSU 66 +#define PPC_INST_MACLHWSUO 67 +#define PPC_INST_MACLHWU 68 +#define PPC_INST_MACLHWUO 69 +#define PPC_INST_MULCHW 70 +#define PPC_INST_MULCHWU 71 +#define PPC_INST_MULHHW 72 +#define PPC_INST_MULHHWU 73 +#define PPC_INST_MULLHW 74 +#define PPC_INST_MULLHWU 75 +#define PPC_INST_NMACCHW 76 +#define PPC_INST_NMACCHWO 77 +#define PPC_INST_NMACCHWS 78 +#define PPC_INST_NMACCHWSO 79 +#define PPC_INST_NMACHHW 80 +#define PPC_INST_NMACHHWO 81 +#define PPC_INST_NMACHHWS 82 +#define PPC_INST_NMACHHWSO 83 +#define PPC_INST_NMACLHW 84 +#define PPC_INST_NMACLHWO 85 +#define PPC_INST_NMACLHWS 86 +#define PPC_INST_NMACLHWSO 87 +#define PPC_INST_MFVSCR 88 +#define PPC_INST_MTVSCR 89 +#define PPC_INST_EFSCFD 90 +#define PPC_INST_EFDABS 91 +#define PPC_INST_EFDNABS 92 +#define PPC_INST_EFDNEG 93 +#define PPC_INST_EFDADD 94 +#define PPC_INST_EFDSUB 95 +#define PPC_INST_EFDMUL 96 +#define PPC_INST_EFDDIV 97 +#define PPC_INST_EFDCMPGT 98 +#define PPC_INST_EFDCMPLT 99 +#define PPC_INST_EFDCMPEQ 100 +#define PPC_INST_EFDTSTGT 101 +#define PPC_INST_EFDTSTLT 102 +#define PPC_INST_EFDTSTEQ 103 +#define PPC_INST_EFDCFSI 104 +#define PPC_INST_EFDCFSID 105 +#define PPC_INST_EFDCFUI 106 +#define PPC_INST_EFDCFUID 107 +#define PPC_INST_EFDCFSF 108 +#define PPC_INST_EFDCFUF 109 +#define PPC_INST_EFDCTSI 110 +#define PPC_INST_EFDCTSIDZ 111 +#define PPC_INST_EFDCTSIZ 112 +#define PPC_INST_EFDCTUI 113 +#define PPC_INST_EFDCTUIDZ 114 +#define PPC_INST_EFDCTUIZ 115 +#define PPC_INST_EFDCTSF 116 +#define PPC_INST_EFDCTUF 117 +#define PPC_INST_EFDCFS 118 +#define PPC_INST_VADDCUW 119 +#define PPC_INST_VADDFP 120 +#define PPC_INST_VADDSBS 121 +#define PPC_INST_VADDSHS 122 +#define PPC_INST_VADDSWS 123 +#define PPC_INST_VADDUBM 124 +#define PPC_INST_VADDUBS 125 +#define PPC_INST_VADDUHM 126 +#define PPC_INST_VADDUHS 127 +#define PPC_INST_VADDUWM 128 +#define PPC_INST_VADDUWS 129 +#define PPC_INST_VAND 130 +#define PPC_INST_VANDC 131 +#define PPC_INST_VAVGSB 132 +#define PPC_INST_VAVGSH 133 +#define PPC_INST_VAVGSW 134 +#define PPC_INST_VAVGUB 135 +#define PPC_INST_VAVGUH 136 +#define PPC_INST_VAVGUW 137 +#define PPC_INST_VCFSX 138 +#define PPC_INST_VCFUX 139 +#define PPC_INST_VCMPBFP 140 +#define PPC_INST_VCMPEQFP 141 +#define PPC_INST_VCMPEQUB 142 +#define PPC_INST_VCMPEQUH 143 +#define PPC_INST_VCMPEQUW 144 +#define PPC_INST_VCMPGEFP 145 +#define PPC_INST_VCMPGTFP 146 +#define PPC_INST_VCMPGTSB 147 +#define PPC_INST_VCMPGTSH 148 +#define PPC_INST_VCMPGTSW 149 +#define PPC_INST_VCMPGTUB 150 +#define PPC_INST_VCMPGTUH 151 +#define PPC_INST_VCMPGTUW 152 +#define PPC_INST_VCTSXS 153 +#define PPC_INST_VCTUXS 154 +#define PPC_INST_VEXPTEFP 155 +#define PPC_INST_VLOGEFP 156 +#define PPC_INST_VMADDFP 157 +#define PPC_INST_VMAXFP 158 +#define PPC_INST_VMAXSB 159 +#define PPC_INST_VMAXSH 160 +#define PPC_INST_VMAXSW 161 +#define PPC_INST_VMAXUB 162 +#define PPC_INST_VMAXUH 163 +#define PPC_INST_VMAXUW 164 +#define PPC_INST_VMHADDSHS 165 +#define PPC_INST_VMHRADDSHS 166 +#define PPC_INST_VMINFP 167 +#define PPC_INST_VMINSB 168 +#define PPC_INST_VMINSH 169 +#define PPC_INST_VMINSW 170 +#define PPC_INST_VMINUB 171 +#define PPC_INST_VMINUH 172 +#define PPC_INST_VMINUW 173 +#define PPC_INST_VMLADDUHM 174 +#define PPC_INST_VMRGHB 175 +#define PPC_INST_VMRGHH 176 +#define PPC_INST_VMRGHW 177 +#define PPC_INST_VMRGLB 178 +#define PPC_INST_VMRGLH 179 +#define PPC_INST_VMRGLW 180 +#define PPC_INST_VMSUMMBM 181 +#define PPC_INST_VMSUMSHM 182 +#define PPC_INST_VMSUMSHS 183 +#define PPC_INST_VMSUMUBM 184 +#define PPC_INST_VMSUMUHM 185 +#define PPC_INST_VMSUMUHS 186 +#define PPC_INST_VMULESB 187 +#define PPC_INST_VMULESH 188 +#define PPC_INST_VMULEUB 189 +#define PPC_INST_VMULEUH 190 +#define PPC_INST_VMULOSB 191 +#define PPC_INST_VMULOSH 192 +#define PPC_INST_VMULOUB 193 +#define PPC_INST_VMULOUH 194 +#define PPC_INST_VNMSUBFP 195 +#define PPC_INST_VNOR 196 +#define PPC_INST_VOR 197 +#define PPC_INST_VPERM 198 +#define PPC_INST_VPKPX 199 +#define PPC_INST_VPKSHSS 200 +#define PPC_INST_VPKSHUS 201 +#define PPC_INST_VPKSWSS 202 +#define PPC_INST_VPKSWUS 203 +#define PPC_INST_VPKUHUM 204 +#define PPC_INST_VPKUHUS 205 +#define PPC_INST_VPKUWUM 206 +#define PPC_INST_VPKUWUS 207 +#define PPC_INST_VREFP 208 +#define PPC_INST_VRFIM 209 +#define PPC_INST_VRFIN 210 +#define PPC_INST_VRFIP 211 +#define PPC_INST_VRFIZ 212 +#define PPC_INST_VRLB 213 +#define PPC_INST_VRLH 214 +#define PPC_INST_VRLW 215 +#define PPC_INST_VRSQRTEFP 216 +#define PPC_INST_VSEL 217 +#define PPC_INST_VSL 218 +#define PPC_INST_VSLB 219 +#define PPC_INST_VSLDOI 220 +#define PPC_INST_VSLH 221 +#define PPC_INST_VSLO 222 +#define PPC_INST_VSLW 223 +#define PPC_INST_VSPLTB 224 +#define PPC_INST_VSPLTH 225 +#define PPC_INST_VSPLTISB 226 +#define PPC_INST_VSPLTISH 227 +#define PPC_INST_VSPLTISW 228 +#define PPC_INST_VSPLTW 229 +#define PPC_INST_VSR 230 +#define PPC_INST_VSRAB 231 +#define PPC_INST_VSRAH 232 +#define PPC_INST_VSRAW 233 +#define PPC_INST_VSRB 234 +#define PPC_INST_VSRH 235 +#define PPC_INST_VSRO 236 +#define PPC_INST_VSRW 237 +#define PPC_INST_VSUBCUW 238 +#define PPC_INST_VSUBFP 239 +#define PPC_INST_VSUBSBS 240 +#define PPC_INST_VSUBSHS 241 +#define PPC_INST_VSUBSWS 242 +#define PPC_INST_VSUBUBM 243 +#define PPC_INST_VSUBUBS 244 +#define PPC_INST_VSUBUHM 245 +#define PPC_INST_VSUBUHS 246 +#define PPC_INST_VSUBUWM 247 +#define PPC_INST_VSUBUWS 248 +#define PPC_INST_VSUMSWS 249 +#define PPC_INST_VSUM2SWS 250 +#define PPC_INST_VSUM4SBS 251 +#define PPC_INST_VSUM4SHS 252 +#define PPC_INST_VSUM4UBS 253 +#define PPC_INST_VUPKHPX 254 +#define PPC_INST_VUPKHSB 255 +#define PPC_INST_VUPKHSH 256 +#define PPC_INST_VUPKLPX 257 +#define PPC_INST_VUPKLSB 258 +#define PPC_INST_VUPKLSH 259 +#define PPC_INST_VXOR 260 +#define PPC_INST_EVADDW 261 +#define PPC_INST_EVADDIW 262 +#define PPC_INST_EVSUBFW 263 +#define PPC_INST_EVSUBW 264 +#define PPC_INST_EVSUBIFW 265 +#define PPC_INST_EVSUBIW 266 +#define PPC_INST_EVABS 267 +#define PPC_INST_EVNEG 268 +#define PPC_INST_EVEXTSB 269 +#define PPC_INST_EVEXTSH 270 +#define PPC_INST_EVRNDW 271 +#define PPC_INST_EVCNTLZW 272 +#define PPC_INST_EVCNTLSW 273 +#define PPC_INST_BRINC 274 +#define PPC_INST_EVAND 275 +#define PPC_INST_EVANDC 276 +#define PPC_INST_EVMR 277 +#define PPC_INST_EVOR 278 +#define PPC_INST_EVORC 279 +#define PPC_INST_EVXOR 280 +#define PPC_INST_EVEQV 281 +#define PPC_INST_EVNAND 282 +#define PPC_INST_EVNOT 283 +#define PPC_INST_EVNOR 284 +#define PPC_INST_EVRLW 285 +#define PPC_INST_EVRLWI 286 +#define PPC_INST_EVSLW 287 +#define PPC_INST_EVSLWI 288 +#define PPC_INST_EVSRWS 289 +#define PPC_INST_EVSRWU 290 +#define PPC_INST_EVSRWIS 291 +#define PPC_INST_EVSRWIU 292 +#define PPC_INST_EVSPLATI 293 +#define PPC_INST_EVSPLATFI 294 +#define PPC_INST_EVMERGEHI 295 +#define PPC_INST_EVMERGELO 296 +#define PPC_INST_EVMERGEHILO 297 +#define PPC_INST_EVMERGELOHI 298 +#define PPC_INST_EVCMPGTS 299 +#define PPC_INST_EVCMPGTU 300 +#define PPC_INST_EVCMPLTS 301 +#define PPC_INST_EVCMPLTU 302 +#define PPC_INST_EVCMPEQ 303 +#define PPC_INST_EVSEL 304 +#define PPC_INST_EVLDD 305 +#define PPC_INST_EVLDDX 306 +#define PPC_INST_EVLDW 307 +#define PPC_INST_EVLDWX 308 +#define PPC_INST_EVLDH 309 +#define PPC_INST_EVLDHX 310 +#define PPC_INST_EVLWHE 311 +#define PPC_INST_EVLWHEX 312 +#define PPC_INST_EVLWHOU 313 +#define PPC_INST_EVLWHOUX 314 +#define PPC_INST_EVLWHOS 315 +#define PPC_INST_EVLWHOSX 316 +#define PPC_INST_EVLWWSPLAT 317 +#define PPC_INST_EVLWWSPLATX 318 +#define PPC_INST_EVLWHSPLAT 319 +#define PPC_INST_EVLWHSPLATX 320 +#define PPC_INST_EVLHHESPLAT 321 +#define PPC_INST_EVLHHESPLATX 322 +#define PPC_INST_EVLHHOUSPLAT 323 +#define PPC_INST_EVLHHOUSPLATX 324 +#define PPC_INST_EVLHHOSSPLAT 325 +#define PPC_INST_EVLHHOSSPLATX 326 +#define PPC_INST_EVSTDD 327 +#define PPC_INST_EVSTDDX 328 +#define PPC_INST_EVSTDW 329 +#define PPC_INST_EVSTDWX 330 +#define PPC_INST_EVSTDH 331 +#define PPC_INST_EVSTDHX 332 +#define PPC_INST_EVSTWWE 333 +#define PPC_INST_EVSTWWEX 334 +#define PPC_INST_EVSTWWO 335 +#define PPC_INST_EVSTWWOX 336 +#define PPC_INST_EVSTWHE 337 +#define PPC_INST_EVSTWHEX 338 +#define PPC_INST_EVSTWHO 339 +#define PPC_INST_EVSTWHOX 340 +#define PPC_INST_EVFSABS 341 +#define PPC_INST_EVFSNABS 342 +#define PPC_INST_EVFSNEG 343 +#define PPC_INST_EVFSADD 344 +#define PPC_INST_EVFSSUB 345 +#define PPC_INST_EVFSMUL 346 +#define PPC_INST_EVFSDIV 347 +#define PPC_INST_EVFSCMPGT 348 +#define PPC_INST_EVFSCMPLT 349 +#define PPC_INST_EVFSCMPEQ 350 +#define PPC_INST_EVFSTSTGT 351 +#define PPC_INST_EVFSTSTLT 352 +#define PPC_INST_EVFSTSTEQ 353 +#define PPC_INST_EVFSCFUI 354 +#define PPC_INST_EVFSCTUIZ 355 +#define PPC_INST_EVFSCFSI 356 +#define PPC_INST_EVFSCFUF 357 +#define PPC_INST_EVFSCFSF 358 +#define PPC_INST_EVFSCTUI 359 +#define PPC_INST_EVFSCTSI 360 +#define PPC_INST_EVFSCTSIZ 361 +#define PPC_INST_EVFSCTUF 362 +#define PPC_INST_EVFSCTSF 363 +#define PPC_INST_EFSABS 364 +#define PPC_INST_EFSNABS 365 +#define PPC_INST_EFSNEG 366 +#define PPC_INST_EFSADD 367 +#define PPC_INST_EFSSUB 368 +#define PPC_INST_EFSMUL 369 +#define PPC_INST_EFSDIV 370 +#define PPC_INST_EFSCMPGT 371 +#define PPC_INST_EFSCMPLT 372 +#define PPC_INST_EFSCMPEQ 373 +#define PPC_INST_EFSTSTGT 374 +#define PPC_INST_EFSTSTLT 375 +#define PPC_INST_EFSTSTEQ 376 +#define PPC_INST_EFSCFUI 377 +#define PPC_INST_EFSCTUIZ 378 +#define PPC_INST_EFSCFSI 379 +#define PPC_INST_EFSCFUF 380 +#define PPC_INST_EFSCFSF 381 +#define PPC_INST_EFSCTUI 382 +#define PPC_INST_EFSCTSI 383 +#define PPC_INST_EFSCTSIZ 384 +#define PPC_INST_EFSCTUF 385 +#define PPC_INST_EFSCTSF 386 +#define PPC_INST_EVMHOSSF 387 +#define PPC_INST_EVMHOSSFA 388 +#define PPC_INST_EVMHOSMF 389 +#define PPC_INST_EVMHOSMFA 390 +#define PPC_INST_EVMHOSMI 391 +#define PPC_INST_EVMHOSMIA 392 +#define PPC_INST_EVMHOUMI 393 +#define PPC_INST_EVMHOUMIA 394 +#define PPC_INST_EVMHESSF 395 +#define PPC_INST_EVMHESSFA 396 +#define PPC_INST_EVMHESMF 397 +#define PPC_INST_EVMHESMFA 398 +#define PPC_INST_EVMHESMI 399 +#define PPC_INST_EVMHESMIA 400 +#define PPC_INST_EVMHEUMI 401 +#define PPC_INST_EVMHEUMIA 402 +#define PPC_INST_EVMHOSSFAAW 403 +#define PPC_INST_EVMHOSSIAAW 404 +#define PPC_INST_EVMHOSMFAAW 405 +#define PPC_INST_EVMHOSMIAAW 406 +#define PPC_INST_EVMHOUSIAAW 407 +#define PPC_INST_EVMHOUMIAAW 408 +#define PPC_INST_EVMHESSFAAW 409 +#define PPC_INST_EVMHESSIAAW 410 +#define PPC_INST_EVMHESMFAAW 411 +#define PPC_INST_EVMHESMIAAW 412 +#define PPC_INST_EVMHEUSIAAW 413 +#define PPC_INST_EVMHEUMIAAW 414 +#define PPC_INST_EVMHOSSFANW 415 +#define PPC_INST_EVMHOSSIANW 416 +#define PPC_INST_EVMHOSMFANW 417 +#define PPC_INST_EVMHOSMIANW 418 +#define PPC_INST_EVMHOUSIANW 419 +#define PPC_INST_EVMHOUMIANW 420 +#define PPC_INST_EVMHESSFANW 421 +#define PPC_INST_EVMHESSIANW 422 +#define PPC_INST_EVMHESMFANW 423 +#define PPC_INST_EVMHESMIANW 424 +#define PPC_INST_EVMHEUSIANW 425 +#define PPC_INST_EVMHEUMIANW 426 +#define PPC_INST_EVMHOGSMFAA 427 +#define PPC_INST_EVMHOGSMIAA 428 +#define PPC_INST_EVMHOGUMIAA 429 +#define PPC_INST_EVMHEGSMFAA 430 +#define PPC_INST_EVMHEGSMIAA 431 +#define PPC_INST_EVMHEGUMIAA 432 +#define PPC_INST_EVMHOGSMFAN 433 +#define PPC_INST_EVMHOGSMIAN 434 +#define PPC_INST_EVMHOGUMIAN 435 +#define PPC_INST_EVMHEGSMFAN 436 +#define PPC_INST_EVMHEGSMIAN 437 +#define PPC_INST_EVMHEGUMIAN 438 +#define PPC_INST_EVMWHSSF 439 +#define PPC_INST_EVMWHSSFA 440 +#define PPC_INST_EVMWHSMF 441 +#define PPC_INST_EVMWHSMFA 442 +#define PPC_INST_EVMWHSMI 443 +#define PPC_INST_EVMWHSMIA 444 +#define PPC_INST_EVMWHUMI 445 +#define PPC_INST_EVMWHUMIA 446 +#define PPC_INST_EVMWLUMI 447 +#define PPC_INST_EVMWLUMIA 448 +#define PPC_INST_EVMWLSSIAAW 449 +#define PPC_INST_EVMWLSMIAAW 450 +#define PPC_INST_EVMWLUSIAAW 451 +#define PPC_INST_EVMWLUMIAAW 452 +#define PPC_INST_EVMWLSSIANW 453 +#define PPC_INST_EVMWLSMIANW 454 +#define PPC_INST_EVMWLUSIANW 455 +#define PPC_INST_EVMWLUMIANW 456 +#define PPC_INST_EVMWSSF 457 +#define PPC_INST_EVMWSSFA 458 +#define PPC_INST_EVMWSMF 459 +#define PPC_INST_EVMWSMFA 460 +#define PPC_INST_EVMWSMI 461 +#define PPC_INST_EVMWSMIA 462 +#define PPC_INST_EVMWUMI 463 +#define PPC_INST_EVMWUMIA 464 +#define PPC_INST_EVMWSSFAA 465 +#define PPC_INST_EVMWSMFAA 466 +#define PPC_INST_EVMWSMIAA 467 +#define PPC_INST_EVMWUMIAA 468 +#define PPC_INST_EVMWSSFAN 469 +#define PPC_INST_EVMWSMFAN 470 +#define PPC_INST_EVMWSMIAN 471 +#define PPC_INST_EVMWUMIAN 472 +#define PPC_INST_EVADDSSIAAW 473 +#define PPC_INST_EVADDSMIAAW 474 +#define PPC_INST_EVADDUSIAAW 475 +#define PPC_INST_EVADDUMIAAW 476 +#define PPC_INST_EVSUBFSSIAAW 477 +#define PPC_INST_EVSUBFSMIAAW 478 +#define PPC_INST_EVSUBFUSIAAW 479 +#define PPC_INST_EVSUBFUMIAAW 480 +#define PPC_INST_EVMRA 481 +#define PPC_INST_EVDIVWS 482 +#define PPC_INST_EVDIVWU 483 +#define PPC_INST_MULLI 484 +#define PPC_INST_MULI 485 +#define PPC_INST_SUBFIC 486 +#define PPC_INST_SFI 487 +#define PPC_INST_DOZI 488 +#define PPC_INST_BCE 489 +#define PPC_INST_BCEL 490 +#define PPC_INST_BCEA 491 +#define PPC_INST_BCELA 492 +#define PPC_INST_CMPLWI 493 +#define PPC_INST_CMPLDI 494 +#define PPC_INST_CMPLI 495 +#define PPC_INST_CMPWI 496 +#define PPC_INST_CMPDI 497 +#define PPC_INST_CMPI 498 +#define PPC_INST_ADDIC 499 +#define PPC_INST_AI 500 +#define PPC_INST_SUBIC 501 +#define PPC_INST_LI 502 +#define PPC_INST_LIL 503 +#define PPC_INST_ADDI 504 +#define PPC_INST_CAL 505 +#define PPC_INST_SUBI 506 +#define PPC_INST_LA 507 +#define PPC_INST_LIS 508 +#define PPC_INST_LIU 509 +#define PPC_INST_ADDIS 510 +#define PPC_INST_CAU 511 +#define PPC_INST_SUBIS 512 +#define PPC_INST_BDNZ 513 +#define PPC_INST_BDN 514 +#define PPC_INST_BDNZL 515 +#define PPC_INST_BDNL 516 +#define PPC_INST_BDNZA 517 +#define PPC_INST_BDNA 518 +#define PPC_INST_BDNZLA 519 +#define PPC_INST_BDNLA 520 +#define PPC_INST_BDZ 521 +#define PPC_INST_BDZL 522 +#define PPC_INST_BDZA 523 +#define PPC_INST_BDZLA 524 +#define PPC_INST_BLT 525 +#define PPC_INST_BLTL 526 +#define PPC_INST_BLTA 527 +#define PPC_INST_BLTLA 528 +#define PPC_INST_BGT 529 +#define PPC_INST_BGTL 530 +#define PPC_INST_BGTA 531 +#define PPC_INST_BGTLA 532 +#define PPC_INST_BEQ 533 +#define PPC_INST_BEQL 534 +#define PPC_INST_BEQA 535 +#define PPC_INST_BEQLA 536 +#define PPC_INST_BSO 537 +#define PPC_INST_BSOL 538 +#define PPC_INST_BSOA 539 +#define PPC_INST_BSOLA 540 +#define PPC_INST_BUN 541 +#define PPC_INST_BUNL 542 +#define PPC_INST_BUNA 543 +#define PPC_INST_BUNLA 544 +#define PPC_INST_BGE 545 +#define PPC_INST_BGEL 546 +#define PPC_INST_BGEA 547 +#define PPC_INST_BGELA 548 +#define PPC_INST_BNL 549 +#define PPC_INST_BNLL 550 +#define PPC_INST_BNLA 551 +#define PPC_INST_BNLLA 552 +#define PPC_INST_BLE 553 +#define PPC_INST_BLEL 554 +#define PPC_INST_BLEA 555 +#define PPC_INST_BLELA 556 +#define PPC_INST_BNG 557 +#define PPC_INST_BNGL 558 +#define PPC_INST_BNGA 559 +#define PPC_INST_BNGLA 560 +#define PPC_INST_BNE 561 +#define PPC_INST_BNEL 562 +#define PPC_INST_BNEA 563 +#define PPC_INST_BNELA 564 +#define PPC_INST_BNS 565 +#define PPC_INST_BNSL 566 +#define PPC_INST_BNSA 567 +#define PPC_INST_BNSLA 568 +#define PPC_INST_BNU 569 +#define PPC_INST_BNUL 570 +#define PPC_INST_BNUA 571 +#define PPC_INST_BNULA 572 +#define PPC_INST_BDNZT 573 +#define PPC_INST_BDNZTL 574 +#define PPC_INST_BDNZTA 575 +#define PPC_INST_BDNZTLA 576 +#define PPC_INST_BDNZF 577 +#define PPC_INST_BDNZFL 578 +#define PPC_INST_BDNZFA 579 +#define PPC_INST_BDNZFLA 580 +#define PPC_INST_BT 581 +#define PPC_INST_BBT 582 +#define PPC_INST_BTL 583 +#define PPC_INST_BBTL 584 +#define PPC_INST_BTA 585 +#define PPC_INST_BBTA 586 +#define PPC_INST_BTLA 587 +#define PPC_INST_BBTLA 588 +#define PPC_INST_BF 589 +#define PPC_INST_BBF 590 +#define PPC_INST_BFL 591 +#define PPC_INST_BBFL 592 +#define PPC_INST_BFA 593 +#define PPC_INST_BBFA 594 +#define PPC_INST_BFLA 595 +#define PPC_INST_BBFLA 596 +#define PPC_INST_BDZT 597 +#define PPC_INST_BDZTL 598 +#define PPC_INST_BDZTA 599 +#define PPC_INST_BDZTLA 600 +#define PPC_INST_BDZF 601 +#define PPC_INST_BDZFL 602 +#define PPC_INST_BDZFA 603 +#define PPC_INST_BDZFLA 604 +#define PPC_INST_BC 605 +#define PPC_INST_BCL 606 +#define PPC_INST_BCA 607 +#define PPC_INST_BCLA 608 +#define PPC_INST_SC 609 +#define PPC_INST_SVC 610 +#define PPC_INST_SVCL 611 +#define PPC_INST_SVCA 612 +#define PPC_INST_SVCLA 613 +#define PPC_INST_B 614 +#define PPC_INST_BL 615 +#define PPC_INST_BA 616 +#define PPC_INST_BLA 617 +#define PPC_INST_MCRF 618 +#define PPC_INST_BLR 619 +#define PPC_INST_BR 620 +#define PPC_INST_BLRL 621 +#define PPC_INST_BRL 622 +#define PPC_INST_BDNZLR 623 +#define PPC_INST_BDNZLRL 624 +#define PPC_INST_BDZLR 625 +#define PPC_INST_BDZLRL 626 +#define PPC_INST_BLTLR 627 +#define PPC_INST_BLTR 628 +#define PPC_INST_BLTLRL 629 +#define PPC_INST_BLTRL 630 +#define PPC_INST_BGTLR 631 +#define PPC_INST_BGTR 632 +#define PPC_INST_BGTLRL 633 +#define PPC_INST_BGTRL 634 +#define PPC_INST_BEQLR 635 +#define PPC_INST_BEQR 636 +#define PPC_INST_BEQLRL 637 +#define PPC_INST_BEQRL 638 +#define PPC_INST_BSOLR 639 +#define PPC_INST_BSOR 640 +#define PPC_INST_BSOLRL 641 +#define PPC_INST_BSORL 642 +#define PPC_INST_BUNLR 643 +#define PPC_INST_BUNLRL 644 +#define PPC_INST_BGELR 645 +#define PPC_INST_BGER 646 +#define PPC_INST_BGELRL 647 +#define PPC_INST_BGERL 648 +#define PPC_INST_BNLLR 649 +#define PPC_INST_BNLR 650 +#define PPC_INST_BNLLRL 651 +#define PPC_INST_BNLRL 652 +#define PPC_INST_BLELR 653 +#define PPC_INST_BLER 654 +#define PPC_INST_BLELRL 655 +#define PPC_INST_BLERL 656 +#define PPC_INST_BNGLR 657 +#define PPC_INST_BNGR 658 +#define PPC_INST_BNGLRL 659 +#define PPC_INST_BNGRL 660 +#define PPC_INST_BNELR 661 +#define PPC_INST_BNER 662 +#define PPC_INST_BNELRL 663 +#define PPC_INST_BNERL 664 +#define PPC_INST_BNSLR 665 +#define PPC_INST_BNSR 666 +#define PPC_INST_BNSLRL 667 +#define PPC_INST_BNSRL 668 +#define PPC_INST_BNULR 669 +#define PPC_INST_BNULRL 670 +#define PPC_INST_BTLR 671 +#define PPC_INST_BBTR 672 +#define PPC_INST_BTLRL 673 +#define PPC_INST_BBTRL 674 +#define PPC_INST_BFLR 675 +#define PPC_INST_BBFR 676 +#define PPC_INST_BFLRL 677 +#define PPC_INST_BBFRL 678 +#define PPC_INST_BDNZTLR 679 +#define PPC_INST_BDNZTLRL 680 +#define PPC_INST_BDNZFLR 681 +#define PPC_INST_BDNZFLRL 682 +#define PPC_INST_BDZTLR 683 +#define PPC_INST_BDZTLRL 684 +#define PPC_INST_BDZFLR 685 +#define PPC_INST_BDZFLRL 686 +#define PPC_INST_BCLR 687 +#define PPC_INST_BCLRL 688 +#define PPC_INST_BCR 689 +#define PPC_INST_BCRL 690 +#define PPC_INST_BCLRE 691 +#define PPC_INST_BCLREL 692 +#define PPC_INST_RFID 693 +#define PPC_INST_CRNOT 694 +#define PPC_INST_CRNOR 695 +#define PPC_INST_RFMCI 696 +#define PPC_INST_RFI 697 +#define PPC_INST_RFCI 698 +#define PPC_INST_RFSVC 699 +#define PPC_INST_CRANDC 700 +#define PPC_INST_ISYNC 701 +#define PPC_INST_ICS 702 +#define PPC_INST_CRCLR 703 +#define PPC_INST_CRXOR 704 +#define PPC_INST_CRNAND 705 +#define PPC_INST_CRAND 706 +#define PPC_INST_HRFID 707 +#define PPC_INST_CRSET 708 +#define PPC_INST_CREQV 709 +#define PPC_INST_DOZE 710 +#define PPC_INST_CRORC 711 +#define PPC_INST_NAP 712 +#define PPC_INST_CRMOVE 713 +#define PPC_INST_CROR 714 +#define PPC_INST_SLEEP 715 +#define PPC_INST_RVWINKLE 716 +#define PPC_INST_BCTR 717 +#define PPC_INST_BCTRL 718 +#define PPC_INST_BLTCTR 719 +#define PPC_INST_BLTCTRL 720 +#define PPC_INST_BGTCTR 721 +#define PPC_INST_BGTCTRL 722 +#define PPC_INST_BEQCTR 723 +#define PPC_INST_BEQCTRL 724 +#define PPC_INST_BSOCTR 725 +#define PPC_INST_BSOCTRL 726 +#define PPC_INST_BUNCTR 727 +#define PPC_INST_BUNCTRL 728 +#define PPC_INST_BGECTR 729 +#define PPC_INST_BGECTRL 730 +#define PPC_INST_BNLCTR 731 +#define PPC_INST_BNLCTRL 732 +#define PPC_INST_BLECTR 733 +#define PPC_INST_BLECTRL 734 +#define PPC_INST_BNGCTR 735 +#define PPC_INST_BNGCTRL 736 +#define PPC_INST_BNECTR 737 +#define PPC_INST_BNECTRL 738 +#define PPC_INST_BNSCTR 739 +#define PPC_INST_BNSCTRL 740 +#define PPC_INST_BNUCTR 741 +#define PPC_INST_BNUCTRL 742 +#define PPC_INST_BTCTR 743 +#define PPC_INST_BTCTRL 744 +#define PPC_INST_BFCTR 745 +#define PPC_INST_BFCTRL 746 +#define PPC_INST_BCCTR 747 +#define PPC_INST_BCCTRL 748 +#define PPC_INST_BCC 749 +#define PPC_INST_BCCL 750 +#define PPC_INST_BCCTRE 751 +#define PPC_INST_BCCTREL 752 +#define PPC_INST_RLWIMI 753 +#define PPC_INST_RLIMI 754 +#define PPC_INST_ROTLWI 755 +#define PPC_INST_CLRLWI 756 +#define PPC_INST_RLWINM 757 +#define PPC_INST_RLINM 758 +#define PPC_INST_RLMI 759 +#define PPC_INST_BE 760 +#define PPC_INST_BEL 761 +#define PPC_INST_BEA 762 +#define PPC_INST_BELA 763 +#define PPC_INST_ROTLW 764 +#define PPC_INST_RLWNM 765 +#define PPC_INST_RLNM 766 +#define PPC_INST_NOP 767 +#define PPC_INST_ORI 768 +#define PPC_INST_ORIL 769 +#define PPC_INST_ORIS 770 +#define PPC_INST_ORIU 771 +#define PPC_INST_XORI 772 +#define PPC_INST_XORIL 773 +#define PPC_INST_XORIS 774 +#define PPC_INST_XORIU 775 +#define PPC_INST_ANDI 776 +#define PPC_INST_ANDIL 777 +#define PPC_INST_ANDIS 778 +#define PPC_INST_ANDIU 779 +#define PPC_INST_ROTLDI 780 +#define PPC_INST_CLRLDI 781 +#define PPC_INST_RLDICL 782 +#define PPC_INST_RLDICR 783 +#define PPC_INST_RLDIC 784 +#define PPC_INST_RLDIMI 785 +#define PPC_INST_ROTLD 786 +#define PPC_INST_RLDCL 787 +#define PPC_INST_RLDCR 788 +#define PPC_INST_CMPW 789 +#define PPC_INST_CMPD 790 +#define PPC_INST_CMP 791 +#define PPC_INST_TWLGT 792 +#define PPC_INST_TLGT 793 +#define PPC_INST_TWLLT 794 +#define PPC_INST_TLLT 795 +#define PPC_INST_TWEQ 796 +#define PPC_INST_TEQ 797 +#define PPC_INST_TWLGE 798 +#define PPC_INST_TLGE 799 +#define PPC_INST_TWLNL 800 +#define PPC_INST_TLNL 801 +#define PPC_INST_TWLLE 802 +#define PPC_INST_TLLE 803 +#define PPC_INST_TWLNG 804 +#define PPC_INST_TLNG 805 +#define PPC_INST_TWGT 806 +#define PPC_INST_TGT 807 +#define PPC_INST_TWGE 808 +#define PPC_INST_TGE 809 +#define PPC_INST_TWNL 810 +#define PPC_INST_TNL 811 +#define PPC_INST_TWLT 812 +#define PPC_INST_TLT 813 +#define PPC_INST_TWLE 814 +#define PPC_INST_TLE 815 +#define PPC_INST_TWNG 816 +#define PPC_INST_TNG 817 +#define PPC_INST_TWNE 818 +#define PPC_INST_TNE 819 +#define PPC_INST_TRAP 820 +#define PPC_INST_TW 821 +#define PPC_INST_T 822 +#define PPC_INST_SUBFC 823 +#define PPC_INST_SF 824 +#define PPC_INST_SUBC 825 +#define PPC_INST_SUBFCO 826 +#define PPC_INST_SFO 827 +#define PPC_INST_SUBCO 828 +#define PPC_INST_MULHDU 829 +#define PPC_INST_ADDC 830 +#define PPC_INST_A 831 +#define PPC_INST_ADDCO 832 +#define PPC_INST_AO 833 +#define PPC_INST_MULHWU 834 +#define PPC_INST_ISELLT 835 +#define PPC_INST_ISELGT 836 +#define PPC_INST_ISELEQ 837 +#define PPC_INST_ISEL 838 +#define PPC_INST_MFOCRF 839 +#define PPC_INST_MFCR 840 +#define PPC_INST_LWARX 841 +#define PPC_INST_LDX 842 +#define PPC_INST_ICBT 843 +#define PPC_INST_LWZX 844 +#define PPC_INST_LX 845 +#define PPC_INST_SLW 846 +#define PPC_INST_SL 847 +#define PPC_INST_CNTLZW 848 +#define PPC_INST_CNTLZ 849 +#define PPC_INST_SLD 850 +#define PPC_INST_AND 851 +#define PPC_INST_MASKG 852 +#define PPC_INST_ICBTE 853 +#define PPC_INST_LWZXE 854 +#define PPC_INST_CMPLW 855 +#define PPC_INST_CMPLD 856 +#define PPC_INST_CMPL 857 +#define PPC_INST_SUBF 858 +#define PPC_INST_SUB 859 +#define PPC_INST_SUBFO 860 +#define PPC_INST_SUBO 861 +#define PPC_INST_LDUX 862 +#define PPC_INST_DCBST 863 +#define PPC_INST_LWZUX 864 +#define PPC_INST_LUX 865 +#define PPC_INST_DCBSTE 866 +#define PPC_INST_LWZUXE 867 +#define PPC_INST_CNTLZD 868 +#define PPC_INST_ANDC 869 +#define PPC_INST_TDLGT 870 +#define PPC_INST_TDLLT 871 +#define PPC_INST_TDEQ 872 +#define PPC_INST_TDLGE 873 +#define PPC_INST_TDLNL 874 +#define PPC_INST_TDLLE 875 +#define PPC_INST_TDLNG 876 +#define PPC_INST_TDGT 877 +#define PPC_INST_TDGE 878 +#define PPC_INST_TDNL 879 +#define PPC_INST_TDLT 880 +#define PPC_INST_TDLE 881 +#define PPC_INST_TDNG 882 +#define PPC_INST_TDNE 883 +#define PPC_INST_TD 884 +#define PPC_INST_MULHD 885 +#define PPC_INST_MULHW 886 +#define PPC_INST_DLMZB 887 +#define PPC_INST_MTSRD 888 +#define PPC_INST_MFMSR 889 +#define PPC_INST_LDARX 890 +#define PPC_INST_DCBFL 891 +#define PPC_INST_DCBF 892 +#define PPC_INST_LBZX 893 +#define PPC_INST_DCBFE 894 +#define PPC_INST_LBZXE 895 +#define PPC_INST_NEG 896 +#define PPC_INST_NEGO 897 +#define PPC_INST_MUL 898 +#define PPC_INST_MULO 899 +#define PPC_INST_MTSRDIN 900 +#define PPC_INST_CLF 901 +#define PPC_INST_LBZUX 902 +#define PPC_INST_POPCNTB 903 +#define PPC_INST_NOT 904 +#define PPC_INST_NOR 905 +#define PPC_INST_LWARXE 906 +#define PPC_INST_LBZUXE 907 +#define PPC_INST_WRTEE 908 +#define PPC_INST_DCBTSTLS 909 +#define PPC_INST_SUBFE 910 +#define PPC_INST_SFE 911 +#define PPC_INST_SUBFEO 912 +#define PPC_INST_SFEO 913 +#define PPC_INST_ADDE 914 +#define PPC_INST_AE 915 +#define PPC_INST_ADDEO 916 +#define PPC_INST_AEO 917 +#define PPC_INST_DCBTSTLSE 918 +#define PPC_INST_MTOCRF 919 +#define PPC_INST_MTCR 920 +#define PPC_INST_MTCRF 921 +#define PPC_INST_MTMSR 922 +#define PPC_INST_STDX 923 +#define PPC_INST_STWCX 924 +#define PPC_INST_STWX 925 +#define PPC_INST_STX 926 +#define PPC_INST_STWCXE 927 +#define PPC_INST_STWXE 928 +#define PPC_INST_SLQ 929 +#define PPC_INST_SLE 930 +#define PPC_INST_PRTYW 931 +#define PPC_INST_WRTEEI 932 +#define PPC_INST_DCBTLS 933 +#define PPC_INST_DCBTLSE 934 +#define PPC_INST_MTMSRD 935 +#define PPC_INST_STDUX 936 +#define PPC_INST_STWUX 937 +#define PPC_INST_STUX 938 +#define PPC_INST_SLIQ 939 +#define PPC_INST_PRTYD 940 +#define PPC_INST_STWUXE 941 +#define PPC_INST_SUBFZE 942 +#define PPC_INST_SFZE 943 +#define PPC_INST_SUBFZEO 944 +#define PPC_INST_SFZEO 945 +#define PPC_INST_ADDZE 946 +#define PPC_INST_AZE 947 +#define PPC_INST_ADDZEO 948 +#define PPC_INST_AZEO 949 +#define PPC_INST_MTSR 950 +#define PPC_INST_STDCX 951 +#define PPC_INST_STBX 952 +#define PPC_INST_SLLQ 953 +#define PPC_INST_SLEQ 954 +#define PPC_INST_STBXE 955 +#define PPC_INST_ICBLC 956 +#define PPC_INST_SUBFME 957 +#define PPC_INST_SFME 958 +#define PPC_INST_SUBFMEO 959 +#define PPC_INST_SFMEO 960 +#define PPC_INST_MULLD 961 +#define PPC_INST_MULLDO 962 +#define PPC_INST_ADDME 963 +#define PPC_INST_AME 964 +#define PPC_INST_ADDMEO 965 +#define PPC_INST_AMEO 966 +#define PPC_INST_MULLW 967 +#define PPC_INST_MULS 968 +#define PPC_INST_MULLWO 969 +#define PPC_INST_MULSO 970 +#define PPC_INST_ICBLCE 971 +#define PPC_INST_MTSRIN 972 +#define PPC_INST_MTSRI 973 +#define PPC_INST_DCBTST 974 +#define PPC_INST_STBUX 975 +#define PPC_INST_SLLIQ 976 +#define PPC_INST_DCBTSTE 977 +#define PPC_INST_STBUXE 978 +#define PPC_INST_MFDCRX 979 +#define PPC_INST_DOZ 980 +#define PPC_INST_DOZO 981 +#define PPC_INST_ADD 982 +#define PPC_INST_CAX 983 +#define PPC_INST_ADDO 984 +#define PPC_INST_CAXO 985 +#define PPC_INST_TLBIEL 986 +#define PPC_INST_MFAPIDI 987 +#define PPC_INST_LSCBX 988 +#define PPC_INST_DCBT 989 +#define PPC_INST_LHZX 990 +#define PPC_INST_EQV 991 +#define PPC_INST_DCBTE 992 +#define PPC_INST_LHZXE 993 +#define PPC_INST_TLBIE 994 +#define PPC_INST_TLBI 995 +#define PPC_INST_ECIWX 996 +#define PPC_INST_LHZUX 997 +#define PPC_INST_XOR 998 +#define PPC_INST_LHZUXE 999 +#define PPC_INST_MFEXISR 1000 +#define PPC_INST_MFEXIER 1001 +#define PPC_INST_MFBR0 1002 +#define PPC_INST_MFBR1 1003 +#define PPC_INST_MFBR2 1004 +#define PPC_INST_MFBR3 1005 +#define PPC_INST_MFBR4 1006 +#define PPC_INST_MFBR5 1007 +#define PPC_INST_MFBR6 1008 +#define PPC_INST_MFBR7 1009 +#define PPC_INST_MFBEAR 1010 +#define PPC_INST_MFBESR 1011 +#define PPC_INST_MFIOCR 1012 +#define PPC_INST_MFDMACR0 1013 +#define PPC_INST_MFDMACT0 1014 +#define PPC_INST_MFDMADA0 1015 +#define PPC_INST_MFDMASA0 1016 +#define PPC_INST_MFDMACC0 1017 +#define PPC_INST_MFDMACR1 1018 +#define PPC_INST_MFDMACT1 1019 +#define PPC_INST_MFDMADA1 1020 +#define PPC_INST_MFDMASA1 1021 +#define PPC_INST_MFDMACC1 1022 +#define PPC_INST_MFDMACR2 1023 +#define PPC_INST_MFDMACT2 1024 +#define PPC_INST_MFDMADA2 1025 +#define PPC_INST_MFDMASA2 1026 +#define PPC_INST_MFDMACC2 1027 +#define PPC_INST_MFDMACR3 1028 +#define PPC_INST_MFDMACT3 1029 +#define PPC_INST_MFDMADA3 1030 +#define PPC_INST_MFDMASA3 1031 +#define PPC_INST_MFDMACC3 1032 +#define PPC_INST_MFDMASR 1033 +#define PPC_INST_MFDCR 1034 +#define PPC_INST_DIV 1035 +#define PPC_INST_DIVO 1036 +#define PPC_INST_MFPMR 1037 +#define PPC_INST_MFMQ 1038 +#define PPC_INST_MFXER 1039 +#define PPC_INST_MFRTCU 1040 +#define PPC_INST_MFRTCL 1041 +#define PPC_INST_MFDEC 1042 +#define PPC_INST_MFLR 1043 +#define PPC_INST_MFCTR 1044 +#define PPC_INST_MFTID 1045 +#define PPC_INST_MFDSISR 1046 +#define PPC_INST_MFDAR 1047 +#define PPC_INST_MFSDR0 1048 +#define PPC_INST_MFSDR1 1049 +#define PPC_INST_MFSRR0 1050 +#define PPC_INST_MFSRR1 1051 +#define PPC_INST_MFCFAR 1052 +#define PPC_INST_MFPID 1053 +#define PPC_INST_MFCSRR0 1054 +#define PPC_INST_MFCSRR1 1055 +#define PPC_INST_MFDEAR 1056 +#define PPC_INST_MFESR 1057 +#define PPC_INST_MFIVPR 1058 +#define PPC_INST_MFCMPA 1059 +#define PPC_INST_MFCMPB 1060 +#define PPC_INST_MFCMPC 1061 +#define PPC_INST_MFCMPD 1062 +#define PPC_INST_MFICR 1063 +#define PPC_INST_MFDER 1064 +#define PPC_INST_MFCOUNTA 1065 +#define PPC_INST_MFCOUNTB 1066 +#define PPC_INST_MFCMPE 1067 +#define PPC_INST_MFCMPF 1068 +#define PPC_INST_MFCMPG 1069 +#define PPC_INST_MFCMPH 1070 +#define PPC_INST_MFLCTRL1 1071 +#define PPC_INST_MFLCTRL2 1072 +#define PPC_INST_MFICTRL 1073 +#define PPC_INST_MFBAR 1074 +#define PPC_INST_MFVRSAVE 1075 +#define PPC_INST_MFUSPRG0 1076 +#define PPC_INST_MFTB 1077 +#define PPC_INST_MFTBL 1078 +#define PPC_INST_MFTBU 1079 +#define PPC_INST_MFSPRG 1080 +#define PPC_INST_MFSPRG0 1081 +#define PPC_INST_MFSPRG1 1082 +#define PPC_INST_MFSPRG2 1083 +#define PPC_INST_MFSPRG3 1084 +#define PPC_INST_MFSPRG4 1085 +#define PPC_INST_MFSPRG5 1086 +#define PPC_INST_MFSPRG6 1087 +#define PPC_INST_MFSPRG7 1088 +#define PPC_INST_MFASR 1089 +#define PPC_INST_MFEAR 1090 +#define PPC_INST_MFPIR 1091 +#define PPC_INST_MFPVR 1092 +#define PPC_INST_MFDBSR 1093 +#define PPC_INST_MFDBCR0 1094 +#define PPC_INST_MFDBCR1 1095 +#define PPC_INST_MFDBCR2 1096 +#define PPC_INST_MFIAC1 1097 +#define PPC_INST_MFIAC2 1098 +#define PPC_INST_MFIAC3 1099 +#define PPC_INST_MFIAC4 1100 +#define PPC_INST_MFDAC1 1101 +#define PPC_INST_MFDAC2 1102 +#define PPC_INST_MFDVC1 1103 +#define PPC_INST_MFDVC2 1104 +#define PPC_INST_MFTSR 1105 +#define PPC_INST_MFTCR 1106 +#define PPC_INST_MFIVOR0 1107 +#define PPC_INST_MFIVOR1 1108 +#define PPC_INST_MFIVOR2 1109 +#define PPC_INST_MFIVOR3 1110 +#define PPC_INST_MFIVOR4 1111 +#define PPC_INST_MFIVOR5 1112 +#define PPC_INST_MFIVOR6 1113 +#define PPC_INST_MFIVOR7 1114 +#define PPC_INST_MFIVOR8 1115 +#define PPC_INST_MFIVOR9 1116 +#define PPC_INST_MFIVOR10 1117 +#define PPC_INST_MFIVOR11 1118 +#define PPC_INST_MFIVOR12 1119 +#define PPC_INST_MFIVOR13 1120 +#define PPC_INST_MFIVOR14 1121 +#define PPC_INST_MFIVOR15 1122 +#define PPC_INST_MFSPEFSCR 1123 +#define PPC_INST_MFBBEAR 1124 +#define PPC_INST_MFBBTAR 1125 +#define PPC_INST_MFIVOR32 1126 +#define PPC_INST_MFIVOR33 1127 +#define PPC_INST_MFIVOR34 1128 +#define PPC_INST_MFIVOR35 1129 +#define PPC_INST_MFIBATU 1130 +#define PPC_INST_MFIBATL 1131 +#define PPC_INST_MFDBATU 1132 +#define PPC_INST_MFDBATL 1133 +#define PPC_INST_MFIC_CST 1134 +#define PPC_INST_MFIC_ADR 1135 +#define PPC_INST_MFIC_DAT 1136 +#define PPC_INST_MFDC_CST 1137 +#define PPC_INST_MFDC_ADR 1138 +#define PPC_INST_MFMCSRR0 1139 +#define PPC_INST_MFDC_DAT 1140 +#define PPC_INST_MFMCSRR1 1141 +#define PPC_INST_MFMCSR 1142 +#define PPC_INST_MFMCAR 1143 +#define PPC_INST_MFDPDR 1144 +#define PPC_INST_MFDPIR 1145 +#define PPC_INST_MFIMMR 1146 +#define PPC_INST_MFMI_CTR 1147 +#define PPC_INST_MFMI_AP 1148 +#define PPC_INST_MFMI_EPN 1149 +#define PPC_INST_MFMI_TWC 1150 +#define PPC_INST_MFMI_RPN 1151 +#define PPC_INST_MFMD_CTR 1152 +#define PPC_INST_MFM_CASID 1153 +#define PPC_INST_MFMD_AP 1154 +#define PPC_INST_MFMD_EPN 1155 +#define PPC_INST_MFMD_TWB 1156 +#define PPC_INST_MFMD_TWC 1157 +#define PPC_INST_MFMD_RPN 1158 +#define PPC_INST_MFM_TW 1159 +#define PPC_INST_MFMI_DBCAM 1160 +#define PPC_INST_MFMI_DBRAM0 1161 +#define PPC_INST_MFMI_DBRAM1 1162 +#define PPC_INST_MFMD_DBCAM 1163 +#define PPC_INST_MFMD_DBRAM0 1164 +#define PPC_INST_MFMD_DBRAM1 1165 +#define PPC_INST_MFUMMCR0 1166 +#define PPC_INST_MFUPMC1 1167 +#define PPC_INST_MFUPMC2 1168 +#define PPC_INST_MFUSIA 1169 +#define PPC_INST_MFUMMCR1 1170 +#define PPC_INST_MFUPMC3 1171 +#define PPC_INST_MFUPMC4 1172 +#define PPC_INST_MFZPR 1173 +#define PPC_INST_MFCCR0 1174 +#define PPC_INST_MFMMCR0 1175 +#define PPC_INST_MFPMC1 1176 +#define PPC_INST_MFSGR 1177 +#define PPC_INST_MFPMC2 1178 +#define PPC_INST_MFDCWR 1179 +#define PPC_INST_MFSIA 1180 +#define PPC_INST_MFSLER 1181 +#define PPC_INST_MFMMCR1 1182 +#define PPC_INST_MFSU0R 1183 +#define PPC_INST_MFPMC3 1184 +#define PPC_INST_MFPMC4 1185 +#define PPC_INST_MFICDBDR 1186 +#define PPC_INST_MFEVPR 1187 +#define PPC_INST_MFCDBCR 1188 +#define PPC_INST_MFPIT 1189 +#define PPC_INST_MFTBHI 1190 +#define PPC_INST_MFTBLO 1191 +#define PPC_INST_MFSRR2 1192 +#define PPC_INST_MFSRR3 1193 +#define PPC_INST_MFL2CR 1194 +#define PPC_INST_MFDCCR 1195 +#define PPC_INST_MFICCR 1196 +#define PPC_INST_MFICTC 1197 +#define PPC_INST_MFPBL1 1198 +#define PPC_INST_MFTHRM1 1199 +#define PPC_INST_MFPBU1 1200 +#define PPC_INST_MFTHRM2 1201 +#define PPC_INST_MFPBL2 1202 +#define PPC_INST_MFTHRM3 1203 +#define PPC_INST_MFPBU2 1204 +#define PPC_INST_MFSPR 1205 +#define PPC_INST_LWAX 1206 +#define PPC_INST_DST 1207 +#define PPC_INST_DSTT 1208 +#define PPC_INST_LHAX 1209 +#define PPC_INST_LHAXE 1210 +#define PPC_INST_DSTST 1211 +#define PPC_INST_DSTSTT 1212 +#define PPC_INST_DCCCI 1213 +#define PPC_INST_ABS 1214 +#define PPC_INST_ABSO 1215 +#define PPC_INST_DIVS 1216 +#define PPC_INST_DIVSO 1217 +#define PPC_INST_TLBIA 1218 +#define PPC_INST_LWAUX 1219 +#define PPC_INST_LHAUX 1220 +#define PPC_INST_LHAUXE 1221 +#define PPC_INST_MTDCRX 1222 +#define PPC_INST_DCBLC 1223 +#define PPC_INST_SUBFE64 1224 +#define PPC_INST_SUBFE64O 1225 +#define PPC_INST_ADDE64 1226 +#define PPC_INST_ADDE64O 1227 +#define PPC_INST_DCBLCE 1228 +#define PPC_INST_SLBMTE 1229 +#define PPC_INST_STHX 1230 +#define PPC_INST_CMPB 1231 +#define PPC_INST_LFQX 1232 +#define PPC_INST_LFDPX 1233 +#define PPC_INST_LFQUX 1234 +#define PPC_INST_STFQX 1235 +#define PPC_INST_STFDPX 1236 +#define PPC_INST_STFQUX 1237 +#define PPC_INST_ORC 1238 +#define PPC_INST_SRADI 1239 +#define PPC_INST_STHXE 1240 +#define PPC_INST_SLBIE 1241 +#define PPC_INST_ECOWX 1242 +#define PPC_INST_STHUX 1243 +#define PPC_INST_STHUXE 1244 +#define PPC_INST_CCTPL 1245 +#define PPC_INST_CCTPM 1246 +#define PPC_INST_CCTPH 1247 +#define PPC_INST_DB8CYC 1248 +#define PPC_INST_DB10CYC 1249 +#define PPC_INST_DB12CYC 1250 +#define PPC_INST_DB16CYC 1251 +#define PPC_INST_MR 1252 +#define PPC_INST_OR 1253 +#define PPC_INST_MTEXISR 1254 +#define PPC_INST_MTEXIER 1255 +#define PPC_INST_MTBR0 1256 +#define PPC_INST_MTBR1 1257 +#define PPC_INST_MTBR2 1258 +#define PPC_INST_MTBR3 1259 +#define PPC_INST_MTBR4 1260 +#define PPC_INST_MTBR5 1261 +#define PPC_INST_MTBR6 1262 +#define PPC_INST_MTBR7 1263 +#define PPC_INST_MTBEAR 1264 +#define PPC_INST_MTBESR 1265 +#define PPC_INST_MTIOCR 1266 +#define PPC_INST_MTDMACR0 1267 +#define PPC_INST_MTDMACT0 1268 +#define PPC_INST_MTDMADA0 1269 +#define PPC_INST_MTDMASA0 1270 +#define PPC_INST_MTDMACC0 1271 +#define PPC_INST_MTDMACR1 1272 +#define PPC_INST_MTDMACT1 1273 +#define PPC_INST_MTDMADA1 1274 +#define PPC_INST_MTDMASA1 1275 +#define PPC_INST_MTDMACC1 1276 +#define PPC_INST_MTDMACR2 1277 +#define PPC_INST_MTDMACT2 1278 +#define PPC_INST_MTDMADA2 1279 +#define PPC_INST_MTDMASA2 1280 +#define PPC_INST_MTDMACC2 1281 +#define PPC_INST_MTDMACR3 1282 +#define PPC_INST_MTDMACT3 1283 +#define PPC_INST_MTDMADA3 1284 +#define PPC_INST_MTDMASA3 1285 +#define PPC_INST_MTDMACC3 1286 +#define PPC_INST_MTDMASR 1287 +#define PPC_INST_MTDCR 1288 +#define PPC_INST_SUBFZE64 1289 +#define PPC_INST_SUBFZE64O 1290 +#define PPC_INST_DIVDU 1291 +#define PPC_INST_DIVDUO 1292 +#define PPC_INST_ADDZE64 1293 +#define PPC_INST_ADDZE64O 1294 +#define PPC_INST_DIVWU 1295 +#define PPC_INST_DIVWUO 1296 +#define PPC_INST_MTMQ 1297 +#define PPC_INST_MTXER 1298 +#define PPC_INST_MTLR 1299 +#define PPC_INST_MTCTR 1300 +#define PPC_INST_MTTID 1301 +#define PPC_INST_MTDSISR 1302 +#define PPC_INST_MTDAR 1303 +#define PPC_INST_MTRTCU 1304 +#define PPC_INST_MTRTCL 1305 +#define PPC_INST_MTDEC 1306 +#define PPC_INST_MTSDR0 1307 +#define PPC_INST_MTSDR1 1308 +#define PPC_INST_MTSRR0 1309 +#define PPC_INST_MTSRR1 1310 +#define PPC_INST_MTCFAR 1311 +#define PPC_INST_MTPID 1312 +#define PPC_INST_MTDECAR 1313 +#define PPC_INST_MTCSRR0 1314 +#define PPC_INST_MTCSRR1 1315 +#define PPC_INST_MTDEAR 1316 +#define PPC_INST_MTESR 1317 +#define PPC_INST_MTIVPR 1318 +#define PPC_INST_MTCMPA 1319 +#define PPC_INST_MTCMPB 1320 +#define PPC_INST_MTCMPC 1321 +#define PPC_INST_MTCMPD 1322 +#define PPC_INST_MTICR 1323 +#define PPC_INST_MTDER 1324 +#define PPC_INST_MTCOUNTA 1325 +#define PPC_INST_MTCOUNTB 1326 +#define PPC_INST_MTCMPE 1327 +#define PPC_INST_MTCMPF 1328 +#define PPC_INST_MTCMPG 1329 +#define PPC_INST_MTCMPH 1330 +#define PPC_INST_MTLCTRL1 1331 +#define PPC_INST_MTLCTRL2 1332 +#define PPC_INST_MTICTRL 1333 +#define PPC_INST_MTBAR 1334 +#define PPC_INST_MTVRSAVE 1335 +#define PPC_INST_MTUSPRG0 1336 +#define PPC_INST_MTSPRG 1337 +#define PPC_INST_MTSPRG0 1338 +#define PPC_INST_MTSPRG1 1339 +#define PPC_INST_MTSPRG2 1340 +#define PPC_INST_MTSPRG3 1341 +#define PPC_INST_MTSPRG4 1342 +#define PPC_INST_MTSPRG5 1343 +#define PPC_INST_MTSPRG6 1344 +#define PPC_INST_MTSPRG7 1345 +#define PPC_INST_MTASR 1346 +#define PPC_INST_MTEAR 1347 +#define PPC_INST_MTTBL 1348 +#define PPC_INST_MTTBU 1349 +#define PPC_INST_MTDBSR 1350 +#define PPC_INST_MTDBCR0 1351 +#define PPC_INST_MTDBCR1 1352 +#define PPC_INST_MTDBCR2 1353 +#define PPC_INST_MTIAC1 1354 +#define PPC_INST_MTIAC2 1355 +#define PPC_INST_MTIAC3 1356 +#define PPC_INST_MTIAC4 1357 +#define PPC_INST_MTDAC1 1358 +#define PPC_INST_MTDAC2 1359 +#define PPC_INST_MTDVC1 1360 +#define PPC_INST_MTDVC2 1361 +#define PPC_INST_MTTSR 1362 +#define PPC_INST_MTTCR 1363 +#define PPC_INST_MTIVOR0 1364 +#define PPC_INST_MTIVOR1 1365 +#define PPC_INST_MTIVOR2 1366 +#define PPC_INST_MTIVOR3 1367 +#define PPC_INST_MTIVOR4 1368 +#define PPC_INST_MTIVOR5 1369 +#define PPC_INST_MTIVOR6 1370 +#define PPC_INST_MTIVOR7 1371 +#define PPC_INST_MTIVOR8 1372 +#define PPC_INST_MTIVOR9 1373 +#define PPC_INST_MTIVOR10 1374 +#define PPC_INST_MTIVOR11 1375 +#define PPC_INST_MTIVOR12 1376 +#define PPC_INST_MTIVOR13 1377 +#define PPC_INST_MTIVOR14 1378 +#define PPC_INST_MTIVOR15 1379 +#define PPC_INST_MTSPEFSCR 1380 +#define PPC_INST_MTBBEAR 1381 +#define PPC_INST_MTBBTAR 1382 +#define PPC_INST_MTIVOR32 1383 +#define PPC_INST_MTIVOR33 1384 +#define PPC_INST_MTIVOR34 1385 +#define PPC_INST_MTIVOR35 1386 +#define PPC_INST_MTIBATU 1387 +#define PPC_INST_MTIBATL 1388 +#define PPC_INST_MTDBATU 1389 +#define PPC_INST_MTDBATL 1390 +#define PPC_INST_MTMCSRR0 1391 +#define PPC_INST_MTMCSRR1 1392 +#define PPC_INST_MTMCSR 1393 +#define PPC_INST_MTUMMCR0 1394 +#define PPC_INST_MTUPMC1 1395 +#define PPC_INST_MTUPMC2 1396 +#define PPC_INST_MTUSIA 1397 +#define PPC_INST_MTUMMCR1 1398 +#define PPC_INST_MTUPMC3 1399 +#define PPC_INST_MTUPMC4 1400 +#define PPC_INST_MTZPR 1401 +#define PPC_INST_MTCCR0 1402 +#define PPC_INST_MTMMCR0 1403 +#define PPC_INST_MTSGR 1404 +#define PPC_INST_MTPMC1 1405 +#define PPC_INST_MTDCWR 1406 +#define PPC_INST_MTPMC2 1407 +#define PPC_INST_MTSLER 1408 +#define PPC_INST_MTSIA 1409 +#define PPC_INST_MTSU0R 1410 +#define PPC_INST_MTMMCR1 1411 +#define PPC_INST_MTPMC3 1412 +#define PPC_INST_MTPMC4 1413 +#define PPC_INST_MTICDBDR 1414 +#define PPC_INST_MTEVPR 1415 +#define PPC_INST_MTCDBCR 1416 +#define PPC_INST_MTPIT 1417 +#define PPC_INST_MTTBHI 1418 +#define PPC_INST_MTTBLO 1419 +#define PPC_INST_MTSRR2 1420 +#define PPC_INST_MTSRR3 1421 +#define PPC_INST_MTL2CR 1422 +#define PPC_INST_MTDCCR 1423 +#define PPC_INST_MTICCR 1424 +#define PPC_INST_MTICTC 1425 +#define PPC_INST_MTPBL1 1426 +#define PPC_INST_MTTHRM1 1427 +#define PPC_INST_MTPBU1 1428 +#define PPC_INST_MTTHRM2 1429 +#define PPC_INST_MTPBL2 1430 +#define PPC_INST_MTTHRM3 1431 +#define PPC_INST_MTPBU2 1432 +#define PPC_INST_MTSPR 1433 +#define PPC_INST_DCBI 1434 +#define PPC_INST_NAND 1435 +#define PPC_INST_DCBIE 1436 +#define PPC_INST_DCREAD 1437 +#define PPC_INST_MTPMR 1438 +#define PPC_INST_ICBTLS 1439 +#define PPC_INST_NABS 1440 +#define PPC_INST_SUBFME64 1441 +#define PPC_INST_NABSO 1442 +#define PPC_INST_SUBFME64O 1443 +#define PPC_INST_DIVD 1444 +#define PPC_INST_DIVDO 1445 +#define PPC_INST_ADDME64 1446 +#define PPC_INST_ADDME64O 1447 +#define PPC_INST_DIVW 1448 +#define PPC_INST_DIVWO 1449 +#define PPC_INST_ICBTLSE 1450 +#define PPC_INST_SLBIA 1451 +#define PPC_INST_CLI 1452 +#define PPC_INST_STDCXE 1453 +#define PPC_INST_MCRXR 1454 +#define PPC_INST_BBLELS 1455 +#define PPC_INST_MCRXR64 1456 +#define PPC_INST_CLCS 1457 +#define PPC_INST_LDBRX 1458 +#define PPC_INST_LSWX 1459 +#define PPC_INST_LSX 1460 +#define PPC_INST_LWBRX 1461 +#define PPC_INST_LBRX 1462 +#define PPC_INST_LFSX 1463 +#define PPC_INST_SRW 1464 +#define PPC_INST_SR 1465 +#define PPC_INST_RRIB 1466 +#define PPC_INST_SRD 1467 +#define PPC_INST_MASKIR 1468 +#define PPC_INST_LWBRXE 1469 +#define PPC_INST_LFSXE 1470 +#define PPC_INST_BBELR 1471 +#define PPC_INST_TLBSYNC 1472 +#define PPC_INST_LFSUX 1473 +#define PPC_INST_LFSUXE 1474 +#define PPC_INST_MFSR 1475 +#define PPC_INST_LSWI 1476 +#define PPC_INST_LSI 1477 +#define PPC_INST_LWSYNC 1478 +#define PPC_INST_PTESYNC 1479 +#define PPC_INST_MSYNC 1480 +#define PPC_INST_SYNC 1481 +#define PPC_INST_DCS 1482 +#define PPC_INST_LFDX 1483 +#define PPC_INST_LFDXE 1484 +#define PPC_INST_MFFGPR 1485 +#define PPC_INST_MFSRI 1486 +#define PPC_INST_DCLST 1487 +#define PPC_INST_LFDUX 1488 +#define PPC_INST_LFDUXE 1489 +#define PPC_INST_MFSRIN 1490 +#define PPC_INST_STDBRX 1491 +#define PPC_INST_STSWX 1492 +#define PPC_INST_STSX 1493 +#define PPC_INST_STWBRX 1494 +#define PPC_INST_STBRX 1495 +#define PPC_INST_STFSX 1496 +#define PPC_INST_SRQ 1497 +#define PPC_INST_SRE 1498 +#define PPC_INST_STWBRXE 1499 +#define PPC_INST_STFSXE 1500 +#define PPC_INST_STFSUX 1501 +#define PPC_INST_SRIQ 1502 +#define PPC_INST_STFSUXE 1503 +#define PPC_INST_STSWI 1504 +#define PPC_INST_STSI 1505 +#define PPC_INST_STFDX 1506 +#define PPC_INST_SRLQ 1507 +#define PPC_INST_SREQ 1508 +#define PPC_INST_STFDXE 1509 +#define PPC_INST_MFTGPR 1510 +#define PPC_INST_DCBA 1511 +#define PPC_INST_STFDUX 1512 +#define PPC_INST_SRLIQ 1513 +#define PPC_INST_DCBAE 1514 +#define PPC_INST_STFDUXE 1515 +#define PPC_INST_TLBIVAX 1516 +#define PPC_INST_TLBIVAXE 1517 +#define PPC_INST_LWZCIX 1518 +#define PPC_INST_LHBRX 1519 +#define PPC_INST_SRAW 1520 +#define PPC_INST_SRA 1521 +#define PPC_INST_SRAD 1522 +#define PPC_INST_LHBRXE 1523 +#define PPC_INST_LDXE 1524 +#define PPC_INST_LDUXE 1525 +#define PPC_INST_RAC 1526 +#define PPC_INST_LHZCIX 1527 +#define PPC_INST_DSS 1528 +#define PPC_INST_DSSALL 1529 +#define PPC_INST_SRAWI 1530 +#define PPC_INST_SRAI 1531 +#define PPC_INST_SLBMFEV 1532 +#define PPC_INST_LBZCIX 1533 +#define PPC_INST_MBAR 1534 +#define PPC_INST_EIEIO 1535 +#define PPC_INST_LFIWAX 1536 +#define PPC_INST_LDCIX 1537 +#define PPC_INST_TLBSX 1538 +#define PPC_INST_TLBSXE 1539 +#define PPC_INST_SLBMFEE 1540 +#define PPC_INST_STWCIX 1541 +#define PPC_INST_STHBRX 1542 +#define PPC_INST_SRAQ 1543 +#define PPC_INST_SREA 1544 +#define PPC_INST_EXTSH 1545 +#define PPC_INST_EXTS 1546 +#define PPC_INST_STHBRXE 1547 +#define PPC_INST_STDXE 1548 +#define PPC_INST_TLBREHI 1549 +#define PPC_INST_TLBRELO 1550 +#define PPC_INST_TLBRE 1551 +#define PPC_INST_STHCIX 1552 +#define PPC_INST_SRAIQ 1553 +#define PPC_INST_EXTSB 1554 +#define PPC_INST_STDUXE 1555 +#define PPC_INST_ICCCI 1556 +#define PPC_INST_TLBWEHI 1557 +#define PPC_INST_TLBWELO 1558 +#define PPC_INST_TLBWE 1559 +#define PPC_INST_TLBLD 1560 +#define PPC_INST_STBCIX 1561 +#define PPC_INST_ICBI 1562 +#define PPC_INST_STFIWX 1563 +#define PPC_INST_EXTSW 1564 +#define PPC_INST_ICREAD 1565 +#define PPC_INST_ICBIE 1566 +#define PPC_INST_STFIWXE 1567 +#define PPC_INST_TLBLI 1568 +#define PPC_INST_STDCIX 1569 +#define PPC_INST_DCBZL 1570 +#define PPC_INST_DCBZ 1571 +#define PPC_INST_DCLZ 1572 +#define PPC_INST_DCBZE 1573 +#define PPC_INST_LVEBX 1574 +#define PPC_INST_LVEHX 1575 +#define PPC_INST_LVEWX 1576 +#define PPC_INST_LVSL 1577 +#define PPC_INST_LVSR 1578 +#define PPC_INST_LVX 1579 +#define PPC_INST_LVXL 1580 +#define PPC_INST_STVEBX 1581 +#define PPC_INST_STVEHX 1582 +#define PPC_INST_STVEWX 1583 +#define PPC_INST_STVX 1584 +#define PPC_INST_STVXL 1585 +#define PPC_INST_LVLX 1586 +#define PPC_INST_LVLXL 1587 +#define PPC_INST_LVRX 1588 +#define PPC_INST_LVRXL 1589 +#define PPC_INST_STVLX 1590 +#define PPC_INST_STVLXL 1591 +#define PPC_INST_STVRX 1592 +#define PPC_INST_STVRXL 1593 +#define PPC_INST_LWZ 1594 +#define PPC_INST_L 1595 +#define PPC_INST_LWZU 1596 +#define PPC_INST_LU 1597 +#define PPC_INST_LBZ 1598 +#define PPC_INST_LBZU 1599 +#define PPC_INST_STW 1600 +#define PPC_INST_ST 1601 +#define PPC_INST_STWU 1602 +#define PPC_INST_STU 1603 +#define PPC_INST_STB 1604 +#define PPC_INST_STBU 1605 +#define PPC_INST_LHZ 1606 +#define PPC_INST_LHZU 1607 +#define PPC_INST_LHA 1608 +#define PPC_INST_LHAU 1609 +#define PPC_INST_STH 1610 +#define PPC_INST_STHU 1611 +#define PPC_INST_LMW 1612 +#define PPC_INST_LM 1613 +#define PPC_INST_STMW 1614 +#define PPC_INST_STM 1615 +#define PPC_INST_LFS 1616 +#define PPC_INST_LFSU 1617 +#define PPC_INST_LFD 1618 +#define PPC_INST_LFDU 1619 +#define PPC_INST_STFS 1620 +#define PPC_INST_STFSU 1621 +#define PPC_INST_STFD 1622 +#define PPC_INST_STFDU 1623 +#define PPC_INST_LQ 1624 +#define PPC_INST_LFQ 1625 +#define PPC_INST_LFQU 1626 +#define PPC_INST_LFDP 1627 +#define PPC_INST_LBZE 1628 +#define PPC_INST_LBZUE 1629 +#define PPC_INST_LHZE 1630 +#define PPC_INST_LHZUE 1631 +#define PPC_INST_LHAE 1632 +#define PPC_INST_LHAUE 1633 +#define PPC_INST_LWZE 1634 +#define PPC_INST_LWZUE 1635 +#define PPC_INST_STBE 1636 +#define PPC_INST_STBUE 1637 +#define PPC_INST_STHE 1638 +#define PPC_INST_STHUE 1639 +#define PPC_INST_STWE 1640 +#define PPC_INST_STWUE 1641 +#define PPC_INST_LD 1642 +#define PPC_INST_LDU 1643 +#define PPC_INST_LWA 1644 +#define PPC_INST_DADD 1645 +#define PPC_INST_DQUA 1646 +#define PPC_INST_FDIVS 1647 +#define PPC_INST_FSUBS 1648 +#define PPC_INST_FADDS 1649 +#define PPC_INST_FSQRTS 1650 +#define PPC_INST_FRES 1651 +#define PPC_INST_FMULS 1652 +#define PPC_INST_FRSQRTES 1653 +#define PPC_INST_FMSUBS 1654 +#define PPC_INST_FMADDS 1655 +#define PPC_INST_FNMSUBS 1656 +#define PPC_INST_FNMADDS 1657 +#define PPC_INST_DMUL 1658 +#define PPC_INST_DRRND 1659 +#define PPC_INST_DSCLI 1660 +#define PPC_INST_DQUAI 1661 +#define PPC_INST_DSCRI 1662 +#define PPC_INST_DRINTX 1663 +#define PPC_INST_DCMPO 1664 +#define PPC_INST_DTSTEX 1665 +#define PPC_INST_DTSTDC 1666 +#define PPC_INST_DTSTDG 1667 +#define PPC_INST_DRINTN 1668 +#define PPC_INST_DCTDP 1669 +#define PPC_INST_DCTFIX 1670 +#define PPC_INST_DDEDPD 1671 +#define PPC_INST_DXEX 1672 +#define PPC_INST_DSUB 1673 +#define PPC_INST_DDIV 1674 +#define PPC_INST_DCMPU 1675 +#define PPC_INST_DTSTSF 1676 +#define PPC_INST_DRSP 1677 +#define PPC_INST_DCFFIX 1678 +#define PPC_INST_DENBCD 1679 +#define PPC_INST_DIEX 1680 +#define PPC_INST_STFQ 1681 +#define PPC_INST_STFQU 1682 +#define PPC_INST_STFDP 1683 +#define PPC_INST_LDE 1684 +#define PPC_INST_LDUE 1685 +#define PPC_INST_LFSE 1686 +#define PPC_INST_LFSUE 1687 +#define PPC_INST_LFDE 1688 +#define PPC_INST_LFDUE 1689 +#define PPC_INST_STDE 1690 +#define PPC_INST_STDUE 1691 +#define PPC_INST_STFSE 1692 +#define PPC_INST_STFSUE 1693 +#define PPC_INST_STFDE 1694 +#define PPC_INST_STFDUE 1695 +#define PPC_INST_STD 1696 +#define PPC_INST_STDU 1697 +#define PPC_INST_STQ 1698 +#define PPC_INST_FCMPU 1699 +#define PPC_INST_DADDQ 1700 +#define PPC_INST_DQUAQ 1701 +#define PPC_INST_FCPSGN 1702 +#define PPC_INST_FRSP 1703 +#define PPC_INST_FCTIW 1704 +#define PPC_INST_FCIR 1705 +#define PPC_INST_FCTIWZ 1706 +#define PPC_INST_FCIRZ 1707 +#define PPC_INST_FDIV 1708 +#define PPC_INST_FD 1709 +#define PPC_INST_FSUB 1710 +#define PPC_INST_FS 1711 +#define PPC_INST_FADD 1712 +#define PPC_INST_FA 1713 +#define PPC_INST_FSQRT 1714 +#define PPC_INST_FSEL 1715 +#define PPC_INST_FRE 1716 +#define PPC_INST_FMUL 1717 +#define PPC_INST_FM 1718 +#define PPC_INST_FRSQRTE 1719 +#define PPC_INST_FMSUB 1720 +#define PPC_INST_FMS 1721 +#define PPC_INST_FMADD 1722 +#define PPC_INST_FMA 1723 +#define PPC_INST_FNMSUB 1724 +#define PPC_INST_FNMS 1725 +#define PPC_INST_FNMADD 1726 +#define PPC_INST_FNMA 1727 +#define PPC_INST_FCMPO 1728 +#define PPC_INST_DMULQ 1729 +#define PPC_INST_DRRNDQ 1730 +#define PPC_INST_MTFSB1 1731 +#define PPC_INST_FNEG 1732 +#define PPC_INST_MCRFS 1733 +#define PPC_INST_DSCLIQ 1734 +#define PPC_INST_DQUAIQ 1735 +#define PPC_INST_MTFSB0 1736 +#define PPC_INST_FMR 1737 +#define PPC_INST_DSCRIQ 1738 +#define PPC_INST_DRINTXQ 1739 +#define PPC_INST_DCMPOQ 1740 +#define PPC_INST_MTFSFI 1741 +#define PPC_INST_FNABS 1742 +#define PPC_INST_DTSTEXQ 1743 +#define PPC_INST_DTSTDCQ 1744 +#define PPC_INST_DTSTDGQ 1745 +#define PPC_INST_DRINTNQ 1746 +#define PPC_INST_DCTQPQ 1747 +#define PPC_INST_FABS 1748 +#define PPC_INST_DCTFIXQ 1749 +#define PPC_INST_DDEDPDQ 1750 +#define PPC_INST_DXEXQ 1751 +#define PPC_INST_FRIN 1752 +#define PPC_INST_FRIZ 1753 +#define PPC_INST_FRIP 1754 +#define PPC_INST_FRIM 1755 +#define PPC_INST_DSUBQ 1756 +#define PPC_INST_DDIVQ 1757 +#define PPC_INST_MFFS 1758 +#define PPC_INST_DCMPUQ 1759 +#define PPC_INST_DTSTSFQ 1760 +#define PPC_INST_MTFSF 1761 +#define PPC_INST_DRDPQ 1762 +#define PPC_INST_DCFFIXQ 1763 +#define PPC_INST_FCTID 1764 +#define PPC_INST_FCTIDZ 1765 +#define PPC_INST_DENBCDQ 1766 +#define PPC_INST_FCFID 1767 +#define PPC_INST_DIEXQ 1768