mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 01:02:08 +00:00
Implement some more vector instructions.
This commit is contained in:
Skyth
parent
d4c267c123
commit
8d4d99e644
@ -1127,11 +1127,27 @@ int main()
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break;
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case PPC_INST_VADDSHS:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.s16, _mm_adds_epi16(_mm_load_si128((__m128i*)ctx.v{}.s16), _mm_load_si128((__m128i*)ctx.v{}.s16)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VADDUBM:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_add_epi8(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VADDUBS:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_adds_epu8(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VADDUHM:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u16, _mm_add_epi16(_mm_load_si128((__m128i*)ctx.v{}.u16), _mm_load_si128((__m128i*)ctx.v{}.u16)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VADDUWM:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u32, _mm_add_epi32(_mm_load_si128((__m128i*)ctx.v{}.u32), _mm_load_si128((__m128i*)ctx.v{}.u32)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VADDUWS:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u32, _mm_adds_epu32(_mm_load_si128((__m128i*)ctx.v{}.u32), _mm_load_si128((__m128i*)ctx.v{}.u32)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VAND:
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@ -1144,14 +1160,36 @@ int main()
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break;
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case PPC_INST_VAVGSB:
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// TODO: no _mm_avg_epi8
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break;
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case PPC_INST_VAVGSH:
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// TODO: no _mm_avg_epi16
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break;
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case PPC_INST_VAVGUB:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_avg_epu8(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VCFPSXWS128:
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break;
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case PPC_INST_VCFSX:
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// NOTE: ignoring the immediate since it's always 0 in the game code
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_cvtepi32_ps(_mm_load_si128((__m128i*)ctx.v{}.u32)));", insn.operands[0], insn.operands[1]);
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break;
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case PPC_INST_VCFUX:
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break;
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case PPC_INST_VCMPBFP128:
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break;
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case PPC_INST_VCMPEQFP:
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case PPC_INST_VCMPEQFP128:
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_cmpeq_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VCMPEQUB:
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case PPC_INST_VCMPEQUW:
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case PPC_INST_VCMPEQUW128:
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@ -1193,6 +1231,7 @@ int main()
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break;
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case PPC_INST_VMAXSW:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u32, _mm_max_epi32(_mm_load_si128((__m128i*)ctx.v{}.u32), _mm_load_si128((__m128i*)ctx.v{}.u32)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VMINFP:
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@ -1201,13 +1240,29 @@ int main()
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break;
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case PPC_INST_VMRGHB:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_unpackhi_epi8(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VMRGHH:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u16, _mm_unpackhi_epi16(_mm_load_si128((__m128i*)ctx.v{}.u16), _mm_load_si128((__m128i*)ctx.v{}.u16)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VMRGHW:
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case PPC_INST_VMRGHW128:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u32, _mm_unpackhi_epi32(_mm_load_si128((__m128i*)ctx.v{}.u32), _mm_load_si128((__m128i*)ctx.v{}.u32)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VMRGLB:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_unpacklo_epi8(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VMRGLH:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u16, _mm_unpacklo_epi16(_mm_load_si128((__m128i*)ctx.v{}.u16), _mm_load_si128((__m128i*)ctx.v{}.u16)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VMRGLW:
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case PPC_INST_VMRGLW128:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u32, _mm_unpacklo_epi32(_mm_load_si128((__m128i*)ctx.v{}.u32), _mm_load_si128((__m128i*)ctx.v{}.u32)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VMSUM3FP128:
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@ -1237,7 +1292,10 @@ int main()
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case PPC_INST_VPERM128:
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case PPC_INST_VPERMWI128:
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case PPC_INST_VPKD3D128:
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break;
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case PPC_INST_VPKSHUS:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_packus_epi16(_mm_load_si128((__m128i*)ctx.v{}.s16), _mm_load_si128((__m128i*)ctx.v{}.s16)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VREFP:
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@ -1246,9 +1304,18 @@ int main()
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break;
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case PPC_INST_VRFIM128:
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_round_ps(_mm_load_ps(ctx.v{}.f32), _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC));", insn.operands[0], insn.operands[1]);
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break;
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case PPC_INST_VRFIN:
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case PPC_INST_VRFIN128:
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_round_ps(_mm_load_ps(ctx.v{}.f32), _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC));", insn.operands[0], insn.operands[1]);
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break;
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case PPC_INST_VRFIZ128:
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_round_ps(_mm_load_ps(ctx.v{}.f32), _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC));", insn.operands[0], insn.operands[1]);
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break;
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case PPC_INST_VRLIMI128:
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break;
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@ -1258,6 +1325,9 @@ int main()
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break;
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case PPC_INST_VSEL:
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_or_ps(_mm_and_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32)), _mm_andnot_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32))));", insn.operands[0], insn.operands[3], insn.operands[1], insn.operands[3], insn.operands[2]);
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break;
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case PPC_INST_VSLB:
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case PPC_INST_VSLDOI:
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case PPC_INST_VSLDOI128:
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@ -338,3 +338,8 @@ struct PPCContext
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PPCVRegister v[128];
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};
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};
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inline __m128i _mm_adds_epu32(__m128i a, __m128i b)
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{
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return _mm_add_epi32(_mm_min_epu32(a, _mm_xor_si128(b, _mm_cmpeq_epi32(b, b))), b);
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}
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