mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-04-19 19:01:17 +00:00
Merge branch 'main' of https://github.com/hedge-dev/PowerRecomp
This commit is contained in:
Sajid
commit
a3126d6beb
@ -6,7 +6,7 @@
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#include <disasm.h>
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#include <filesystem>
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#define TEST_FILE "add.elf"
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#define TEST_FILE "cond.elf"
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int main()
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{
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@ -44,6 +44,8 @@ int main()
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std::filesystem::create_directory("out");
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FILE* f = fopen("out/" TEST_FILE ".cpp", "w");
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std::println(f, "#include <ppc_context.h>\n");
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for (const auto& fn : functions)
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{
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auto base = fn.base;
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@ -61,11 +63,16 @@ int main()
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name = std::format("sub_{:X}", base);
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}
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std::println(f, "void {}() {{", name);
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std::println(f, "void {}(PPCContext& __restrict ctx, uint8_t* __restrict base) {{", name);
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std::println(f, "\tuint32_t ea;\n");
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ppc_insn insn;
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while (base < end)
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{
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auto block = fn.SearchBlock(base);
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if (block != -1 && (fn.base + fn.blocks[block].base) == base)
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std::println(f, "loc_{:X}:", base);
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ppc::Disassemble(data, 4, base, insn);
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base += 4;
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@ -76,41 +83,68 @@ int main()
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}
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else
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{
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// TODO: need to handle instructions that treat r0 as 0
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std::println(f, "\t// {:x} {} {}", base - 4, insn.opcode->name, insn.op_str);
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switch (insn.opcode->id)
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{
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case PPC_INST_ADD:
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std::println(f, "\tr{} = r{} + r{};", insn.operands[0], insn.operands[1], insn.operands[2]);
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// TODO: . variant
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std::println(f, "\tctx.r{}.u64 = ctx.r{}.u64 + ctx.r{}.u64;", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_ADDI:
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std::println(f, "\tr{} = r{} + {};", insn.operands[0], insn.operands[1], insn.operands[2]);
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std::println(f, "\tctx.r{}.s64 = ctx.r{}.s64 + {};", insn.operands[0], insn.operands[1], static_cast<int32_t>(insn.operands[2]));
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break;
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case PPC_INST_STWU:
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std::println(f, "\tea = r{} + {};", insn.operands[2], static_cast<int32_t>(insn.operands[1]));
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std::println(f, "\t*ea = byteswap(r{});", insn.operands[0]);
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std::println(f, "\tr{} = ea;", insn.operands[2]);
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case PPC_INST_ADDIC:
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break;
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case PPC_INST_STW:
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std::println(f, "\t*(r{} + {}) = byteswap(r{});", insn.operands[2], static_cast<int32_t>(insn.operands[1]), insn.operands[0]);
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case PPC_INST_ADDIS:
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// TODO: validate the sign extend
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std::println(f, "\tctx.r{}.s64 = ctx.r{}.s64 + {};", insn.operands[0], insn.operands[1], static_cast<int32_t>(insn.operands[2] << 16));
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break;
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case PPC_INST_MR:
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std::println(f, "\tr{} = r{};", insn.operands[0], insn.operands[1]);
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case PPC_INST_ADDZE:
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break;
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case PPC_INST_LWZ:
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std::println(f, "\tr{} = *(r{} + {});", insn.operands[0], insn.operands[2], insn.operands[1]);
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case PPC_INST_AND:
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// TODO: . variant
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std::println(f, "\tctx.r{}.u64 = ctx.r{}.u64 & ctx.r{}.u64;", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_LI:
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std::println(f, "\tr{} = {};", insn.operands[0], insn.operands[1]);
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case PPC_INST_ANDC:
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// TODO: . variant
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std::println(f, "\tctx.r{}.u64 = ctx.r{}.u64 & ~ctx.r{}.u64;", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_MFLR:
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std::println(f, "\tr{} = lr;", insn.operands[0]);
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case PPC_INST_ANDI:
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// TODO: . variant
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std::println(f, "\tctx.r{}.u64 = ctx.r{}.u64 & {};", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_MTLR:
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std::println(f, "\tlr = r{};", insn.operands[0]);
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case PPC_INST_ANDIS:
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// TODO: . variant
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std::println(f, "\tctx.r{}.u64 = ctx.r{}.u64 & {};", insn.operands[0], insn.operands[1], insn.operands[2] << 16);
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break;
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case PPC_INST_BLR:
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std::println(f, "\treturn;");
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case PPC_INST_ATTN:
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// undefined instruction
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break;
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case PPC_INST_B:
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case PPC_INST_BCTR:
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case PPC_INST_BCTRL:
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case PPC_INST_BDNZ:
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case PPC_INST_BDNZF:
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case PPC_INST_BEQ:
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case PPC_INST_BEQLR:
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case PPC_INST_BGE:
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case PPC_INST_BGELR:
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case PPC_INST_BGT:
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case PPC_INST_BGTLR:
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break;
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case PPC_INST_BL:
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{
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std::string targetName = "";
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@ -123,10 +157,426 @@ int main()
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{
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targetName = std::format("sub_{:X}", insn.operands[0]);
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}
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std::println(f, "\tlr = 0x{:x};", base);
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std::println(f, "\t{}();", targetName);
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std::println(f, "\tctx.lr = 0x{:X};", base);
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std::println(f, "\t{}(ctx, base);", targetName);
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break;
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}
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case PPC_INST_BLE:
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case PPC_INST_BLELR:
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break;
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case PPC_INST_BLR:
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// TODO: do they use this for anything other than a return?
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std::println(f, "\treturn;");
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break;
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case PPC_INST_BLRL:
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case PPC_INST_BLT:
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case PPC_INST_BLTLR:
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case PPC_INST_BNE:
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case PPC_INST_BNECTR:
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case PPC_INST_BNELR:
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case PPC_INST_CCTPL:
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case PPC_INST_CCTPM:
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case PPC_INST_CLRLDI:
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case PPC_INST_CLRLWI:
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case PPC_INST_CMPD:
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case PPC_INST_CMPDI:
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case PPC_INST_CMPLD:
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case PPC_INST_CMPLDI:
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case PPC_INST_CMPLW:
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case PPC_INST_CMPLWI:
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case PPC_INST_CMPW:
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case PPC_INST_CMPWI:
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case PPC_INST_CNTLZD:
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case PPC_INST_CNTLZW:
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case PPC_INST_DB16CYC:
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case PPC_INST_DCBF:
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// no op
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break;
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case PPC_INST_DCBT:
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// no op
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break;
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case PPC_INST_DCBTST:
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case PPC_INST_DCBZ:
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case PPC_INST_DCBZL:
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case PPC_INST_DIVD:
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case PPC_INST_DIVDU:
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case PPC_INST_DIVW:
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case PPC_INST_DIVWU:
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break;
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case PPC_INST_EIEIO:
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// no op
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break;
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case PPC_INST_EXTSB:
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case PPC_INST_EXTSH:
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case PPC_INST_EXTSW:
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case PPC_INST_FABS:
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case PPC_INST_FADD:
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case PPC_INST_FADDS:
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case PPC_INST_FCFID:
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case PPC_INST_FCMPU:
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case PPC_INST_FCTID:
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case PPC_INST_FCTIDZ:
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case PPC_INST_FCTIWZ:
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case PPC_INST_FDIV:
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case PPC_INST_FDIVS:
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case PPC_INST_FMADD:
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case PPC_INST_FMADDS:
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case PPC_INST_FMR:
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case PPC_INST_FMSUB:
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case PPC_INST_FMSUBS:
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case PPC_INST_FMUL:
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case PPC_INST_FMULS:
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case PPC_INST_FNABS:
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case PPC_INST_FNEG:
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case PPC_INST_FNMADDS:
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case PPC_INST_FNMSUB:
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case PPC_INST_FNMSUBS:
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case PPC_INST_FRES:
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case PPC_INST_FRSP:
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case PPC_INST_FSEL:
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case PPC_INST_FSQRT:
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case PPC_INST_FSQRTS:
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case PPC_INST_FSUB:
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case PPC_INST_FSUBS:
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break;
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case PPC_INST_LBZ:
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std::println(f, "\tctx.r{}.u64 = PPC_LOAD_U8({} + ctx.r{}.u32);", insn.operands[0], int32_t(insn.operands[1]), insn.operands[2]);
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break;
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case PPC_INST_LBZU:
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std::println(f, "\tea = {} + ctx.r{}.u32;", int32_t(insn.operands[1]), insn.operands[2]);
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std::println(f, "\tctx.r{}.u64 = PPC_LOAD_U8(ea);", insn.operands[0]);
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std::println(f, "\tctx.r{}.u64 = ea;", insn.operands[2]);
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break;
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case PPC_INST_LBZX:
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std::println(f, "\tctx.r{}.u64 = PPC_LOAD_U8(ctx.r{}.u32 + ctx.r{}.u32);", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_LD:
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std::println(f, "\tctx.r{}.u64 = PPC_LOAD_U64({} + ctx.r{}.u32);", insn.operands[0], int32_t(insn.operands[1]), insn.operands[2]);
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break;
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||||
case PPC_INST_LDARX:
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case PPC_INST_LDU:
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case PPC_INST_LDX:
|
||||
case PPC_INST_LFD:
|
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case PPC_INST_LFDX:
|
||||
case PPC_INST_LFS:
|
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case PPC_INST_LFSX:
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case PPC_INST_LHA:
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case PPC_INST_LHAX:
|
||||
case PPC_INST_LHZ:
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||||
case PPC_INST_LHZX:
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||||
break;
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||||
|
||||
case PPC_INST_LI:
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||||
// TODO: validate the sign extend
|
||||
std::println(f, "\tctx.r{}.s64 = {};", insn.operands[0], int32_t(insn.operands[1]));
|
||||
break;
|
||||
|
||||
case PPC_INST_LIS:
|
||||
// TODO: validate the sign extend
|
||||
std::println(f, "\tctx.r{}.s64 = {};", insn.operands[0], int32_t(insn.operands[1] << 16));
|
||||
break;
|
||||
|
||||
case PPC_INST_LVEWX:
|
||||
case PPC_INST_LVEWX128:
|
||||
case PPC_INST_LVLX:
|
||||
case PPC_INST_LVLX128:
|
||||
case PPC_INST_LVRX:
|
||||
case PPC_INST_LVRX128:
|
||||
case PPC_INST_LVSL:
|
||||
case PPC_INST_LVSR:
|
||||
case PPC_INST_LVX:
|
||||
case PPC_INST_LVX128:
|
||||
case PPC_INST_LWA:
|
||||
case PPC_INST_LWARX:
|
||||
case PPC_INST_LWAX:
|
||||
case PPC_INST_LWBRX:
|
||||
break;
|
||||
|
||||
case PPC_INST_LWSYNC:
|
||||
// no op
|
||||
break;
|
||||
|
||||
case PPC_INST_LWZ:
|
||||
std::println(f, "\tctx.r{}.u64 = PPC_LOAD_U32({} + ctx.r{}.u32);", insn.operands[0], int32_t(insn.operands[1]), insn.operands[2]);
|
||||
break;
|
||||
|
||||
case PPC_INST_LWZU:
|
||||
case PPC_INST_LWZX:
|
||||
case PPC_INST_MFCR:
|
||||
case PPC_INST_MFFS:
|
||||
break;
|
||||
|
||||
case PPC_INST_MFLR:
|
||||
std::println(f, "\tctx.lr = ctx.r{}.u64;", insn.operands[0]);
|
||||
break;
|
||||
|
||||
case PPC_INST_MFMSR:
|
||||
case PPC_INST_MFOCRF:
|
||||
case PPC_INST_MFTB:
|
||||
break;
|
||||
|
||||
case PPC_INST_MR:
|
||||
// TODO: . variant
|
||||
std::println(f, "\tctx.r{}.u64 = ctx.r{}.u64;", insn.operands[0], insn.operands[1]);
|
||||
break;
|
||||
|
||||
case PPC_INST_MTCR:
|
||||
case PPC_INST_MTCTR:
|
||||
case PPC_INST_MTFSF:
|
||||
break;
|
||||
|
||||
case PPC_INST_MTLR:
|
||||
std::println(f, "\tctx.r{}.u64 = ctx.lr;", insn.operands[0]);
|
||||
break;
|
||||
|
||||
case PPC_INST_MTMSRD:
|
||||
case PPC_INST_MTXER:
|
||||
case PPC_INST_MULCHWU:
|
||||
case PPC_INST_MULHHW:
|
||||
case PPC_INST_MULHW:
|
||||
case PPC_INST_MULHWU:
|
||||
case PPC_INST_MULLD:
|
||||
break;
|
||||
|
||||
case PPC_INST_MULLI:
|
||||
std::println(f, "\tctx.r{}.s64 = ctx.r{}.s64 * {};", insn.operands[0], insn.operands[1], static_cast<int32_t>(insn.operands[2]));
|
||||
break;
|
||||
|
||||
case PPC_INST_MULLW:
|
||||
break;
|
||||
|
||||
case PPC_INST_NAND:
|
||||
std::println(f, "\tctx.r{}.u64 = ~(ctx.r{}.u64 & ctx.r{}.u64);", insn.operands[0], insn.operands[1], insn.operands[2]);
|
||||
break;
|
||||
|
||||
case PPC_INST_NEG:
|
||||
// TODO: . variant
|
||||
std::println(f, "\tctx.r{}.s64 = -ctx.r{}.s64;", insn.operands[0], insn.operands[1]);
|
||||
break;
|
||||
|
||||
case PPC_INST_NOP:
|
||||
// no op
|
||||
break;
|
||||
|
||||
case PPC_INST_NOR:
|
||||
std::println(f, "\tctx.r{}.u64 = ~(ctx.r{}.u64 | ctx.r{}.u64);", insn.operands[0], insn.operands[1], insn.operands[2]);
|
||||
break;
|
||||
|
||||
case PPC_INST_NOT:
|
||||
// TODO: . variant
|
||||
std::println(f, "\tctx.r{}.u64 = ~ctx.r{}.u64;", insn.operands[0], insn.operands[1]);
|
||||
break;
|
||||
|
||||
case PPC_INST_OR:
|
||||
// TODO: . variant
|
||||
std::println(f, "\tctx.r{}.u64 = ctx.r{}.u64 | ctx.r{}.u64;", insn.operands[0], insn.operands[1], insn.operands[2]);
|
||||
break;
|
||||
|
||||
case PPC_INST_ORC:
|
||||
std::println(f, "\tctx.r{}.u64 = ctx.r{}.u64 | ~ctx.r{}.u64;", insn.operands[0], insn.operands[1], insn.operands[2]);
|
||||
break;
|
||||
|
||||
case PPC_INST_ORI:
|
||||
std::println(f, "\tctx.r{}.u64 = ctx.r{}.u64 | {}", insn.operands[0], insn.operands[1], insn.operands[2]);
|
||||
break;
|
||||
|
||||
case PPC_INST_ORIS:
|
||||
std::println(f, "\tctx.r{}.u64 = ctx.r{}.u64 | {}", insn.operands[0], insn.operands[1], insn.operands[2] << 16);
|
||||
break;
|
||||
|
||||
case PPC_INST_RLDICL:
|
||||
case PPC_INST_RLDICR:
|
||||
case PPC_INST_RLDIMI:
|
||||
case PPC_INST_RLWIMI:
|
||||
case PPC_INST_RLWINM:
|
||||
case PPC_INST_ROTLDI:
|
||||
case PPC_INST_ROTLW:
|
||||
case PPC_INST_ROTLWI:
|
||||
case PPC_INST_SLD:
|
||||
case PPC_INST_SLW:
|
||||
case PPC_INST_SRAD:
|
||||
case PPC_INST_SRADI:
|
||||
case PPC_INST_SRAW:
|
||||
case PPC_INST_SRAWI:
|
||||
case PPC_INST_SRD:
|
||||
case PPC_INST_SRW:
|
||||
case PPC_INST_STB:
|
||||
case PPC_INST_STBU:
|
||||
case PPC_INST_STBX:
|
||||
case PPC_INST_STD:
|
||||
case PPC_INST_STDCX:
|
||||
case PPC_INST_STDU:
|
||||
case PPC_INST_STDX:
|
||||
case PPC_INST_STFD:
|
||||
case PPC_INST_STFDX:
|
||||
case PPC_INST_STFIWX:
|
||||
case PPC_INST_STFS:
|
||||
case PPC_INST_STFSX:
|
||||
case PPC_INST_STH:
|
||||
case PPC_INST_STHBRX:
|
||||
case PPC_INST_STHX:
|
||||
case PPC_INST_STVEHX:
|
||||
case PPC_INST_STVEWX:
|
||||
case PPC_INST_STVEWX128:
|
||||
case PPC_INST_STVLX:
|
||||
case PPC_INST_STVLX128:
|
||||
case PPC_INST_STVRX:
|
||||
case PPC_INST_STVRX128:
|
||||
case PPC_INST_STVX:
|
||||
case PPC_INST_STVX128:
|
||||
break;
|
||||
|
||||
case PPC_INST_STW:
|
||||
std::println(f, "\tPPC_STORE_U32({} + ctx.r{}.u32, ctx.r{}.u32);", int32_t(insn.operands[1]), insn.operands[2], insn.operands[0]);
|
||||
break;
|
||||
|
||||
case PPC_INST_STWBRX:
|
||||
case PPC_INST_STWCX:
|
||||
break;
|
||||
|
||||
case PPC_INST_STWU:
|
||||
std::println(f, "\tea = {} + ctx.r{}.u32;", int32_t(insn.operands[1]), insn.operands[2]);
|
||||
std::println(f, "\tPPC_STORE_U32(ea, ctx.r{}.u32);", insn.operands[0]);
|
||||
std::println(f, "\tctx.r{}.u64 = ea;", insn.operands[0]);
|
||||
break;
|
||||
|
||||
case PPC_INST_STWUX:
|
||||
case PPC_INST_STWX:
|
||||
case PPC_INST_SUBF:
|
||||
case PPC_INST_SUBFC:
|
||||
case PPC_INST_SUBFE:
|
||||
case PPC_INST_SUBFIC:
|
||||
case PPC_INST_SYNC:
|
||||
case PPC_INST_TDLGEI:
|
||||
case PPC_INST_TDLLEI:
|
||||
case PPC_INST_TWI:
|
||||
case PPC_INST_TWLGEI:
|
||||
case PPC_INST_TWLLEI:
|
||||
case PPC_INST_VADDFP:
|
||||
case PPC_INST_VADDFP128:
|
||||
case PPC_INST_VADDSHS:
|
||||
case PPC_INST_VADDUBM:
|
||||
case PPC_INST_VADDUBS:
|
||||
case PPC_INST_VADDUHM:
|
||||
case PPC_INST_VADDUWM:
|
||||
case PPC_INST_VADDUWS:
|
||||
case PPC_INST_VAND:
|
||||
case PPC_INST_VAND128:
|
||||
case PPC_INST_VANDC128:
|
||||
case PPC_INST_VAVGSB:
|
||||
case PPC_INST_VAVGSH:
|
||||
case PPC_INST_VAVGUB:
|
||||
case PPC_INST_VCFPSXWS128:
|
||||
case PPC_INST_VCFSX:
|
||||
case PPC_INST_VCFUX:
|
||||
case PPC_INST_VCMPBFP128:
|
||||
case PPC_INST_VCMPEQFP:
|
||||
case PPC_INST_VCMPEQFP128:
|
||||
case PPC_INST_VCMPEQUB:
|
||||
case PPC_INST_VCMPEQUW:
|
||||
case PPC_INST_VCMPEQUW128:
|
||||
case PPC_INST_VCMPGEFP:
|
||||
case PPC_INST_VCMPGEFP128:
|
||||
case PPC_INST_VCMPGTFP:
|
||||
case PPC_INST_VCMPGTFP128:
|
||||
case PPC_INST_VCMPGTUB:
|
||||
case PPC_INST_VCMPGTUH:
|
||||
case PPC_INST_VCSXWFP128:
|
||||
case PPC_INST_VCTSXS:
|
||||
case PPC_INST_VCUXWFP128:
|
||||
case PPC_INST_VEXPTEFP128:
|
||||
case PPC_INST_VLOGEFP128:
|
||||
case PPC_INST_VMADDCFP128:
|
||||
case PPC_INST_VMADDFP:
|
||||
case PPC_INST_VMADDFP128:
|
||||
case PPC_INST_VMAXFP:
|
||||
case PPC_INST_VMAXFP128:
|
||||
case PPC_INST_VMAXSW:
|
||||
case PPC_INST_VMINFP:
|
||||
case PPC_INST_VMINFP128:
|
||||
case PPC_INST_VMRGHB:
|
||||
case PPC_INST_VMRGHH:
|
||||
case PPC_INST_VMRGHW:
|
||||
case PPC_INST_VMRGHW128:
|
||||
case PPC_INST_VMRGLB:
|
||||
case PPC_INST_VMRGLH:
|
||||
case PPC_INST_VMRGLW:
|
||||
case PPC_INST_VMRGLW128:
|
||||
case PPC_INST_VMSUM3FP128:
|
||||
case PPC_INST_VMSUM4FP128:
|
||||
case PPC_INST_VMULFP128:
|
||||
case PPC_INST_VNMSUBFP:
|
||||
case PPC_INST_VNMSUBFP128:
|
||||
case PPC_INST_VOR:
|
||||
case PPC_INST_VOR128:
|
||||
case PPC_INST_VPERM:
|
||||
case PPC_INST_VPERM128:
|
||||
case PPC_INST_VPERMWI128:
|
||||
case PPC_INST_VPKD3D128:
|
||||
case PPC_INST_VPKSHUS:
|
||||
case PPC_INST_VREFP:
|
||||
case PPC_INST_VREFP128:
|
||||
case PPC_INST_VRFIM128:
|
||||
case PPC_INST_VRFIN:
|
||||
case PPC_INST_VRFIN128:
|
||||
case PPC_INST_VRFIZ128:
|
||||
case PPC_INST_VRLIMI128:
|
||||
case PPC_INST_VRSQRTEFP:
|
||||
case PPC_INST_VRSQRTEFP128:
|
||||
case PPC_INST_VSEL:
|
||||
case PPC_INST_VSLB:
|
||||
case PPC_INST_VSLDOI:
|
||||
case PPC_INST_VSLDOI128:
|
||||
case PPC_INST_VSLW128:
|
||||
case PPC_INST_VSPLTH:
|
||||
case PPC_INST_VSPLTISB:
|
||||
case PPC_INST_VSPLTISW:
|
||||
case PPC_INST_VSPLTISW128:
|
||||
case PPC_INST_VSPLTW:
|
||||
case PPC_INST_VSPLTW128:
|
||||
case PPC_INST_VSR:
|
||||
case PPC_INST_VSRAW128:
|
||||
case PPC_INST_VSRW:
|
||||
case PPC_INST_VSRW128:
|
||||
case PPC_INST_VSUBFP:
|
||||
case PPC_INST_VSUBFP128:
|
||||
case PPC_INST_VSUBSWS:
|
||||
case PPC_INST_VSUBUBS:
|
||||
case PPC_INST_VSUBUHM:
|
||||
case PPC_INST_VUPKD3D128:
|
||||
case PPC_INST_VUPKHSB128:
|
||||
case PPC_INST_VUPKHSH:
|
||||
case PPC_INST_VUPKLSB128:
|
||||
case PPC_INST_VUPKLSH:
|
||||
case PPC_INST_VXOR:
|
||||
case PPC_INST_VXOR128:
|
||||
break;
|
||||
|
||||
case PPC_INST_XOR:
|
||||
// TODO: . variant
|
||||
std::println(f, "\tctx.r{}.u64 = ctx.r{}.u64 ^ ctx.r{}.u64;", insn.operands[0], insn.operands[1], insn.operands[2]);
|
||||
break;
|
||||
|
||||
case PPC_INST_XORI:
|
||||
std::println(f, "\tctx.r{}.u64 = ctx.r{}.u64 ^ {};", insn.operands[0], insn.operands[1], insn.operands[2]);
|
||||
break;
|
||||
|
||||
case PPC_INST_XORIS:
|
||||
std::println(f, "\tctx.r{}.u64 = ctx.r{}.u64 ^ {};", insn.operands[0], insn.operands[1], insn.operands[2] << 16);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,18 +1,285 @@
|
||||
#pragma once
|
||||
#include <cstdint>
|
||||
#include <cstdlib>
|
||||
|
||||
#ifdef __clang__
|
||||
#define __restrict __restrict__
|
||||
#define _byteswap_ushort __builtin_bswap16
|
||||
#define _byteswap_ulong __builtin_bswap32
|
||||
#define _byteswap_uint64 __builtin_bswap64
|
||||
#endif
|
||||
|
||||
#define PPC_LOAD_U8(x) *(uint8_t*)(base + (x))
|
||||
#define PPC_LOAD_U16(x) _byteswap_ushort(*(uint16_t*)(base + (x)))
|
||||
#define PPC_LOAD_U32(x) _byteswap_ulong(*(uint32_t*)(base + (x)))
|
||||
#define PPC_LOAD_U64(x) _byteswap_uint64(*(uint64_t*)(base + (x)))
|
||||
|
||||
#define PPC_STORE_U8(x, y) *(uint8_t*)(base + (x)) = (y)
|
||||
#define PPC_STORE_U16(x, y) *(uint16_t*)(base + (x)) = _byteswap_ushort(y)
|
||||
#define PPC_STORE_U32(x, y) *(uint32_t*)(base + (x)) = _byteswap_ulong(y)
|
||||
#define PPC_STORE_U64(x, y) *(uint64_t*)(base + (x)) = _byteswap_uint64(y)
|
||||
|
||||
struct PPCRegister
|
||||
{
|
||||
union
|
||||
{
|
||||
int8_t s8;
|
||||
uint8_t u8;
|
||||
int16_t s16;
|
||||
uint16_t u16;
|
||||
int32_t s32;
|
||||
uint32_t u32;
|
||||
int64_t s64;
|
||||
uint64_t u64;
|
||||
float f32;
|
||||
double f64;
|
||||
};
|
||||
};
|
||||
|
||||
struct PPCCRRegister
|
||||
{
|
||||
uint8_t lt;
|
||||
uint8_t gt;
|
||||
uint8_t eq;
|
||||
uint8_t so;
|
||||
};
|
||||
|
||||
typedef float float128[4];
|
||||
|
||||
struct PPCContext
|
||||
{
|
||||
uint64_t iar;
|
||||
uint64_t lr;
|
||||
uint64_t ctr;
|
||||
|
||||
uint32_t xer;
|
||||
uint32_t cr[8];
|
||||
uint32_t fpcsr;
|
||||
uint64_t gpr[32];
|
||||
double fpr[32];
|
||||
float128 vpr[128];
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
PPCCRRegister cr0;
|
||||
PPCCRRegister cr1;
|
||||
PPCCRRegister cr2;
|
||||
PPCCRRegister cr3;
|
||||
PPCCRRegister cr4;
|
||||
PPCCRRegister cr5;
|
||||
PPCCRRegister cr6;
|
||||
PPCCRRegister cr7;
|
||||
};
|
||||
PPCCRRegister cr[8];
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
PPCRegister r0;
|
||||
PPCRegister r1;
|
||||
PPCRegister r2;
|
||||
PPCRegister r3;
|
||||
PPCRegister r4;
|
||||
PPCRegister r5;
|
||||
PPCRegister r6;
|
||||
PPCRegister r7;
|
||||
PPCRegister r8;
|
||||
PPCRegister r9;
|
||||
PPCRegister r10;
|
||||
PPCRegister r11;
|
||||
PPCRegister r12;
|
||||
PPCRegister r13;
|
||||
PPCRegister r14;
|
||||
PPCRegister r15;
|
||||
PPCRegister r16;
|
||||
PPCRegister r17;
|
||||
PPCRegister r18;
|
||||
PPCRegister r19;
|
||||
PPCRegister r20;
|
||||
PPCRegister r21;
|
||||
PPCRegister r22;
|
||||
PPCRegister r23;
|
||||
PPCRegister r24;
|
||||
PPCRegister r25;
|
||||
PPCRegister r26;
|
||||
PPCRegister r27;
|
||||
PPCRegister r28;
|
||||
PPCRegister r29;
|
||||
PPCRegister r30;
|
||||
PPCRegister r31;
|
||||
};
|
||||
PPCRegister r[32];
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
PPCRegister f0;
|
||||
PPCRegister f1;
|
||||
PPCRegister f2;
|
||||
PPCRegister f3;
|
||||
PPCRegister f4;
|
||||
PPCRegister f5;
|
||||
PPCRegister f6;
|
||||
PPCRegister f7;
|
||||
PPCRegister f8;
|
||||
PPCRegister f9;
|
||||
PPCRegister f10;
|
||||
PPCRegister f11;
|
||||
PPCRegister f12;
|
||||
PPCRegister f13;
|
||||
PPCRegister f14;
|
||||
PPCRegister f15;
|
||||
PPCRegister f16;
|
||||
PPCRegister f17;
|
||||
PPCRegister f18;
|
||||
PPCRegister f19;
|
||||
PPCRegister f20;
|
||||
PPCRegister f21;
|
||||
PPCRegister f22;
|
||||
PPCRegister f23;
|
||||
PPCRegister f24;
|
||||
PPCRegister f25;
|
||||
PPCRegister f26;
|
||||
PPCRegister f27;
|
||||
PPCRegister f28;
|
||||
PPCRegister f29;
|
||||
PPCRegister f30;
|
||||
PPCRegister f31;
|
||||
};
|
||||
PPCRegister f[32];
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
float128 v0;
|
||||
float128 v1;
|
||||
float128 v2;
|
||||
float128 v3;
|
||||
float128 v4;
|
||||
float128 v5;
|
||||
float128 v6;
|
||||
float128 v7;
|
||||
float128 v8;
|
||||
float128 v9;
|
||||
float128 v10;
|
||||
float128 v11;
|
||||
float128 v12;
|
||||
float128 v13;
|
||||
float128 v14;
|
||||
float128 v15;
|
||||
float128 v16;
|
||||
float128 v17;
|
||||
float128 v18;
|
||||
float128 v19;
|
||||
float128 v20;
|
||||
float128 v21;
|
||||
float128 v22;
|
||||
float128 v23;
|
||||
float128 v24;
|
||||
float128 v25;
|
||||
float128 v26;
|
||||
float128 v27;
|
||||
float128 v28;
|
||||
float128 v29;
|
||||
float128 v30;
|
||||
float128 v31;
|
||||
float128 v32;
|
||||
float128 v33;
|
||||
float128 v34;
|
||||
float128 v35;
|
||||
float128 v36;
|
||||
float128 v37;
|
||||
float128 v38;
|
||||
float128 v39;
|
||||
float128 v40;
|
||||
float128 v41;
|
||||
float128 v42;
|
||||
float128 v43;
|
||||
float128 v44;
|
||||
float128 v45;
|
||||
float128 v46;
|
||||
float128 v47;
|
||||
float128 v48;
|
||||
float128 v49;
|
||||
float128 v50;
|
||||
float128 v51;
|
||||
float128 v52;
|
||||
float128 v53;
|
||||
float128 v54;
|
||||
float128 v55;
|
||||
float128 v56;
|
||||
float128 v57;
|
||||
float128 v58;
|
||||
float128 v59;
|
||||
float128 v60;
|
||||
float128 v61;
|
||||
float128 v62;
|
||||
float128 v63;
|
||||
float128 v64;
|
||||
float128 v65;
|
||||
float128 v66;
|
||||
float128 v67;
|
||||
float128 v68;
|
||||
float128 v69;
|
||||
float128 v70;
|
||||
float128 v71;
|
||||
float128 v72;
|
||||
float128 v73;
|
||||
float128 v74;
|
||||
float128 v75;
|
||||
float128 v76;
|
||||
float128 v77;
|
||||
float128 v78;
|
||||
float128 v79;
|
||||
float128 v80;
|
||||
float128 v81;
|
||||
float128 v82;
|
||||
float128 v83;
|
||||
float128 v84;
|
||||
float128 v85;
|
||||
float128 v86;
|
||||
float128 v87;
|
||||
float128 v88;
|
||||
float128 v89;
|
||||
float128 v90;
|
||||
float128 v91;
|
||||
float128 v92;
|
||||
float128 v93;
|
||||
float128 v94;
|
||||
float128 v95;
|
||||
float128 v96;
|
||||
float128 v97;
|
||||
float128 v98;
|
||||
float128 v99;
|
||||
float128 v100;
|
||||
float128 v101;
|
||||
float128 v102;
|
||||
float128 v103;
|
||||
float128 v104;
|
||||
float128 v105;
|
||||
float128 v106;
|
||||
float128 v107;
|
||||
float128 v108;
|
||||
float128 v109;
|
||||
float128 v110;
|
||||
float128 v111;
|
||||
float128 v112;
|
||||
float128 v113;
|
||||
float128 v114;
|
||||
float128 v115;
|
||||
float128 v116;
|
||||
float128 v117;
|
||||
float128 v118;
|
||||
float128 v119;
|
||||
float128 v120;
|
||||
float128 v121;
|
||||
float128 v122;
|
||||
float128 v123;
|
||||
float128 v124;
|
||||
float128 v125;
|
||||
float128 v126;
|
||||
float128 v127;
|
||||
};
|
||||
float128 v[128];
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user