mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
Fix missing defines, don’t use native aliases
Signed-off-by: Isaac Marovitz <isaacryu@icloud.com>
This commit is contained in:
Isaac Marovitz
parent
5d500f26e7
commit
d1d8b9e597
@ -12,10 +12,15 @@
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#include <cstdlib>
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#include <cstring>
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#define SIMDE_ENABLE_NATIVE_ALIASES
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#include <x86/avx.h>
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#include <x86/sse.h>
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#include <x86/sse4.1.h>
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// SSE3 constants are missing from simde
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#ifndef _MM_DENORMALS_ZERO_MASK
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#define _MM_DENORMALS_ZERO_MASK 0x0040
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#endif
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#define PPC_JOIN(x, y) x##y
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#define PPC_XSTRINGIFY(x) #x
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#define PPC_STRINGIFY(x) PPC_XSTRINGIFY(x)
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@ -170,18 +175,18 @@ struct PPCCRRegister
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eq = !un && (left == right);
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}
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inline void setFromMask(__m128 mask, int imm) noexcept
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inline void setFromMask(simde__m128 mask, int imm) noexcept
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{
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int m = _mm_movemask_ps(mask);
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int m = simde_mm_movemask_ps(mask);
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lt = m == imm; // all equal
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gt = 0;
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eq = m == 0; // none equal
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so = 0;
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}
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inline void setFromMask(__m128i mask, int imm) noexcept
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inline void setFromMask(simde__m128i mask, int imm) noexcept
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{
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int m = _mm_movemask_epi8(mask);
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int m = simde_mm_movemask_epi8(mask);
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lt = m == imm; // all equal
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gt = 0;
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eq = m == 0; // none equal
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@ -216,34 +221,34 @@ struct PPCFPSCRRegister
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{
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uint32_t csr;
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static constexpr size_t GuestToHost[] = { _MM_ROUND_NEAREST, _MM_ROUND_TOWARD_ZERO, _MM_ROUND_UP, _MM_ROUND_DOWN };
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static constexpr size_t GuestToHost[] = { SIMDE_MM_ROUND_NEAREST, SIMDE_MM_ROUND_TOWARD_ZERO, SIMDE_MM_ROUND_UP, SIMDE_MM_ROUND_DOWN };
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static constexpr size_t HostToGuest[] = { PPC_ROUND_NEAREST, PPC_ROUND_DOWN, PPC_ROUND_UP, PPC_ROUND_TOWARD_ZERO };
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inline uint32_t loadFromHost() noexcept
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{
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csr = _mm_getcsr();
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return HostToGuest[(csr & _MM_ROUND_MASK) >> 13];
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csr = simde_mm_getcsr();
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return HostToGuest[(csr & SIMDE_MM_ROUND_MASK) >> 13];
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}
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inline void storeFromGuest(uint32_t value) noexcept
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{
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csr &= ~_MM_ROUND_MASK;
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csr &= ~SIMDE_MM_ROUND_MASK;
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csr |= GuestToHost[value & PPC_ROUND_MASK];
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_mm_setcsr(csr);
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simde_mm_setcsr(csr);
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}
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static constexpr size_t FlushMask = _MM_FLUSH_ZERO_MASK | _MM_DENORMALS_ZERO_MASK;
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static constexpr size_t FlushMask = SIMDE_MM_FLUSH_ZERO_MASK | _MM_DENORMALS_ZERO_MASK;
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inline void enableFlushModeUnconditional() noexcept
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{
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csr |= FlushMask;
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_mm_setcsr(csr);
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simde_mm_setcsr(csr);
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}
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inline void disableFlushModeUnconditional() noexcept
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{
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csr &= ~FlushMask;
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_mm_setcsr(csr);
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simde_mm_setcsr(csr);
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}
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inline void enableFlushMode() noexcept
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@ -251,7 +256,7 @@ struct PPCFPSCRRegister
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if ((csr & FlushMask) != FlushMask) [[unlikely]]
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{
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csr |= FlushMask;
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_mm_setcsr(csr);
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simde_mm_setcsr(csr);
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}
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}
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@ -260,7 +265,7 @@ struct PPCFPSCRRegister
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if ((csr & FlushMask) != 0) [[unlikely]]
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{
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csr &= ~FlushMask;
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_mm_setcsr(csr);
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simde_mm_setcsr(csr);
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}
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}
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};
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@ -588,68 +593,68 @@ inline uint8_t VectorShiftTableR[] =
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0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
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};
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inline __m128i _mm_adds_epu32(__m128i a, __m128i b)
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inline simde__m128i _mm_adds_epu32(simde__m128i a, simde__m128i b)
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{
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return _mm_add_epi32(a, _mm_min_epu32(_mm_xor_si128(a, _mm_cmpeq_epi32(a, a)), b));
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return simde_mm_add_epi32(a, simde_mm_min_epu32(simde_mm_xor_si128(a, simde_mm_cmpeq_epi32(a, a)), b));
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}
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inline __m128i _mm_avg_epi8(__m128i a, __m128i b)
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inline simde__m128i _mm_avg_epi8(simde__m128i a, simde__m128i b)
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{
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__m128i c = _mm_set1_epi8(char(128));
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return _mm_xor_si128(c, _mm_avg_epu8(_mm_xor_si128(c, a), _mm_xor_si128(c, b)));
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simde__m128i c = simde_mm_set1_epi8(char(128));
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return simde_mm_xor_si128(c, simde_mm_avg_epu8(simde_mm_xor_si128(c, a), simde_mm_xor_si128(c, b)));
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}
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inline __m128i _mm_avg_epi16(__m128i a, __m128i b)
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inline simde__m128i _mm_avg_epi16(simde__m128i a, simde__m128i b)
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{
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__m128i c = _mm_set1_epi16(short(32768));
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return _mm_xor_si128(c, _mm_avg_epu16(_mm_xor_si128(c, a), _mm_xor_si128(c, b)));
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simde__m128i c = simde_mm_set1_epi16(short(32768));
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return simde_mm_xor_si128(c, simde_mm_avg_epu16(simde_mm_xor_si128(c, a), simde_mm_xor_si128(c, b)));
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}
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inline __m128 _mm_cvtepu32_ps_(__m128i src1)
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inline simde__m128 _mm_cvtepu32_ps_(simde__m128i src1)
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{
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__m128i xmm1 = _mm_add_epi32(src1, _mm_set1_epi32(127));
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__m128i xmm0 = _mm_slli_epi32(src1, 31 - 8);
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xmm0 = _mm_srli_epi32(xmm0, 31);
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xmm0 = _mm_add_epi32(xmm0, xmm1);
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xmm0 = _mm_srai_epi32(xmm0, 8);
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xmm0 = _mm_add_epi32(xmm0, _mm_set1_epi32(0x4F800000));
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__m128 xmm2 = _mm_cvtepi32_ps(src1);
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return _mm_blendv_ps(xmm2, _mm_castsi128_ps(xmm0), _mm_castsi128_ps(src1));
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simde__m128i xmm1 = simde_mm_add_epi32(src1, simde_mm_set1_epi32(127));
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simde__m128i xmm0 = simde_mm_slli_epi32(src1, 31 - 8);
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xmm0 = simde_mm_srli_epi32(xmm0, 31);
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xmm0 = simde_mm_add_epi32(xmm0, xmm1);
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xmm0 = simde_mm_srai_epi32(xmm0, 8);
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xmm0 = simde_mm_add_epi32(xmm0, simde_mm_set1_epi32(0x4F800000));
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simde__m128 xmm2 = simde_mm_cvtepi32_ps(src1);
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return simde_mm_blendv_ps(xmm2, simde_mm_castsi128_ps(xmm0), simde_mm_castsi128_ps(src1));
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}
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inline __m128i _mm_perm_epi8_(__m128i a, __m128i b, __m128i c)
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inline simde__m128i _mm_perm_epi8_(simde__m128i a, simde__m128i b, simde__m128i c)
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{
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__m128i d = _mm_set1_epi8(0xF);
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__m128i e = _mm_sub_epi8(d, _mm_and_si128(c, d));
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return _mm_blendv_epi8(_mm_shuffle_epi8(a, e), _mm_shuffle_epi8(b, e), _mm_slli_epi32(c, 3));
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simde__m128i d = simde_mm_set1_epi8(0xF);
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simde__m128i e = simde_mm_sub_epi8(d, simde_mm_and_si128(c, d));
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return simde_mm_blendv_epi8(simde_mm_shuffle_epi8(a, e), simde_mm_shuffle_epi8(b, e), simde_mm_slli_epi32(c, 3));
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}
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inline __m128i _mm_cmpgt_epu8(__m128i a, __m128i b)
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inline simde__m128i _mm_cmpgt_epu8(simde__m128i a, simde__m128i b)
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{
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__m128i c = _mm_set1_epi8(char(128));
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return _mm_cmpgt_epi8(_mm_xor_si128(a, c), _mm_xor_si128(b, c));
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simde__m128i c = simde_mm_set1_epi8(char(128));
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return simde_mm_cmpgt_epi8(simde_mm_xor_si128(a, c), simde_mm_xor_si128(b, c));
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}
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inline __m128i _mm_cmpgt_epu16(__m128i a, __m128i b)
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inline simde__m128i _mm_cmpgt_epu16(simde__m128i a, simde__m128i b)
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{
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__m128i c = _mm_set1_epi16(short(32768));
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return _mm_cmpgt_epi16(_mm_xor_si128(a, c), _mm_xor_si128(b, c));
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simde__m128i c = simde_mm_set1_epi16(short(32768));
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return simde_mm_cmpgt_epi16(simde_mm_xor_si128(a, c), simde_mm_xor_si128(b, c));
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}
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inline __m128i _mm_vctsxs(__m128 src1)
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inline simde__m128i _mm_vctsxs(simde__m128 src1)
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{
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__m128 xmm2 = _mm_cmpunord_ps(src1, src1);
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__m128i xmm0 = _mm_cvttps_epi32(src1);
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__m128i xmm1 = _mm_cmpeq_epi32(xmm0, _mm_set1_epi32(INT_MIN));
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xmm1 = _mm_andnot_si128(_mm_castps_si128(src1), xmm1);
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__m128 dest = _mm_blendv_ps(_mm_castsi128_ps(xmm0), _mm_castsi128_ps(_mm_set1_epi32(INT_MAX)), _mm_castsi128_ps(xmm1));
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return _mm_andnot_si128(_mm_castps_si128(xmm2), _mm_castps_si128(dest));
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simde__m128 xmm2 = simde_mm_cmpunord_ps(src1, src1);
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simde__m128i xmm0 = simde_mm_cvttps_epi32(src1);
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simde__m128i xmm1 = simde_mm_cmpeq_epi32(xmm0, simde_mm_set1_epi32(INT_MIN));
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xmm1 = simde_mm_andnot_si128(simde_mm_castps_si128(src1), xmm1);
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simde__m128 dest = simde_mm_blendv_ps(simde_mm_castsi128_ps(xmm0), simde_mm_castsi128_ps(simde_mm_set1_epi32(INT_MAX)), simde_mm_castsi128_ps(xmm1));
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return simde_mm_andnot_si128(simde_mm_castps_si128(xmm2), simde_mm_castps_si128(dest));
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}
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inline __m128i _mm_vsr(__m128i a, __m128i b)
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inline simde__m128i _mm_vsr(simde__m128i a, simde__m128i b)
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{
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b = _mm_srli_epi64(_mm_slli_epi64(b, 61), 61);
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return _mm_castps_si128(_mm_insert_ps(_mm_castsi128_ps(_mm_srl_epi64(a, b)), _mm_castsi128_ps(_mm_srl_epi64(_mm_srli_si128(a, 4), b)), 0x10));
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b = simde_mm_srli_epi64(simde_mm_slli_epi64(b, 61), 61);
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return simde_mm_castps_si128(simde_mm_insert_ps(simde_mm_castsi128_ps(simde_mm_srl_epi64(a, b)), simde_mm_castsi128_ps(simde_mm_srl_epi64(simde_mm_srli_si128(a, 4), b)), 0x10));
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}
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#endif
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