mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-03 15:52:05 +00:00
Implement even more vector instructions & add missing ones.
This commit is contained in:
Skyth
parent
3a887e6e2c
commit
ee4cab12b8
@ -1246,11 +1246,11 @@ int main()
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break;
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case PPC_INST_VAVGSB:
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// TODO: no _mm_avg_epi8
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_avg_epi8(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VAVGSH:
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// TODO: no _mm_avg_epi16
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_avg_epi16(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VAVGUB:
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@ -1266,6 +1266,8 @@ int main()
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break;
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case PPC_INST_VCFUX:
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// NOTE: ignoring the immediate since it's always 0 in the game code
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_cvtepu32_ps(_mm_load_si128((__m128i*)ctx.v{}.u32)));", insn.operands[0], insn.operands[1]);
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break;
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case PPC_INST_VCMPBFP128:
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@ -1279,10 +1281,20 @@ int main()
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case PPC_INST_VCMPEQUB:
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case PPC_INST_VCMPEQUW:
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case PPC_INST_VCMPEQUW128:
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break;
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case PPC_INST_VCMPGEFP:
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case PPC_INST_VCMPGEFP128:
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// TODO: . variant
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_cmpge_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VCMPGTFP:
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case PPC_INST_VCMPGTFP128:
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// TODO: . variant
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_cmpgt_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VCMPGTUB:
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case PPC_INST_VCMPGTUH:
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case PPC_INST_VCSXWFP128:
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@ -1291,13 +1303,15 @@ int main()
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break;
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case PPC_INST_VEXPTEFP128:
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// TODO: this doesn't exist despite being documented?
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//println("\t_mm_store_ps(ctx.v{}.f32, _mm_exp2_ps(_mm_load_ps(ctx.v{}.f32)));", insn.operands[0], insn.operands[1]);
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// TODO: vectorize
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for (size_t i = 0; i < 4; i++)
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println("\tctx.v{}.f32[{}] = exp2f(ctx.v{}.f32[{}]);", insn.operands[0], i, insn.operands[1], i);
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break;
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case PPC_INST_VLOGEFP128:
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// TODO: this doesn't exist despite being documented?
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//println("\t_mm_store_ps(ctx.v{}.f32, _mm_log2_ps(_mm_load_ps(ctx.v{}.f32)));", insn.operands[0], insn.operands[1]);
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// TODO: vectorize
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for (size_t i = 0; i < 4; i++)
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println("\tctx.v{}.f32[{}] = log2f(ctx.v{}.f32[{}]);", insn.operands[0], i, insn.operands[1], i);
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break;
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case PPC_INST_VMADDCFP128:
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@ -1415,8 +1429,13 @@ int main()
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break;
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case PPC_INST_VSLB:
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break;
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case PPC_INST_VSLDOI:
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case PPC_INST_VSLDOI128:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_alignr_epi8(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8), {}));", insn.operands[0], insn.operands[1], insn.operands[2], 16 - insn.operands[3]);
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break;
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case PPC_INST_VSLW128:
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case PPC_INST_VSPLTH:
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case PPC_INST_VSPLTISB:
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@ -1436,13 +1455,35 @@ int main()
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break;
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case PPC_INST_VSUBSWS:
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break;
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case PPC_INST_VSUBUBS:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_subs_epu8(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VSUBUHM:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_sub_epi16(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VUPKD3D128:
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break;
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case PPC_INST_VUPKHSB128:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.s16, _mm_cvtepi8_epi16(_mm_unpackhi_epi64(_mm_load_si128((__m128i*)ctx.v{}.s8), _mm_load_si128((__m128i*)ctx.v{}.s8))));", insn.operands[0], insn.operands[1], insn.operands[1]);
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break;
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case PPC_INST_VUPKHSH:
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case PPC_INST_VUPKHSH128:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.s32, _mm_cvtepi16_epi32(_mm_unpackhi_epi64(_mm_load_si128((__m128i*)ctx.v{}.s16), _mm_load_si128((__m128i*)ctx.v{}.s16))));", insn.operands[0], insn.operands[1], insn.operands[1]);
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break;
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case PPC_INST_VUPKLSB128:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.s32, _mm_cvtepi8_epi16(_mm_load_si128((__m128i*)ctx.v{}.s16)));", insn.operands[0], insn.operands[1]);
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break;
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case PPC_INST_VUPKLSH:
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case PPC_INST_VUPKLSH128:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.s32, _mm_cvtepi16_epi32(_mm_load_si128((__m128i*)ctx.v{}.s16)));", insn.operands[0], insn.operands[1]);
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break;
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case PPC_INST_VXOR:
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@ -346,3 +346,24 @@ inline __m128i _mm_adds_epu32(__m128i a, __m128i b)
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{
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return _mm_add_epi32(_mm_min_epu32(a, _mm_xor_si128(b, _mm_cmpeq_epi32(b, b))), b);
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}
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inline __m128i _mm_avg_epi8(__m128i a, __m128i b)
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{
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__m128i c = _mm_set1_epi8(char(128));
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return _mm_add_epi8(c, _mm_avg_epu8(_mm_add_epi8(c, a), _mm_add_epi8(c, b)));
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}
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inline __m128i _mm_avg_epi16(__m128i a, __m128i b)
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{
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__m128i c = _mm_set1_epi16(short(32768));
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return _mm_add_epi16(c, _mm_avg_epu16(_mm_add_epi16(c, a), _mm_add_epi16(c, b)));
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}
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inline __m128 _mm_cvtepu32_ps(__m128i v)
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{
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__m128i v2 = _mm_srli_epi32(v, 1);
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__m128i v1 = _mm_sub_epi32(v, v2);
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__m128 v2f = _mm_cvtepi32_ps(v2);
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__m128 v1f = _mm_cvtepi32_ps(v1);
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return _mm_add_ps(v2f, v1f);
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}
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6
thirdparty/disasm/ppc-dis.c
vendored
6
thirdparty/disasm/ppc-dis.c
vendored
@ -1825,10 +1825,10 @@ extract_vperm (unsigned long insn,
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#define VXR_MASK VXR(0x3f, 0x3ff, 1)
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/* An VX128 form instruction. */
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#define VX128(op, xop) (OP(op) | (((unsigned long)(xop)) & 0x3d0))
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#define VX128(op, xop) (OP(op) | (((unsigned long)(xop)) & 0x7d0))
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/* The mask for an VX form instruction. */
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#define VX128_MASK VX(0x3f, 0x3d0)
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#define VX128_MASK VX(0x3f, 0x7d0)
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/* An VX128 form instruction. */
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#define VX128_1(op, xop) (OP(op) | (((unsigned long)(xop)) & 0x7f3))
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@ -2543,6 +2543,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "vmrglw128", VX128(6, 832), VX128_MASK, PPCVEC128, { VD128, VA128, VB128 }, PPC_INST_VMRGLW128 },
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{ "vupkhsb128", VX128(6, 896), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKHSB128 },
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{ "vupklsb128", VX128(6, 960), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKLSB128 },
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{ "vupkhsh128", VX128(6, 1952), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKHSH128 },
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{ "vupklsh128", VX128(6, 2016), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKLSH128 },
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{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVADDW },
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2
thirdparty/disasm/ppc-inst.h
vendored
2
thirdparty/disasm/ppc-inst.h
vendored
@ -1844,3 +1844,5 @@
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#define PPC_INST_DENBCDQ 1842
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#define PPC_INST_FCFID 1843
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#define PPC_INST_DIEXQ 1844
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#define PPC_INST_VUPKHSH128 1845
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#define PPC_INST_VUPKLSH128 1846
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