test_cases:
  -
    input:
      bytes: [ 0x00, 0x20, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, TTBR0_EL1"

  -
    input:
      bytes: [ 0x20, 0x20, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, TTBR1_EL1"

  -
    input:
      bytes: [ 0x00, 0x74, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, PAR_EL1"

  -
    input:
      bytes: [ 0x60, 0xd0, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, RCWSMASK_EL1"

  -
    input:
      bytes: [ 0xc0, 0xd0, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, RCWMASK_EL1"

  -
    input:
      bytes: [ 0x00, 0x20, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, TTBR0_EL2"

  -
    input:
      bytes: [ 0x20, 0x20, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, TTBR1_EL2"

  -
    input:
      bytes: [ 0x00, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, VTTBR_EL2"

  -
    input:
      bytes: [ 0x00, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, VTTBR_EL2"

  -
    input:
      bytes: [ 0x02, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x2, x3, VTTBR_EL2"

  -
    input:
      bytes: [ 0x04, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x4, x5, VTTBR_EL2"

  -
    input:
      bytes: [ 0x06, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x6, x7, VTTBR_EL2"

  -
    input:
      bytes: [ 0x08, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x8, x9, VTTBR_EL2"

  -
    input:
      bytes: [ 0x0a, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x10, x11, VTTBR_EL2"

  -
    input:
      bytes: [ 0x0c, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x12, x13, VTTBR_EL2"

  -
    input:
      bytes: [ 0x0e, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x14, x15, VTTBR_EL2"

  -
    input:
      bytes: [ 0x10, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x16, x17, VTTBR_EL2"

  -
    input:
      bytes: [ 0x12, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x18, x19, VTTBR_EL2"

  -
    input:
      bytes: [ 0x14, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x20, x21, VTTBR_EL2"

  -
    input:
      bytes: [ 0x16, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x22, x23, VTTBR_EL2"

  -
    input:
      bytes: [ 0x18, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x24, x25, VTTBR_EL2"

  -
    input:
      bytes: [ 0x1a, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "mrrs x26, x27, VTTBR_EL2"

  -
    input:
      bytes: [ 0x00, 0x20, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr TTBR0_EL1, x0, x1"

  -
    input:
      bytes: [ 0x20, 0x20, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr TTBR1_EL1, x0, x1"

  -
    input:
      bytes: [ 0x00, 0x74, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr PAR_EL1, x0, x1"

  -
    input:
      bytes: [ 0x60, 0xd0, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr RCWSMASK_EL1, x0, x1"

  -
    input:
      bytes: [ 0xc0, 0xd0, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr RCWMASK_EL1, x0, x1"

  -
    input:
      bytes: [ 0x00, 0x20, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr TTBR0_EL2, x0, x1"

  -
    input:
      bytes: [ 0x20, 0x20, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr TTBR1_EL2, x0, x1"

  -
    input:
      bytes: [ 0x00, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x0, x1"

  -
    input:
      bytes: [ 0x00, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x0, x1"

  -
    input:
      bytes: [ 0x02, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x2, x3"

  -
    input:
      bytes: [ 0x04, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x4, x5"

  -
    input:
      bytes: [ 0x06, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x6, x7"

  -
    input:
      bytes: [ 0x08, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x8, x9"

  -
    input:
      bytes: [ 0x0a, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x10, x11"

  -
    input:
      bytes: [ 0x0c, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x12, x13"

  -
    input:
      bytes: [ 0x0e, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x14, x15"

  -
    input:
      bytes: [ 0x10, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x16, x17"

  -
    input:
      bytes: [ 0x12, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x18, x19"

  -
    input:
      bytes: [ 0x14, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x20, x21"

  -
    input:
      bytes: [ 0x16, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x22, x23"

  -
    input:
      bytes: [ 0x18, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x24, x25"

  -
    input:
      bytes: [ 0x1a, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x26, x27"

  -
    input:
      bytes: [ 0x00, 0x20, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, TTBR0_EL1"

  -
    input:
      bytes: [ 0x20, 0x20, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, TTBR1_EL1"

  -
    input:
      bytes: [ 0x00, 0x74, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, PAR_EL1"

  -
    input:
      bytes: [ 0x60, 0xd0, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, RCWSMASK_EL1"

  -
    input:
      bytes: [ 0xc0, 0xd0, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, RCWMASK_EL1"

  -
    input:
      bytes: [ 0x00, 0x20, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, TTBR0_EL2"

  -
    input:
      bytes: [ 0x20, 0x20, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, TTBR1_EL2"

  -
    input:
      bytes: [ 0x00, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, VTTBR_EL2"

  -
    input:
      bytes: [ 0x00, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, VTTBR_EL2"

  -
    input:
      bytes: [ 0x02, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x2, x3, VTTBR_EL2"

  -
    input:
      bytes: [ 0x04, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x4, x5, VTTBR_EL2"

  -
    input:
      bytes: [ 0x06, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x6, x7, VTTBR_EL2"

  -
    input:
      bytes: [ 0x08, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x8, x9, VTTBR_EL2"

  -
    input:
      bytes: [ 0x0a, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x10, x11, VTTBR_EL2"

  -
    input:
      bytes: [ 0x0c, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x12, x13, VTTBR_EL2"

  -
    input:
      bytes: [ 0x0e, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x14, x15, VTTBR_EL2"

  -
    input:
      bytes: [ 0x10, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x16, x17, VTTBR_EL2"

  -
    input:
      bytes: [ 0x12, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x18, x19, VTTBR_EL2"

  -
    input:
      bytes: [ 0x14, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x20, x21, VTTBR_EL2"

  -
    input:
      bytes: [ 0x16, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x22, x23, VTTBR_EL2"

  -
    input:
      bytes: [ 0x18, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x24, x25, VTTBR_EL2"

  -
    input:
      bytes: [ 0x1a, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "mrrs x26, x27, VTTBR_EL2"

  -
    input:
      bytes: [ 0x00, 0x20, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr TTBR0_EL1, x0, x1"

  -
    input:
      bytes: [ 0x20, 0x20, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr TTBR1_EL1, x0, x1"

  -
    input:
      bytes: [ 0x00, 0x74, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr PAR_EL1, x0, x1"

  -
    input:
      bytes: [ 0x60, 0xd0, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr RCWSMASK_EL1, x0, x1"

  -
    input:
      bytes: [ 0xc0, 0xd0, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr RCWMASK_EL1, x0, x1"

  -
    input:
      bytes: [ 0x00, 0x20, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr TTBR0_EL2, x0, x1"

  -
    input:
      bytes: [ 0x20, 0x20, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr TTBR1_EL2, x0, x1"

  -
    input:
      bytes: [ 0x00, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x0, x1"

  -
    input:
      bytes: [ 0x00, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x0, x1"

  -
    input:
      bytes: [ 0x02, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x2, x3"

  -
    input:
      bytes: [ 0x04, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x4, x5"

  -
    input:
      bytes: [ 0x06, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x6, x7"

  -
    input:
      bytes: [ 0x08, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x8, x9"

  -
    input:
      bytes: [ 0x0a, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x10, x11"

  -
    input:
      bytes: [ 0x0c, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x12, x13"

  -
    input:
      bytes: [ 0x0e, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x14, x15"

  -
    input:
      bytes: [ 0x10, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x16, x17"

  -
    input:
      bytes: [ 0x12, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x18, x19"

  -
    input:
      bytes: [ 0x14, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x20, x21"

  -
    input:
      bytes: [ 0x16, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x22, x23"

  -
    input:
      bytes: [ 0x18, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x24, x25"

  -
    input:
      bytes: [ 0x1a, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x26, x27"

  -
    input:
      bytes: [ 0x00, 0x20, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, TTBR0_EL1"

  -
    input:
      bytes: [ 0x20, 0x20, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, TTBR1_EL1"

  -
    input:
      bytes: [ 0x00, 0x74, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, PAR_EL1"

  -
    input:
      bytes: [ 0x60, 0xd0, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, RCWSMASK_EL1"

  -
    input:
      bytes: [ 0xc0, 0xd0, 0x78, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, RCWMASK_EL1"

  -
    input:
      bytes: [ 0x00, 0x20, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, TTBR0_EL2"

  -
    input:
      bytes: [ 0x20, 0x20, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, TTBR1_EL2"

  -
    input:
      bytes: [ 0x00, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, VTTBR_EL2"

  -
    input:
      bytes: [ 0x00, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x0, x1, VTTBR_EL2"

  -
    input:
      bytes: [ 0x02, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x2, x3, VTTBR_EL2"

  -
    input:
      bytes: [ 0x04, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x4, x5, VTTBR_EL2"

  -
    input:
      bytes: [ 0x06, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x6, x7, VTTBR_EL2"

  -
    input:
      bytes: [ 0x08, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x8, x9, VTTBR_EL2"

  -
    input:
      bytes: [ 0x0a, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x10, x11, VTTBR_EL2"

  -
    input:
      bytes: [ 0x0c, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x12, x13, VTTBR_EL2"

  -
    input:
      bytes: [ 0x0e, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x14, x15, VTTBR_EL2"

  -
    input:
      bytes: [ 0x10, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x16, x17, VTTBR_EL2"

  -
    input:
      bytes: [ 0x12, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x18, x19, VTTBR_EL2"

  -
    input:
      bytes: [ 0x14, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x20, x21, VTTBR_EL2"

  -
    input:
      bytes: [ 0x16, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x22, x23, VTTBR_EL2"

  -
    input:
      bytes: [ 0x18, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x24, x25, VTTBR_EL2"

  -
    input:
      bytes: [ 0x1a, 0x21, 0x7c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "mrrs x26, x27, VTTBR_EL2"

  -
    input:
      bytes: [ 0x00, 0x20, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr TTBR0_EL1, x0, x1"

  -
    input:
      bytes: [ 0x20, 0x20, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr TTBR1_EL1, x0, x1"

  -
    input:
      bytes: [ 0x00, 0x74, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr PAR_EL1, x0, x1"

  -
    input:
      bytes: [ 0x60, 0xd0, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr RCWSMASK_EL1, x0, x1"

  -
    input:
      bytes: [ 0xc0, 0xd0, 0x58, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr RCWMASK_EL1, x0, x1"

  -
    input:
      bytes: [ 0x00, 0x20, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr TTBR0_EL2, x0, x1"

  -
    input:
      bytes: [ 0x20, 0x20, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr TTBR1_EL2, x0, x1"

  -
    input:
      bytes: [ 0x00, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x0, x1"

  -
    input:
      bytes: [ 0x00, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x0, x1"

  -
    input:
      bytes: [ 0x02, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x2, x3"

  -
    input:
      bytes: [ 0x04, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x4, x5"

  -
    input:
      bytes: [ 0x06, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x6, x7"

  -
    input:
      bytes: [ 0x08, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x8, x9"

  -
    input:
      bytes: [ 0x0a, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x10, x11"

  -
    input:
      bytes: [ 0x0c, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x12, x13"

  -
    input:
      bytes: [ 0x0e, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x14, x15"

  -
    input:
      bytes: [ 0x10, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x16, x17"

  -
    input:
      bytes: [ 0x12, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x18, x19"

  -
    input:
      bytes: [ 0x14, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x20, x21"

  -
    input:
      bytes: [ 0x16, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x22, x23"

  -
    input:
      bytes: [ 0x18, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x24, x25"

  -
    input:
      bytes: [ 0x1a, 0x21, 0x5c, 0xd5 ]
      arch: "CS_ARCH_AARCH64"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
    expected:
      insns:
        -
          asm_text: "msrr VTTBR_EL2, x26, x27"