/* Capstone Disassembly Engine, https://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2022, */ /* Rot127 2022-2024 */ /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ /* LLVM-commit: */ /* LLVM-tag: */ /* Do not edit. */ /* Capstone's LLVM TableGen Backends: */ /* https://github.com/capstone-engine/llvm-capstone */ AArch64_OP_GROUP_AMNoIndex = 0, AArch64_OP_GROUP_AdrLabel = 1, AArch64_OP_GROUP_AdrpLabel = 2, AArch64_OP_GROUP_BTIHintOp = 3, AArch64_OP_GROUP_ImplicitlyTypedVectorList = 4, AArch64_OP_GROUP_InverseCondCode = 5, AArch64_OP_GROUP_LogicalImm_int16_t = 6, AArch64_OP_GROUP_LogicalImm_int8_t = 7, AArch64_OP_GROUP_MatrixIndex_0 = 8, AArch64_OP_GROUP_MatrixIndex_1 = 9, AArch64_OP_GROUP_MatrixIndex_8 = 10, AArch64_OP_GROUP_PSBHintOp = 11, AArch64_OP_GROUP_PrefetchOp_1 = 12, AArch64_OP_GROUP_SVELogicalImm_int16_t = 13, AArch64_OP_GROUP_SVELogicalImm_int32_t = 14, AArch64_OP_GROUP_SVELogicalImm_int64_t = 15, AArch64_OP_GROUP_SVERegOp_0 = 16, AArch64_OP_GROUP_VectorIndex_8 = 17, AArch64_OP_GROUP_ZPRasFPR_128 = 18, AArch64_OP_GROUP_Operand = 19, AArch64_OP_GROUP_SVERegOp_b = 20, AArch64_OP_GROUP_SVERegOp_d = 21, AArch64_OP_GROUP_SVERegOp_h = 22, AArch64_OP_GROUP_SVERegOp_s = 23, AArch64_OP_GROUP_TypedVectorList_0_d = 24, AArch64_OP_GROUP_TypedVectorList_0_s = 25, AArch64_OP_GROUP_VRegOperand = 26, AArch64_OP_GROUP_TypedVectorList_0_h = 27, AArch64_OP_GROUP_VectorIndex_1 = 28, AArch64_OP_GROUP_ImmRangeScale_2_1 = 29, AArch64_OP_GROUP_AlignedLabel = 30, AArch64_OP_GROUP_CondCode = 31, AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_one = 32, AArch64_OP_GROUP_TypedVectorList_0_b = 33, AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_zero_AArch64ExactFPImm_one = 34, AArch64_OP_GROUP_ImmRangeScale_4_3 = 35, AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_two = 36, AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_d = 37, AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_d = 38, AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_d = 39, AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_s = 40, AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_s = 41, AArch64_OP_GROUP_ImmScale_8 = 42, AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_d = 43, AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_d = 44, AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_d = 45, AArch64_OP_GROUP_ImmScale_2 = 46, AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_d = 47, AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_d = 48, AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_d = 49, AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_s = 50, AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_s = 51, AArch64_OP_GROUP_ImmScale_4 = 52, AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_d = 53, AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_d = 54, AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_d = 55, AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_s = 56, AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_s = 57, AArch64_OP_GROUP_PredicateAsCounter_0 = 58, AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_0 = 59, AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_0 = 60, AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_0 = 61, AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_0 = 62, AArch64_OP_GROUP_SVCROp = 63, AArch64_OP_GROUP_ImmScale_16 = 64, AArch64_OP_GROUP_MatrixTile = 65, AArch64_OP_GROUP_Shifter = 66, AArch64_OP_GROUP_AddSubImm = 67, AArch64_OP_GROUP_ShiftedRegister = 68, AArch64_OP_GROUP_ExtendedRegister = 69, AArch64_OP_GROUP_ArithExtend = 70, AArch64_OP_GROUP_Matrix_64 = 71, AArch64_OP_GROUP_Matrix_32 = 72, AArch64_OP_GROUP_Imm8OptLsl_uint8_t = 73, AArch64_OP_GROUP_Imm8OptLsl_uint64_t = 74, AArch64_OP_GROUP_Imm8OptLsl_uint16_t = 75, AArch64_OP_GROUP_Imm8OptLsl_uint32_t = 76, AArch64_OP_GROUP_AdrAdrpLabel = 77, AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_s = 78, AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_s = 79, AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_s = 80, AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_s = 81, AArch64_OP_GROUP_LogicalImm_int32_t = 82, AArch64_OP_GROUP_LogicalImm_int64_t = 83, AArch64_OP_GROUP_ZPRasFPR_8 = 84, AArch64_OP_GROUP_ZPRasFPR_64 = 85, AArch64_OP_GROUP_ZPRasFPR_16 = 86, AArch64_OP_GROUP_ZPRasFPR_32 = 87, AArch64_OP_GROUP_Matrix_16 = 88, AArch64_OP_GROUP_Imm = 89, AArch64_OP_GROUP_ImmHex = 90, AArch64_OP_GROUP_ComplexRotationOp_180_90 = 91, AArch64_OP_GROUP_GPRSeqPairsClassOperand_32 = 92, AArch64_OP_GROUP_GPRSeqPairsClassOperand_64 = 93, AArch64_OP_GROUP_ComplexRotationOp_90_0 = 94, AArch64_OP_GROUP_SVEPattern = 95, AArch64_OP_GROUP_PredicateAsCounter_8 = 96, AArch64_OP_GROUP_SVEVecLenSpecifier = 97, AArch64_OP_GROUP_PredicateAsCounter_64 = 98, AArch64_OP_GROUP_PredicateAsCounter_16 = 99, AArch64_OP_GROUP_PredicateAsCounter_32 = 100, AArch64_OP_GROUP_Imm8OptLsl_int8_t = 101, AArch64_OP_GROUP_Imm8OptLsl_int64_t = 102, AArch64_OP_GROUP_Imm8OptLsl_int16_t = 103, AArch64_OP_GROUP_Imm8OptLsl_int32_t = 104, AArch64_OP_GROUP_BarrierOption = 105, AArch64_OP_GROUP_BarriernXSOption = 106, AArch64_OP_GROUP_SVERegOp_q = 107, AArch64_OP_GROUP_MatrixTileVector_0 = 108, AArch64_OP_GROUP_MatrixTileVector_1 = 109, AArch64_OP_GROUP_FPImmOperand = 110, AArch64_OP_GROUP_TypedVectorList_0_q = 111, AArch64_OP_GROUP_SImm_8 = 112, AArch64_OP_GROUP_SImm_16 = 113, AArch64_OP_GROUP_TypedVectorList_16_b = 114, AArch64_OP_GROUP_PostIncOperand_64 = 115, AArch64_OP_GROUP_TypedVectorList_1_d = 116, AArch64_OP_GROUP_PostIncOperand_32 = 117, AArch64_OP_GROUP_TypedVectorList_2_d = 118, AArch64_OP_GROUP_TypedVectorList_2_s = 119, AArch64_OP_GROUP_TypedVectorList_4_h = 120, AArch64_OP_GROUP_TypedVectorList_4_s = 121, AArch64_OP_GROUP_TypedVectorList_8_b = 122, AArch64_OP_GROUP_TypedVectorList_8_h = 123, AArch64_OP_GROUP_PostIncOperand_16 = 124, AArch64_OP_GROUP_PostIncOperand_8 = 125, AArch64_OP_GROUP_ImmScale_32 = 126, AArch64_OP_GROUP_PostIncOperand_1 = 127, AArch64_OP_GROUP_PostIncOperand_4 = 128, AArch64_OP_GROUP_PostIncOperand_2 = 129, AArch64_OP_GROUP_PostIncOperand_48 = 130, AArch64_OP_GROUP_PostIncOperand_24 = 131, AArch64_OP_GROUP_RegWithShiftExtend_0_128_x_0 = 132, AArch64_OP_GROUP_ImmScale_3 = 133, AArch64_OP_GROUP_PostIncOperand_3 = 134, AArch64_OP_GROUP_PostIncOperand_12 = 135, AArch64_OP_GROUP_PostIncOperand_6 = 136, AArch64_OP_GROUP_GPR64x8 = 137, AArch64_OP_GROUP_MemExtend_w_8 = 138, AArch64_OP_GROUP_MemExtend_x_8 = 139, AArch64_OP_GROUP_UImm12Offset_1 = 140, AArch64_OP_GROUP_MemExtend_w_64 = 141, AArch64_OP_GROUP_MemExtend_x_64 = 142, AArch64_OP_GROUP_UImm12Offset_8 = 143, AArch64_OP_GROUP_MemExtend_w_16 = 144, AArch64_OP_GROUP_MemExtend_x_16 = 145, AArch64_OP_GROUP_UImm12Offset_2 = 146, AArch64_OP_GROUP_MemExtend_w_128 = 147, AArch64_OP_GROUP_MemExtend_x_128 = 148, AArch64_OP_GROUP_UImm12Offset_16 = 149, AArch64_OP_GROUP_MemExtend_w_32 = 150, AArch64_OP_GROUP_MemExtend_x_32 = 151, AArch64_OP_GROUP_UImm12Offset_4 = 152, AArch64_OP_GROUP_Matrix_0 = 153, AArch64_OP_GROUP_TypedVectorList_0_0 = 154, AArch64_OP_GROUP_SIMDType10Operand = 155, AArch64_OP_GROUP_MRSSystemRegister = 156, AArch64_OP_GROUP_MSRSystemRegister = 157, AArch64_OP_GROUP_SystemPStateField = 158, AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_s = 159, AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_s = 160, AArch64_OP_GROUP_PrefetchOp_0 = 161, AArch64_OP_GROUP_RPRFMOperand = 162, AArch64_OP_GROUP_GPR64as32 = 163, AArch64_OP_GROUP_SysCROperand = 164, AArch64_OP_GROUP_SyspXzrPair = 165, AArch64_OP_GROUP_MatrixTileList = 166,