test_cases:
  -
    input:
      bytes: [ 0x08, 0x44, 0x08, 0x44, 0x40, 0x18, 0x40, 0x18, 0x08, 0x44, 0x08, 0x44, 0x40, 0x18, 0x40, 0x18, 0x01, 0xbf, 0x40, 0x18, 0x08, 0x44, 0x10, 0xeb, 0x01, 0x00, 0x10, 0xeb, 0x01, 0x00, 0x40, 0x1a, 0x40, 0x1a, 0xa0, 0xeb, 0x01, 0x00, 0xa0, 0xeb, 0x01, 0x00, 0x40, 0x1a, 0x40, 0x1a, 0x01, 0xbf, 0x40, 0x1a, 0x40, 0x1a, 0xb0, 0xeb, 0x01, 0x00, 0xb0, 0xeb, 0x01, 0x00 ]
      arch: "CS_ARCH_ARM"
      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
    expected:
      insns:
        -
          asm_text: "add r0, r1"
        -
          asm_text: "add r0, r1"
        -
          asm_text: "adds r0, r0, r1"
        -
          asm_text: "adds r0, r0, r1"
        -
          asm_text: "add r0, r1"
        -
          asm_text: "add r0, r1"
        -
          asm_text: "adds r0, r0, r1"
        -
          asm_text: "adds r0, r0, r1"
        -
          asm_text: "itttt eq"
        -
          asm_text: "addeq r0, r0, r1"
        -
          asm_text: "addeq r0, r1"
        -
          asm_text: "addseq.w r0, r0, r1"
        -
          asm_text: "addseq.w r0, r0, r1"
        -
          asm_text: "subs r0, r0, r1"
        -
          asm_text: "subs r0, r0, r1"
        -
          asm_text: "sub.w r0, r0, r1"
        -
          asm_text: "sub.w r0, r0, r1"
        -
          asm_text: "subs r0, r0, r1"
        -
          asm_text: "subs r0, r0, r1"
        -
          asm_text: "itttt eq"
        -
          asm_text: "subeq r0, r0, r1"
        -
          asm_text: "subeq r0, r0, r1"
        -
          asm_text: "subseq.w r0, r0, r1"
        -
          asm_text: "subseq.w r0, r0, r1"