saulteafarmer/XenonRecomp
1
0
Fork 0
mirror of https://github.com/hedge-dev/XenonRecomp.git synced 2025-06-06 01:02:08 +00:00
Code Issues Packages Projects Releases Wiki Activity
XenonRecomp/thirdparty/capstone/tests/MC/AArch64/SME2/fsub.s.yaml
Sajid 0f9a53f75a Initial Commit
2024-09-07 18:15:29 +06:00

961 lines
25 KiB
YAML
Raw Blame History

test_cases:
-
input:
bytes: [ 0x08, 0x1c, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 0, vgx2], { z0.d, z1.d }"
-
input:
bytes: [ 0x08, 0x1c, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 0, vgx2], { z0.d, z1.d }"
-
input:
bytes: [ 0x4d, 0x5d, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w10, 5, vgx2], { z10.d, z11.d }"
-
input:
bytes: [ 0x4d, 0x5d, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w10, 5, vgx2], { z10.d, z11.d }"
-
input:
bytes: [ 0x8f, 0x7d, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w11, 7, vgx2], { z12.d, z13.d }"
-
input:
bytes: [ 0x8f, 0x7d, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w11, 7, vgx2], { z12.d, z13.d }"
-
input:
bytes: [ 0xcf, 0x7f, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w11, 7, vgx2], { z30.d, z31.d }"
-
input:
bytes: [ 0xcf, 0x7f, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w11, 7, vgx2], { z30.d, z31.d }"
-
input:
bytes: [ 0x0d, 0x1e, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 5, vgx2], { z16.d, z17.d }"
-
input:
bytes: [ 0x0d, 0x1e, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 5, vgx2], { z16.d, z17.d }"
-
input:
bytes: [ 0x09, 0x1c, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 1, vgx2], { z0.d, z1.d }"
-
input:
bytes: [ 0x09, 0x1c, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 1, vgx2], { z0.d, z1.d }"
-
input:
bytes: [ 0x48, 0x5e, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w10, 0, vgx2], { z18.d, z19.d }"
-
input:
bytes: [ 0x48, 0x5e, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w10, 0, vgx2], { z18.d, z19.d }"
-
input:
bytes: [ 0x88, 0x1d, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 0, vgx2], { z12.d, z13.d }"
-
input:
bytes: [ 0x88, 0x1d, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 0, vgx2], { z12.d, z13.d }"
-
input:
bytes: [ 0x09, 0x5c, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w10, 1, vgx2], { z0.d, z1.d }"
-
input:
bytes: [ 0x09, 0x5c, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w10, 1, vgx2], { z0.d, z1.d }"
-
input:
bytes: [ 0xcd, 0x1e, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 5, vgx2], { z22.d, z23.d }"
-
input:
bytes: [ 0xcd, 0x1e, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 5, vgx2], { z22.d, z23.d }"
-
input:
bytes: [ 0x0a, 0x7d, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w11, 2, vgx2], { z8.d, z9.d }"
-
input:
bytes: [ 0x0a, 0x7d, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w11, 2, vgx2], { z8.d, z9.d }"
-
input:
bytes: [ 0x8f, 0x3d, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w9, 7, vgx2], { z12.d, z13.d }"
-
input:
bytes: [ 0x8f, 0x3d, 0xe0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w9, 7, vgx2], { z12.d, z13.d }"
-
input:
bytes: [ 0x08, 0x1c, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 0, vgx2], { z0.s, z1.s }"
-
input:
bytes: [ 0x08, 0x1c, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 0, vgx2], { z0.s, z1.s }"
-
input:
bytes: [ 0x4d, 0x5d, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w10, 5, vgx2], { z10.s, z11.s }"
-
input:
bytes: [ 0x4d, 0x5d, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w10, 5, vgx2], { z10.s, z11.s }"
-
input:
bytes: [ 0x8f, 0x7d, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w11, 7, vgx2], { z12.s, z13.s }"
-
input:
bytes: [ 0x8f, 0x7d, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w11, 7, vgx2], { z12.s, z13.s }"
-
input:
bytes: [ 0xcf, 0x7f, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w11, 7, vgx2], { z30.s, z31.s }"
-
input:
bytes: [ 0xcf, 0x7f, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w11, 7, vgx2], { z30.s, z31.s }"
-
input:
bytes: [ 0x0d, 0x1e, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 5, vgx2], { z16.s, z17.s }"
-
input:
bytes: [ 0x0d, 0x1e, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 5, vgx2], { z16.s, z17.s }"
-
input:
bytes: [ 0x09, 0x1c, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 1, vgx2], { z0.s, z1.s }"
-
input:
bytes: [ 0x09, 0x1c, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 1, vgx2], { z0.s, z1.s }"
-
input:
bytes: [ 0x48, 0x5e, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w10, 0, vgx2], { z18.s, z19.s }"
-
input:
bytes: [ 0x48, 0x5e, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w10, 0, vgx2], { z18.s, z19.s }"
-
input:
bytes: [ 0x88, 0x1d, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 0, vgx2], { z12.s, z13.s }"
-
input:
bytes: [ 0x88, 0x1d, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 0, vgx2], { z12.s, z13.s }"
-
input:
bytes: [ 0x09, 0x5c, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w10, 1, vgx2], { z0.s, z1.s }"
-
input:
bytes: [ 0x09, 0x5c, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w10, 1, vgx2], { z0.s, z1.s }"
-
input:
bytes: [ 0xcd, 0x1e, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 5, vgx2], { z22.s, z23.s }"
-
input:
bytes: [ 0xcd, 0x1e, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 5, vgx2], { z22.s, z23.s }"
-
input:
bytes: [ 0x0a, 0x7d, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w11, 2, vgx2], { z8.s, z9.s }"
-
input:
bytes: [ 0x0a, 0x7d, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w11, 2, vgx2], { z8.s, z9.s }"
-
input:
bytes: [ 0x8f, 0x3d, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w9, 7, vgx2], { z12.s, z13.s }"
-
input:
bytes: [ 0x8f, 0x3d, 0xa0, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w9, 7, vgx2], { z12.s, z13.s }"
-
input:
bytes: [ 0x08, 0x1c, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 0, vgx4], { z0.d - z3.d }"
-
input:
bytes: [ 0x08, 0x1c, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 0, vgx4], { z0.d - z3.d }"
-
input:
bytes: [ 0x0d, 0x5d, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w10, 5, vgx4], { z8.d - z11.d }"
-
input:
bytes: [ 0x0d, 0x5d, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w10, 5, vgx4], { z8.d - z11.d }"
-
input:
bytes: [ 0x8f, 0x7d, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w11, 7, vgx4], { z12.d - z15.d }"
-
input:
bytes: [ 0x8f, 0x7d, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w11, 7, vgx4], { z12.d - z15.d }"
-
input:
bytes: [ 0x8f, 0x7f, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w11, 7, vgx4], { z28.d - z31.d }"
-
input:
bytes: [ 0x8f, 0x7f, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w11, 7, vgx4], { z28.d - z31.d }"
-
input:
bytes: [ 0x0d, 0x1e, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 5, vgx4], { z16.d - z19.d }"
-
input:
bytes: [ 0x0d, 0x1e, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 5, vgx4], { z16.d - z19.d }"
-
input:
bytes: [ 0x09, 0x1c, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 1, vgx4], { z0.d - z3.d }"
-
input:
bytes: [ 0x09, 0x1c, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 1, vgx4], { z0.d - z3.d }"
-
input:
bytes: [ 0x08, 0x5e, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w10, 0, vgx4], { z16.d - z19.d }"
-
input:
bytes: [ 0x08, 0x5e, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w10, 0, vgx4], { z16.d - z19.d }"
-
input:
bytes: [ 0x88, 0x1d, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 0, vgx4], { z12.d - z15.d }"
-
input:
bytes: [ 0x88, 0x1d, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 0, vgx4], { z12.d - z15.d }"
-
input:
bytes: [ 0x09, 0x5c, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w10, 1, vgx4], { z0.d - z3.d }"
-
input:
bytes: [ 0x09, 0x5c, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w10, 1, vgx4], { z0.d - z3.d }"
-
input:
bytes: [ 0x8d, 0x1e, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 5, vgx4], { z20.d - z23.d }"
-
input:
bytes: [ 0x8d, 0x1e, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w8, 5, vgx4], { z20.d - z23.d }"
-
input:
bytes: [ 0x0a, 0x7d, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w11, 2, vgx4], { z8.d - z11.d }"
-
input:
bytes: [ 0x0a, 0x7d, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w11, 2, vgx4], { z8.d - z11.d }"
-
input:
bytes: [ 0x8f, 0x3d, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w9, 7, vgx4], { z12.d - z15.d }"
-
input:
bytes: [ 0x8f, 0x3d, 0xe1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.d[w9, 7, vgx4], { z12.d - z15.d }"
-
input:
bytes: [ 0x08, 0x1c, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 0, vgx4], { z0.s - z3.s }"
-
input:
bytes: [ 0x08, 0x1c, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 0, vgx4], { z0.s - z3.s }"
-
input:
bytes: [ 0x0d, 0x5d, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w10, 5, vgx4], { z8.s - z11.s }"
-
input:
bytes: [ 0x0d, 0x5d, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w10, 5, vgx4], { z8.s - z11.s }"
-
input:
bytes: [ 0x8f, 0x7d, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w11, 7, vgx4], { z12.s - z15.s }"
-
input:
bytes: [ 0x8f, 0x7d, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w11, 7, vgx4], { z12.s - z15.s }"
-
input:
bytes: [ 0x8f, 0x7f, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w11, 7, vgx4], { z28.s - z31.s }"
-
input:
bytes: [ 0x8f, 0x7f, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w11, 7, vgx4], { z28.s - z31.s }"
-
input:
bytes: [ 0x0d, 0x1e, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 5, vgx4], { z16.s - z19.s }"
-
input:
bytes: [ 0x0d, 0x1e, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 5, vgx4], { z16.s - z19.s }"
-
input:
bytes: [ 0x09, 0x1c, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 1, vgx4], { z0.s - z3.s }"
-
input:
bytes: [ 0x09, 0x1c, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 1, vgx4], { z0.s - z3.s }"
-
input:
bytes: [ 0x08, 0x5e, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w10, 0, vgx4], { z16.s - z19.s }"
-
input:
bytes: [ 0x08, 0x5e, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w10, 0, vgx4], { z16.s - z19.s }"
-
input:
bytes: [ 0x88, 0x1d, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 0, vgx4], { z12.s - z15.s }"
-
input:
bytes: [ 0x88, 0x1d, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 0, vgx4], { z12.s - z15.s }"
-
input:
bytes: [ 0x09, 0x5c, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w10, 1, vgx4], { z0.s - z3.s }"
-
input:
bytes: [ 0x09, 0x5c, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w10, 1, vgx4], { z0.s - z3.s }"
-
input:
bytes: [ 0x8d, 0x1e, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 5, vgx4], { z20.s - z23.s }"
-
input:
bytes: [ 0x8d, 0x1e, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w8, 5, vgx4], { z20.s - z23.s }"
-
input:
bytes: [ 0x0a, 0x7d, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w11, 2, vgx4], { z8.s - z11.s }"
-
input:
bytes: [ 0x0a, 0x7d, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w11, 2, vgx4], { z8.s - z11.s }"
-
input:
bytes: [ 0x8f, 0x3d, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w9, 7, vgx4], { z12.s - z15.s }"
-
input:
bytes: [ 0x8f, 0x3d, 0xa1, 0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
expected:
insns:
-
asm_text: "fsub za.s[w9, 7, vgx4], { z12.s - z15.s }"
Reference in New Issue View Git Blame Copy Permalink