mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 01:02:08 +00:00
321 lines
7.1 KiB
YAML
321 lines
7.1 KiB
YAML
test_cases:
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-
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input:
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bytes: [ 0x00, 0x8c, 0x2b, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp x0, p0.b"
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-
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input:
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bytes: [ 0x00, 0x8c, 0x6b, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp x0, p0.h"
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-
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input:
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bytes: [ 0x00, 0x8c, 0xab, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp x0, p0.s"
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-
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input:
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bytes: [ 0x00, 0x8c, 0xeb, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp x0, p0.d"
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-
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input:
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bytes: [ 0xff, 0x89, 0x2b, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp wzr, p15.b"
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-
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input:
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bytes: [ 0xff, 0x89, 0x6b, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp wzr, p15.h"
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-
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input:
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bytes: [ 0xff, 0x89, 0xab, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp wzr, p15.s"
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-
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input:
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bytes: [ 0xff, 0x89, 0xeb, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp wzr, p15.d"
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-
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input:
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bytes: [ 0x00, 0x80, 0x6b, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.h, p0.h"
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-
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input:
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bytes: [ 0x00, 0x80, 0x6b, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.h, p0.h"
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-
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input:
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bytes: [ 0x00, 0x80, 0xab, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.s, p0.s"
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-
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input:
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bytes: [ 0x00, 0x80, 0xab, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.s, p0.s"
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-
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input:
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bytes: [ 0x00, 0x80, 0xeb, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.d, p0.d"
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-
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input:
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bytes: [ 0x00, 0x80, 0xeb, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.d, p0.d"
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-
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input:
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bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "movprfx z0, z7"
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input:
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bytes: [ 0x00, 0x80, 0xeb, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.d, p0.d"
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-
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input:
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bytes: [ 0x00, 0x8c, 0x2b, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp x0, p0.b"
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-
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input:
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bytes: [ 0x00, 0x8c, 0x6b, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp x0, p0.h"
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-
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input:
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bytes: [ 0x00, 0x8c, 0xab, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp x0, p0.s"
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-
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input:
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bytes: [ 0x00, 0x8c, 0xeb, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp x0, p0.d"
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-
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input:
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bytes: [ 0xff, 0x89, 0x2b, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp wzr, p15.b"
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-
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input:
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bytes: [ 0xff, 0x89, 0x6b, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp wzr, p15.h"
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-
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input:
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bytes: [ 0xff, 0x89, 0xab, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp wzr, p15.s"
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-
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input:
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bytes: [ 0xff, 0x89, 0xeb, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp wzr, p15.d"
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-
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input:
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bytes: [ 0x00, 0x80, 0x6b, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.h, p0.h"
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-
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input:
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bytes: [ 0x00, 0x80, 0x6b, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.h, p0.h"
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-
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input:
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bytes: [ 0x00, 0x80, 0xab, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.s, p0.s"
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-
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input:
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bytes: [ 0x00, 0x80, 0xab, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.s, p0.s"
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-
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input:
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bytes: [ 0x00, 0x80, 0xeb, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.d, p0.d"
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-
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input:
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bytes: [ 0x00, 0x80, 0xeb, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.d, p0.d"
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-
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input:
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bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "movprfx z0, z7"
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-
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input:
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bytes: [ 0x00, 0x80, 0xeb, 0x25 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
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expected:
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insns:
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-
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asm_text: "uqdecp z0.d, p0.d"
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