mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 01:02:08 +00:00
181 lines
4.1 KiB
YAML
181 lines
4.1 KiB
YAML
test_cases:
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x60, 0x5f, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z0.h, z1.b, z31.b"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x60, 0x9f, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z0.s, z1.h, z31.h"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x60, 0xdf, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z0.d, z1.s, z31.s"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x28, 0xbf, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z0.s, z1.h, z7.h[7]"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x28, 0xff, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z0.d, z1.s, z15.s[3]"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "movprfx z21, z28"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x35, 0x60, 0xdf, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z21.d, z1.s, z31.s"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "movprfx z21, z28"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x55, 0x29, 0xe5, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z21.d, z10.s, z5.s[1]"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x60, 0x5f, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z0.h, z1.b, z31.b"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x60, 0x9f, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z0.s, z1.h, z31.h"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x60, 0xdf, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z0.d, z1.s, z31.s"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x28, 0xbf, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z0.s, z1.h, z7.h[7]"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x28, 0xff, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z0.d, z1.s, z15.s[3]"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "movprfx z21, z28"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x35, 0x60, 0xdf, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z21.d, z1.s, z31.s"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "movprfx z21, z28"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x55, 0x29, 0xe5, 0x44 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "sqdmlalb z21.d, z10.s, z5.s[1]"
|