mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-04 08:12:05 +00:00
441 lines
9.9 KiB
YAML
441 lines
9.9 KiB
YAML
test_cases:
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x11, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HFGRTR_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa5, 0x11, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HFGWTR_EL2, x5"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xca, 0x11, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HFGITR_EL2, x10"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x8f, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HDFGRTR_EL2, x15"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xb4, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HDFGWTR_EL2, x20"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xd9, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HAFGRTR_EL2, x25"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x11, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, HFGRTR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xb9, 0x11, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x25, HFGWTR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xd4, 0x11, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x20, HFGITR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x8f, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x15, HDFGRTR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xaa, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x10, HDFGWTR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xc5, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x5, HAFGRTR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x03, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x3, HDFGRTR2_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x23, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x3, HDFGWTR2_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x43, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x3, HFGRTR2_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x63, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x3, HFGWTR2_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xe3, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x3, HFGITR2_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x03, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HDFGRTR2_EL2, x3"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x23, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HDFGWTR2_EL2, x3"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x43, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HFGRTR2_EL2, x3"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x63, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HFGWTR2_EL2, x3"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xe3, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HFGITR2_EL2, x3"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x11, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HFGRTR_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa5, 0x11, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HFGWTR_EL2, x5"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xca, 0x11, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HFGITR_EL2, x10"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x8f, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HDFGRTR_EL2, x15"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xb4, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HDFGWTR_EL2, x20"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xd9, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HAFGRTR_EL2, x25"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x11, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, HFGRTR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xb9, 0x11, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x25, HFGWTR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xd4, 0x11, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x20, HFGITR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x8f, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x15, HDFGRTR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xaa, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x10, HDFGWTR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xc5, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x5, HAFGRTR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x03, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x3, HDFGRTR2_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x23, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x3, HDFGWTR2_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x43, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x3, HFGRTR2_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x63, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x3, HFGWTR2_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xe3, 0x31, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x3, HFGITR2_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x03, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HDFGRTR2_EL2, x3"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x23, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HDFGWTR2_EL2, x3"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x43, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HFGRTR2_EL2, x3"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x63, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HFGWTR2_EL2, x3"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xe3, 0x31, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr HFGITR2_EL2, x3"
|