mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-04 08:12:05 +00:00
2851 lines
63 KiB
YAML
2851 lines
63 KiB
YAML
test_cases:
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-
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input:
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bytes: [ 0x00, 0x20, 0x3c, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, TTBR0_EL2"
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-
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input:
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bytes: [ 0x80, 0x00, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, MPUIR_EL1"
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-
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input:
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bytes: [ 0x80, 0x00, 0x3c, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, MPUIR_EL2"
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-
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input:
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bytes: [ 0x20, 0x61, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRENR_EL1"
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-
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input:
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bytes: [ 0x20, 0x61, 0x3c, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRENR_EL2"
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-
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input:
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bytes: [ 0x20, 0x62, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRSELR_EL1"
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-
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input:
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bytes: [ 0x20, 0x62, 0x3c, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRSELR_EL2"
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-
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input:
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bytes: [ 0x00, 0x68, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR_EL1"
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-
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input:
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bytes: [ 0x00, 0x68, 0x3c, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR_EL2"
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-
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input:
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bytes: [ 0x20, 0x68, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR_EL1"
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-
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input:
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bytes: [ 0x20, 0x68, 0x3c, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR_EL2"
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-
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input:
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bytes: [ 0x80, 0x68, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR1_EL1"
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-
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input:
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bytes: [ 0x00, 0x69, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR2_EL1"
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-
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input:
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bytes: [ 0x80, 0x69, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR3_EL1"
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-
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input:
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bytes: [ 0x00, 0x6a, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR4_EL1"
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-
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input:
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bytes: [ 0x80, 0x6a, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR5_EL1"
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-
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input:
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bytes: [ 0x00, 0x6b, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR6_EL1"
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-
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input:
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bytes: [ 0x80, 0x6b, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR7_EL1"
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-
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input:
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bytes: [ 0x00, 0x6c, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR8_EL1"
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-
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input:
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bytes: [ 0x80, 0x6c, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR9_EL1"
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-
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input:
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bytes: [ 0x00, 0x6d, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR10_EL1"
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-
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input:
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bytes: [ 0x80, 0x6d, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR11_EL1"
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-
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input:
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bytes: [ 0x00, 0x6e, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR12_EL1"
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-
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input:
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bytes: [ 0x80, 0x6e, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR13_EL1"
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-
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input:
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bytes: [ 0x00, 0x6f, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR14_EL1"
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-
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input:
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bytes: [ 0x80, 0x6f, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRBAR15_EL1"
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-
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input:
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bytes: [ 0xa0, 0x68, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR1_EL1"
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-
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input:
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bytes: [ 0x20, 0x69, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR2_EL1"
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-
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input:
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bytes: [ 0xa0, 0x69, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR3_EL1"
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-
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input:
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bytes: [ 0x20, 0x6a, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR4_EL1"
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-
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input:
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bytes: [ 0xa0, 0x6a, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR5_EL1"
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-
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input:
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bytes: [ 0x20, 0x6b, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR6_EL1"
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-
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input:
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bytes: [ 0xa0, 0x6b, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR7_EL1"
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-
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input:
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bytes: [ 0x20, 0x6c, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR8_EL1"
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-
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input:
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bytes: [ 0xa0, 0x6c, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR9_EL1"
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-
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input:
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bytes: [ 0x20, 0x6d, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR10_EL1"
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-
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input:
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bytes: [ 0xa0, 0x6d, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR11_EL1"
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-
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input:
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bytes: [ 0x20, 0x6e, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR12_EL1"
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-
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input:
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bytes: [ 0xa0, 0x6e, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR13_EL1"
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-
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input:
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bytes: [ 0x20, 0x6f, 0x38, 0xd5 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
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expected:
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insns:
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-
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asm_text: "mrs x0, PRLAR14_EL1"
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-
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input:
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bytes: [ 0xa0, 0x6f, 0x38, 0xd5 ]
|
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
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|
insns:
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-
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asm_text: "mrs x0, PRLAR15_EL1"
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-
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input:
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bytes: [ 0x80, 0x68, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
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|
-
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asm_text: "mrs x0, PRBAR1_EL2"
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|
|
|
-
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input:
|
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bytes: [ 0x00, 0x69, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
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|
asm_text: "mrs x0, PRBAR2_EL2"
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|
|
|
-
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input:
|
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bytes: [ 0x80, 0x69, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRBAR3_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6a, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRBAR4_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6a, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRBAR5_EL2"
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|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6b, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRBAR6_EL2"
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|
|
|
-
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|
input:
|
|
bytes: [ 0x80, 0x6b, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRBAR7_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6c, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRBAR8_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6c, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRBAR9_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6d, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRBAR10_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6d, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRBAR11_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6e, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRBAR12_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6e, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRBAR13_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6f, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRBAR14_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6f, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRBAR15_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x68, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR1_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x69, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR2_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x69, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR3_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6a, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR4_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6a, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR5_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6b, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR6_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6b, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR7_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6c, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR8_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6c, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR9_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6d, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR10_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6d, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR11_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6e, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR12_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6e, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR13_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6f, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR14_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6f, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x0, PRLAR15_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x20, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, TTBR0_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x00, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, MPUIR_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x00, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, MPUIR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x61, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRENR_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x61, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRENR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x62, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRSELR_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x62, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRSELR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x68, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x68, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x68, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x68, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x68, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR1_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x69, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR2_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x69, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR3_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6a, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR4_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6a, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR5_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6b, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR6_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6b, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR7_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6c, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR8_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6c, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR9_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6d, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR10_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6d, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR11_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6e, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR12_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6e, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR13_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6f, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR14_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6f, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR15_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x68, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR1_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x69, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR2_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x69, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR3_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6a, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR4_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6a, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR5_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6b, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR6_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6b, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR7_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6c, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR8_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6c, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR9_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6d, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR10_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6d, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR11_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6e, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR12_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6e, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR13_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6f, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR14_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6f, 0x38, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR15_EL1"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x68, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR1_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x69, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR2_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x69, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR3_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6a, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR4_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6a, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR5_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6b, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR6_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6b, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR7_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6c, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR8_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6c, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR9_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6d, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR10_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6d, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR11_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6e, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR12_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6e, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR13_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6f, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR14_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6f, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRBAR15_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x68, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR1_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x69, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR2_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x69, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR3_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6a, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR4_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6a, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR5_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6b, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR6_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6b, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR7_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6c, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR8_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6c, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR9_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6d, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR10_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6d, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR11_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6e, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR12_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6e, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR13_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6f, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR14_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6f, 0x3c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "mrs x30, PRLAR15_EL2"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x20, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr TTBR0_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x00, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr MPUIR_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x00, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr MPUIR_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x61, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRENR_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x61, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRENR_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x62, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRSELR_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x62, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRSELR_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x68, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x68, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x68, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x68, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x68, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR1_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x69, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR2_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x69, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR3_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6a, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR4_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6a, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR5_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6b, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR6_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6b, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR7_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6c, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR8_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6c, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR9_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6d, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR10_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6d, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR11_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6e, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR12_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6e, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR13_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6f, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR14_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6f, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR15_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x68, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR1_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x69, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR2_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x69, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR3_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6a, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR4_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6a, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR5_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6b, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR6_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6b, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR7_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6c, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR8_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6c, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR9_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6d, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR10_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6d, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR11_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6e, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR12_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6e, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR13_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6f, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR14_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6f, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR15_EL1, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x68, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR1_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x69, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR2_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x69, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR3_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6a, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR4_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6a, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR5_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6b, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR6_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6b, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR7_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6c, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR8_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6c, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR9_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6d, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR10_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6d, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR11_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6e, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR12_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6e, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR13_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x00, 0x6f, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR14_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x80, 0x6f, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR15_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x68, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR1_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x69, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR2_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x69, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR3_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6a, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR4_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6a, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR5_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6b, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR6_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6b, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR7_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6c, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR8_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6c, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR9_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6d, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR10_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6d, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR11_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6e, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR12_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6e, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR13_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x6f, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR14_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xa0, 0x6f, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR15_EL2, x0"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x20, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr TTBR0_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x00, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr MPUIR_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x00, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr MPUIR_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x61, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRENR_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x61, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRENR_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x62, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRSELR_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x62, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRSELR_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x68, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x68, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x68, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x68, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x68, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR1_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x69, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR2_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x69, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR3_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6a, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR4_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6a, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR5_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6b, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR6_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6b, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR7_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6c, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR8_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6c, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR9_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6d, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR10_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6d, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR11_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6e, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR12_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6e, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR13_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6f, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR14_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6f, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR15_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x68, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR1_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x69, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR2_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x69, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR3_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6a, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR4_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6a, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR5_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6b, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR6_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6b, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR7_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6c, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR8_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6c, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR9_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6d, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR10_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6d, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR11_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6e, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR12_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6e, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR13_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6f, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR14_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6f, 0x18, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR15_EL1, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x68, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR1_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x69, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR2_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x69, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR3_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6a, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR4_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6a, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR5_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6b, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR6_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6b, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR7_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6c, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR8_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6c, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR9_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6d, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR10_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6d, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR11_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6e, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR12_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6e, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR13_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x6f, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR14_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x9e, 0x6f, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRBAR15_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x68, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR1_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x69, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR2_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x69, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR3_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6a, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR4_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6a, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR5_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6b, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR6_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6b, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR7_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6c, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR8_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6c, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR9_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6d, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR10_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6d, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR11_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6e, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR12_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6e, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR13_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x3e, 0x6f, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR14_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0xbe, 0x6f, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr PRLAR15_EL2, x30"
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0xd0, 0x1c, 0xd5 ]
|
|
arch: "CS_ARCH_AARCH64"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "msr CONTEXTIDR_EL2, x0"
|