mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-04 08:12:05 +00:00
92 lines
1.9 KiB
YAML
92 lines
1.9 KiB
YAML
test_cases:
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-
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input:
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bytes: [ 0x37, 0x34, 0x00, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32" ]
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expected:
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insns:
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-
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asm_text: "lui s0, 3"
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input:
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bytes: [ 0x97, 0x82, 0x00, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32" ]
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expected:
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insns:
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-
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asm_text: "auipc t0, 8"
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input:
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bytes: [ 0x2f, 0xae, 0xaa, 0x0a ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32" ]
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expected:
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insns:
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-
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asm_text: "amoswap.w.rl t3, a0, (s5)"
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input:
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bytes: [ 0xe3, 0x1f, 0x31, 0x5e ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32" ]
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expected:
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insns:
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-
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asm_text: "bne sp, gp, 0xdfe"
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input:
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bytes: [ 0x73, 0x00, 0x00, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32" ]
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expected:
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insns:
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-
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asm_text: "ecall"
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input:
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bytes: [ 0x33, 0x00, 0x31, 0x02 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32" ]
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expected:
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insns:
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-
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asm_text: "mul zero, sp, gp"
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input:
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bytes: [ 0x53, 0x00, 0x31, 0x28 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32" ]
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expected:
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insns:
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-
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asm_text: "fmin.s ft0, ft2, ft3"
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input:
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bytes: [ 0x53, 0x10, 0x31, 0x2a ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32" ]
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expected:
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insns:
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-
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asm_text: "fmax.d ft0, ft2, ft3"
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input:
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bytes: [ 0x27, 0xaa, 0x6a, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32" ]
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expected:
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insns:
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-
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asm_text: "fsw ft6, 0x14(s5)"
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input:
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bytes: [ 0xef, 0xf0, 0x1f, 0xff ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32" ]
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expected:
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insns:
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-
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asm_text: "jal -0x10"
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