mirror of
https://github.com/hedge-dev/XenonRecomp.git
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108 lines
2.7 KiB
YAML
108 lines
2.7 KiB
YAML
test_cases:
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-
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input:
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bytes: [ 0x0c, 0x00, 0x08, 0x14, 0x8c, 0xfd, 0xbf, 0x02 ]
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arch: "loongarch"
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options: [ CS_OPT_DETAIL, CS_MODE_LOONGARCH32 ]
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address: 0x0
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expected:
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insns:
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-
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asm_text: "lu12i.w $t0, 0x4000"
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details:
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loongarch:
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operands:
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-
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type: LOONGARCH_OP_REG
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reg: t0
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-
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type: LOONGARCH_OP_IMM
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imm: 0x4000
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-
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asm_text: "addi.w $t0, $t0, -1"
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details:
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loongarch:
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operands:
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-
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type: LOONGARCH_OP_REG
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reg: t0
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-
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type: LOONGARCH_OP_REG
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reg: t0
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-
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type: LOONGARCH_OP_IMM
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imm: -1
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-
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input:
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bytes: [ 0x80, 0x80, 0x00, 0x40, 0x63, 0x80, 0xff, 0x02, 0x78, 0x20, 0xc0, 0x29, 0x00, 0x84, 0x00, 0x01, 0x00, 0xa4, 0x14, 0x01 ]
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arch: "loongarch"
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options: [ CS_OPT_DETAIL, CS_MODE_LOONGARCH64]
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address: 0x0
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expected:
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insns:
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-
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asm_text: "beqz $a0, 0x80"
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details:
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loongarch:
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operands:
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-
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type: LOONGARCH_OP_REG
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reg: a0
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-
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type: LOONGARCH_OP_IMM
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imm: 0x80
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groups: [ LOONGARCH_GRP_JUMP, LOONGARCH_GRP_BRANCH_RELATIVE ]
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-
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asm_text: "addi.d $sp, $sp, -0x20"
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details:
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loongarch:
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operands:
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-
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type: LOONGARCH_OP_REG
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reg: sp
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-
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type: LOONGARCH_OP_REG
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reg: sp
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-
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type: LOONGARCH_OP_IMM
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imm: -0x20
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groups: [ LOONGARCH_FEATURE_ISLA64 ]
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-
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asm_text: "st.d $s1, $sp, 8"
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details:
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loongarch:
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operands:
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-
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type: LOONGARCH_OP_REG
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reg: s1
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-
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type: LOONGARCH_OP_MEM
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mem_base: sp
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mem_disp: 0x8
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groups: [ LOONGARCH_FEATURE_ISLA64 ]
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-
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asm_text: "fadd.s $fa0, $fa0, $fa1"
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details:
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loongarch:
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operands:
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-
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type: LOONGARCH_OP_REG
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reg: fa0
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-
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type: LOONGARCH_OP_REG
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reg: fa0
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-
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type: LOONGARCH_OP_REG
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reg: fa1
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-
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asm_text: "movgr2fr.w $fa0, $zero"
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details:
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loongarch:
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operands:
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-
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type: LOONGARCH_OP_REG
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reg: fa0
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-
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type: LOONGARCH_OP_REG
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reg: zero
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