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https://github.com/hedge-dev/XenonRecomp.git
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102 lines
2.5 KiB
YAML
102 lines
2.5 KiB
YAML
test_cases:
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-
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input:
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bytes: [ 0x09, 0xcf, 0xbc, 0xf5, 0x09, 0xf4, 0x01, 0x00, 0x89, 0xfb, 0x8f, 0x74, 0x89, 0xfe, 0x48, 0x01, 0x29, 0x00, 0x19, 0x25, 0x29, 0x03, 0x09, 0xf4, 0x85, 0xf9, 0x68, 0x0f, 0x16, 0x01 ]
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arch: "tricore"
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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address: 0x0
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expected:
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insns:
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-
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asm_text: "ld.a a15, [+a12]#-4"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_REG
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reg: a15
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-
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type: TRICORE_OP_MEM
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mem_base: a12
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mem_disp: -4
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-
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asm_text: "ld.b d4, [a15+]#1"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_REG
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reg: d4
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-
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type: TRICORE_OP_MEM
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mem_base: a15
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mem_disp: 0x1
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-
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asm_text: "st.h [+a15]#0x1cf, d11"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_MEM
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mem_base: a15
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mem_disp: 0x1cf
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-
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type: TRICORE_OP_REG
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reg: d11
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-
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asm_text: "st.d [a15+]#8, e14"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_MEM
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mem_base: a15
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mem_disp: 0x8
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-
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type: TRICORE_OP_REG
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reg: e14
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-
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asm_text: "ld.w d0, [p0+c]#0x99"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_REG
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reg: d0
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-
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type: TRICORE_OP_MEM
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mem_base: p0
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mem_disp: 0x99
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-
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asm_text: "ld.b d3, [p0+c]#-0x37"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_REG
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reg: d3
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-
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type: TRICORE_OP_MEM
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mem_base: p0
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mem_disp: -0x37
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-
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asm_text: "ld.da p8, #0xf0003428"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_REG
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reg: p8
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-
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type: TRICORE_OP_IMM
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imm: 0xf0003428
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-
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asm_text: "and d15, #1"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_IMM
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imm: 0x1
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