mirror of
https://github.com/hedge-dev/XenonRecomp.git
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129 lines
3.0 KiB
YAML
129 lines
3.0 KiB
YAML
test_cases:
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-
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input:
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bytes: [ 0xfe, 0x0f, 0xfe, 0x17, 0x13, 0x17, 0xc6, 0xfe, 0xec, 0x17, 0x97, 0xf8, 0xec, 0x4f, 0x1f, 0xfd, 0xec, 0x37, 0x07, 0xf2, 0x45, 0x5b, 0xf9, 0xfa, 0x02, 0x06, 0x1b, 0x10, 0x09, 0xfd, 0xec, 0xa7 ]
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arch: "xcore"
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options: [ CS_OPT_DETAIL ]
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address: 0x0
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expected:
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insns:
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-
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asm_text: "get r11, ed"
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details:
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xcore:
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operands:
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-
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type: XCORE_OP_REG
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reg: r11
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-
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type: XCORE_OP_REG
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reg: ed
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-
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asm_text: "ldw et, sp[4]"
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details:
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xcore:
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operands:
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-
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type: XCORE_OP_REG
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reg: et
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-
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type: XCORE_OP_MEM
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mem_base: sp
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mem_disp: 0x4
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-
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asm_text: "setd res[r3], r4"
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details:
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xcore:
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operands:
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-
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type: XCORE_OP_REG
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reg: r4
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-
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asm_text: "init t[r2]:lr, r1"
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details:
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xcore:
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operands:
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-
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type: XCORE_OP_MEM
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mem_base: r2
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mem_index: lr
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-
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type: XCORE_OP_REG
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reg: r1
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-
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asm_text: "divu r9, r1, r3"
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details:
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xcore:
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operands:
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-
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type: XCORE_OP_REG
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reg: r9
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-
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type: XCORE_OP_REG
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reg: r1
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-
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type: XCORE_OP_REG
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reg: r3
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-
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asm_text: "lda16 r9, r3[-r11]"
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details:
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xcore:
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operands:
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-
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type: XCORE_OP_REG
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reg: r9
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-
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asm_text: "ldw dp, dp[0x81c5]"
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details:
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xcore:
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operands:
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-
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type: XCORE_OP_REG
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reg: dp
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-
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asm_text: "lmul r11, r0, r2, r5, r8, r10"
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details:
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xcore:
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operands:
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-
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type: XCORE_OP_REG
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reg: r11
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-
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type: XCORE_OP_REG
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reg: r0
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-
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type: XCORE_OP_REG
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reg: r2
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-
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type: XCORE_OP_REG
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reg: r5
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-
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type: XCORE_OP_REG
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reg: r8
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-
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type: XCORE_OP_REG
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reg: r10
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-
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asm_text: "add r1, r2, r3"
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details:
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xcore:
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operands:
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-
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type: XCORE_OP_REG
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reg: r1
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-
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type: XCORE_OP_REG
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reg: r2
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-
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type: XCORE_OP_REG
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reg: r3
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-
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asm_text: "ldaw r8, r2[-9]"
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details:
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xcore:
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operands:
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-
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type: XCORE_OP_REG
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reg: r8
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