mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
102 lines
2.7 KiB
C
102 lines
2.7 KiB
C
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
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/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===-- ARMBaseInfo.cpp - ARM Base encoding information------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides basic encoding and assembly information for ARM.
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//
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//===----------------------------------------------------------------------===//
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#include <capstone/platform.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "ARMBaseInfo.h"
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#include "ARMMapping.h"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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const char *get_pred_mask(ARM_PredBlockMask pred_mask)
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{
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switch (pred_mask) {
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default:
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assert(0 && "pred_mask not handled.");
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case ARM_T:
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return "T";
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case ARM_TT:
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return "TT";
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case ARM_TE:
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return "TE";
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case ARM_TTT:
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return "TTT";
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case ARM_TTE:
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return "TTE";
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case ARM_TEE:
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return "TEE";
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case ARM_TET:
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return "TET";
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case ARM_TTTT:
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return "TTTT";
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case ARM_TTTE:
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return "TTTE";
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case ARM_TTEE:
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return "TTEE";
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case ARM_TTET:
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return "TTET";
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case ARM_TEEE:
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return "TEEE";
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case ARM_TEET:
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return "TEET";
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case ARM_TETT:
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return "TETT";
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case ARM_TETE:
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return "TETE";
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}
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}
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#define GET_MCLASSSYSREG_IMPL
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#include "ARMGenSystemRegister.inc"
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// lookup system register using 12-bit SYSm value.
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// Note: the search is uniqued using M1 mask
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const ARMSysReg_MClassSysReg *
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ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
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{
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return ARMSysReg_lookupMClassSysRegByM1Encoding12(SYSm);
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}
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// returns APSR with _<bits> qualifier.
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// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
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const ARMSysReg_MClassSysReg *
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ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
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{
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return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 9) |
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(SYSm & 0xFF));
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}
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// lookup system registers using 8-bit SYSm value
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const ARMSysReg_MClassSysReg *
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ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
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{
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return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 8) |
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(SYSm & 0xFF));
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}
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