mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-10 09:35:06 +00:00
157 lines
5.9 KiB
YAML
157 lines
5.9 KiB
YAML
test_cases:
|
|
-
|
|
input:
|
|
bytes: [ 0x41, 0xef, 0xb0, 0x04, 0x51, 0xef, 0xb0, 0x04, 0x61, 0xef, 0xb0, 0x04, 0x71, 0xef, 0xb0, 0x04, 0x41, 0xff, 0xb0, 0x04, 0x51, 0xff, 0xb0, 0x04, 0x61, 0xff, 0xb0, 0x04, 0x71, 0xff, 0xb0, 0x04, 0x42, 0xef, 0xf0, 0x04, 0x52, 0xef, 0xf0, 0x04, 0x62, 0xef, 0xf0, 0x04, 0x72, 0xef, 0xf0, 0x04, 0x42, 0xff, 0xf0, 0x04, 0x52, 0xff, 0xf0, 0x04, 0x62, 0xff, 0xf0, 0x04, 0x72, 0xff, 0xf0, 0x04, 0xcf, 0xef, 0x30, 0x07, 0xdf, 0xef, 0x30, 0x07, 0xff, 0xef, 0x30, 0x07, 0xff, 0xef, 0xb0, 0x07, 0xcf, 0xff, 0x30, 0x07, 0xdf, 0xff, 0x30, 0x07, 0xff, 0xff, 0x30, 0x07, 0xff, 0xff, 0xb0, 0x07, 0xcf, 0xff, 0x30, 0x06, 0xdf, 0xff, 0x30, 0x06, 0xff, 0xff, 0x30, 0x06, 0xff, 0xff, 0xb0, 0x06, 0xcf, 0xef, 0x70, 0x07, 0xdf, 0xef, 0x70, 0x07, 0xff, 0xef, 0x70, 0x07, 0xff, 0xef, 0xf0, 0x07, 0xcf, 0xff, 0x70, 0x07, 0xdf, 0xff, 0x70, 0x07, 0xff, 0xff, 0x70, 0x07, 0xff, 0xff, 0xf0, 0x07, 0xcf, 0xff, 0x70, 0x06, 0xdf, 0xff, 0x70, 0x06, 0xff, 0xff, 0x70, 0x06, 0xff, 0xff, 0xf0, 0x06, 0x41, 0xef, 0xb0, 0x05, 0x51, 0xef, 0xb0, 0x05, 0x61, 0xef, 0xb0, 0x05, 0x71, 0xef, 0xb0, 0x05, 0x41, 0xff, 0xb0, 0x05, 0x51, 0xff, 0xb0, 0x05, 0x61, 0xff, 0xb0, 0x05, 0x71, 0xff, 0xb0, 0x05, 0x42, 0xef, 0xf0, 0x05, 0x52, 0xef, 0xf0, 0x05, 0x62, 0xef, 0xf0, 0x05, 0x72, 0xef, 0xf0, 0x05, 0x42, 0xff, 0xf0, 0x05, 0x52, 0xff, 0xf0, 0x05, 0x62, 0xff, 0xf0, 0x05, 0x72, 0xff, 0xf0, 0x05, 0xc8, 0xef, 0x30, 0x09, 0xd0, 0xef, 0x30, 0x09, 0xe0, 0xef, 0x30, 0x09, 0xc8, 0xff, 0x30, 0x09, 0xd0, 0xff, 0x30, 0x09, 0xe0, 0xff, 0x30, 0x09, 0xc8, 0xff, 0x30, 0x08, 0xd0, 0xff, 0x30, 0x08, 0xe0, 0xff, 0x30, 0x08, 0xc8, 0xef, 0x70, 0x09, 0xd0, 0xef, 0x70, 0x09, 0xe0, 0xef, 0x70, 0x09, 0xc8, 0xff, 0x70, 0x09, 0xd0, 0xff, 0x70, 0x09, 0xe0, 0xff, 0x70, 0x09, 0xc8, 0xff, 0x70, 0x08, 0xd0, 0xff, 0x70, 0x08, 0xe0, 0xff, 0x70, 0x08 ]
|
|
arch: "CS_ARCH_ARM"
|
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "vqshl.s8 d16, d16, d17"
|
|
-
|
|
asm_text: "vqshl.s16 d16, d16, d17"
|
|
-
|
|
asm_text: "vqshl.s32 d16, d16, d17"
|
|
-
|
|
asm_text: "vqshl.s64 d16, d16, d17"
|
|
-
|
|
asm_text: "vqshl.u8 d16, d16, d17"
|
|
-
|
|
asm_text: "vqshl.u16 d16, d16, d17"
|
|
-
|
|
asm_text: "vqshl.u32 d16, d16, d17"
|
|
-
|
|
asm_text: "vqshl.u64 d16, d16, d17"
|
|
-
|
|
asm_text: "vqshl.s8 q8, q8, q9"
|
|
-
|
|
asm_text: "vqshl.s16 q8, q8, q9"
|
|
-
|
|
asm_text: "vqshl.s32 q8, q8, q9"
|
|
-
|
|
asm_text: "vqshl.s64 q8, q8, q9"
|
|
-
|
|
asm_text: "vqshl.u8 q8, q8, q9"
|
|
-
|
|
asm_text: "vqshl.u16 q8, q8, q9"
|
|
-
|
|
asm_text: "vqshl.u32 q8, q8, q9"
|
|
-
|
|
asm_text: "vqshl.u64 q8, q8, q9"
|
|
-
|
|
asm_text: "vqshl.s8 d16, d16, #7"
|
|
-
|
|
asm_text: "vqshl.s16 d16, d16, #0xf"
|
|
-
|
|
asm_text: "vqshl.s32 d16, d16, #0x1f"
|
|
-
|
|
asm_text: "vqshl.s64 d16, d16, #0x3f"
|
|
-
|
|
asm_text: "vqshl.u8 d16, d16, #7"
|
|
-
|
|
asm_text: "vqshl.u16 d16, d16, #0xf"
|
|
-
|
|
asm_text: "vqshl.u32 d16, d16, #0x1f"
|
|
-
|
|
asm_text: "vqshl.u64 d16, d16, #0x3f"
|
|
-
|
|
asm_text: "vqshlu.s8 d16, d16, #7"
|
|
-
|
|
asm_text: "vqshlu.s16 d16, d16, #0xf"
|
|
-
|
|
asm_text: "vqshlu.s32 d16, d16, #0x1f"
|
|
-
|
|
asm_text: "vqshlu.s64 d16, d16, #0x3f"
|
|
-
|
|
asm_text: "vqshl.s8 q8, q8, #7"
|
|
-
|
|
asm_text: "vqshl.s16 q8, q8, #0xf"
|
|
-
|
|
asm_text: "vqshl.s32 q8, q8, #0x1f"
|
|
-
|
|
asm_text: "vqshl.s64 q8, q8, #0x3f"
|
|
-
|
|
asm_text: "vqshl.u8 q8, q8, #7"
|
|
-
|
|
asm_text: "vqshl.u16 q8, q8, #0xf"
|
|
-
|
|
asm_text: "vqshl.u32 q8, q8, #0x1f"
|
|
-
|
|
asm_text: "vqshl.u64 q8, q8, #0x3f"
|
|
-
|
|
asm_text: "vqshlu.s8 q8, q8, #7"
|
|
-
|
|
asm_text: "vqshlu.s16 q8, q8, #0xf"
|
|
-
|
|
asm_text: "vqshlu.s32 q8, q8, #0x1f"
|
|
-
|
|
asm_text: "vqshlu.s64 q8, q8, #0x3f"
|
|
-
|
|
asm_text: "vqrshl.s8 d16, d16, d17"
|
|
-
|
|
asm_text: "vqrshl.s16 d16, d16, d17"
|
|
-
|
|
asm_text: "vqrshl.s32 d16, d16, d17"
|
|
-
|
|
asm_text: "vqrshl.s64 d16, d16, d17"
|
|
-
|
|
asm_text: "vqrshl.u8 d16, d16, d17"
|
|
-
|
|
asm_text: "vqrshl.u16 d16, d16, d17"
|
|
-
|
|
asm_text: "vqrshl.u32 d16, d16, d17"
|
|
-
|
|
asm_text: "vqrshl.u64 d16, d16, d17"
|
|
-
|
|
asm_text: "vqrshl.s8 q8, q8, q9"
|
|
-
|
|
asm_text: "vqrshl.s16 q8, q8, q9"
|
|
-
|
|
asm_text: "vqrshl.s32 q8, q8, q9"
|
|
-
|
|
asm_text: "vqrshl.s64 q8, q8, q9"
|
|
-
|
|
asm_text: "vqrshl.u8 q8, q8, q9"
|
|
-
|
|
asm_text: "vqrshl.u16 q8, q8, q9"
|
|
-
|
|
asm_text: "vqrshl.u32 q8, q8, q9"
|
|
-
|
|
asm_text: "vqrshl.u64 q8, q8, q9"
|
|
-
|
|
asm_text: "vqshrn.s16 d16, q8, #8"
|
|
-
|
|
asm_text: "vqshrn.s32 d16, q8, #0x10"
|
|
-
|
|
asm_text: "vqshrn.s64 d16, q8, #0x20"
|
|
-
|
|
asm_text: "vqshrn.u16 d16, q8, #8"
|
|
-
|
|
asm_text: "vqshrn.u32 d16, q8, #0x10"
|
|
-
|
|
asm_text: "vqshrn.u64 d16, q8, #0x20"
|
|
-
|
|
asm_text: "vqshrun.s16 d16, q8, #8"
|
|
-
|
|
asm_text: "vqshrun.s32 d16, q8, #0x10"
|
|
-
|
|
asm_text: "vqshrun.s64 d16, q8, #0x20"
|
|
-
|
|
asm_text: "vqrshrn.s16 d16, q8, #8"
|
|
-
|
|
asm_text: "vqrshrn.s32 d16, q8, #0x10"
|
|
-
|
|
asm_text: "vqrshrn.s64 d16, q8, #0x20"
|
|
-
|
|
asm_text: "vqrshrn.u16 d16, q8, #8"
|
|
-
|
|
asm_text: "vqrshrn.u32 d16, q8, #0x10"
|
|
-
|
|
asm_text: "vqrshrn.u64 d16, q8, #0x20"
|
|
-
|
|
asm_text: "vqrshrun.s16 d16, q8, #8"
|
|
-
|
|
asm_text: "vqrshrun.s32 d16, q8, #0x10"
|
|
-
|
|
asm_text: "vqrshrun.s64 d16, q8, #0x20"
|