mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-10 09:35:06 +00:00
103 lines
3.9 KiB
YAML
103 lines
3.9 KiB
YAML
test_cases:
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input:
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bytes: [ 0x80, 0xed, 0x80, 0x2f, 0x09, 0xed, 0x86, 0x4f, 0x29, 0xed, 0x86, 0x4f, 0x29, 0xec, 0x86, 0x4f, 0x88, 0xbf, 0x80, 0xed, 0x80, 0x2f, 0x90, 0xed, 0x80, 0x2f, 0x19, 0xed, 0x86, 0x4f, 0x39, 0xed, 0x86, 0x4f, 0x39, 0xec, 0x86, 0x4f, 0x3d, 0xec, 0x8d, 0x4f, 0x88, 0xbf, 0x90, 0xed, 0x80, 0x2f, 0xcc, 0xed, 0xff, 0xef, 0xec, 0xed, 0xff, 0xef, 0xec, 0xec, 0xff, 0xef, 0x6d, 0xec, 0x86, 0xef, 0xdc, 0xed, 0xff, 0xef, 0xfc, 0xed, 0xff, 0xef, 0xfc, 0xec, 0xff, 0xef, 0x7d, 0xec, 0x86, 0xef, 0xc0, 0xed, 0x80, 0xcf, 0x49, 0xed, 0x86, 0xcf, 0xc6, 0xed, 0xfd, 0xcf, 0x4e, 0xed, 0xff, 0xcf, 0xcc, 0xed, 0xff, 0xcf, 0x6d, 0xec, 0x86, 0xcf, 0xd0, 0xed, 0x80, 0xcf, 0x59, 0xed, 0x86, 0xcf, 0xd6, 0xed, 0xfd, 0xcf, 0x5e, 0xed, 0xff, 0xcf, 0xdc, 0xed, 0xff, 0xcf, 0x7d, 0xec, 0x86, 0xcf, 0xc6, 0xed, 0xfd, 0x8f, 0x4e, 0xed, 0xff, 0xaf, 0xe6, 0xed, 0xfd, 0x8f, 0x6e, 0xed, 0xff, 0xaf, 0xe6, 0xec, 0xfd, 0x8f, 0x6e, 0xec, 0xff, 0xaf, 0x6d, 0xec, 0x86, 0xaf, 0xd6, 0xed, 0xfd, 0x8f, 0x5e, 0xed, 0xff, 0xaf, 0xf6, 0xed, 0xfd, 0x8f, 0x7e, 0xed, 0xff, 0xaf, 0xf6, 0xec, 0xfd, 0x8f, 0x7e, 0xec, 0xff, 0xaf, 0x7d, 0xec, 0x86, 0xaf ]
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arch: "CS_ARCH_ARM"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
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expected:
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insns:
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asm_text: "vstr fpscr, [r0]"
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asm_text: "vstr fpscr_nzcvqc, [r9, #-0x18]"
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asm_text: "vstr fpscr_nzcvqc, [r9, #-0x18]!"
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asm_text: "vstr fpscr_nzcvqc, [r9], #-0x18"
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asm_text: "it hi"
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asm_text: "vstrhi fpscr, [r0]"
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asm_text: "vldr fpscr, [r0]"
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asm_text: "vldr fpscr_nzcvqc, [r9, #-0x18]"
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asm_text: "vldr fpscr_nzcvqc, [r9, #-0x18]!"
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asm_text: "vldr fpscr_nzcvqc, [r9], #-0x18"
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asm_text: "vldr fpscr_nzcvqc, [sp], #-0x34"
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asm_text: "it hi"
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asm_text: "vldrhi fpscr, [r0]"
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asm_text: "vstr fpcxts, [r12, #0x1fc]"
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asm_text: "vstr fpcxts, [r12, #0x1fc]!"
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asm_text: "vstr fpcxts, [r12], #0x1fc"
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asm_text: "vstr fpcxts, [sp], #-0x18"
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asm_text: "vldr fpcxts, [r12, #0x1fc]"
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asm_text: "vldr fpcxts, [r12, #0x1fc]!"
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asm_text: "vldr fpcxts, [r12], #0x1fc"
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asm_text: "vldr fpcxts, [sp], #-0x18"
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asm_text: "vstr fpcxtns, [r0]"
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asm_text: "vstr fpcxtns, [r9, #-0x18]"
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asm_text: "vstr fpcxtns, [r6, #0x1f4]"
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asm_text: "vstr fpcxtns, [lr, #-0x1fc]"
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asm_text: "vstr fpcxtns, [r12, #0x1fc]"
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asm_text: "vstr fpcxtns, [sp], #-0x18"
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asm_text: "vldr fpcxtns, [r0]"
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asm_text: "vldr fpcxtns, [r9, #-0x18]"
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asm_text: "vldr fpcxtns, [r6, #0x1f4]"
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asm_text: "vldr fpcxtns, [lr, #-0x1fc]"
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asm_text: "vldr fpcxtns, [r12, #0x1fc]"
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asm_text: "vldr fpcxtns, [sp], #-0x18"
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asm_text: "vstr vpr, [r6, #0x1f4]"
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asm_text: "vstr p0, [lr, #-0x1fc]"
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asm_text: "vstr vpr, [r6, #0x1f4]!"
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asm_text: "vstr p0, [lr, #-0x1fc]!"
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asm_text: "vstr vpr, [r6], #0x1f4"
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asm_text: "vstr p0, [lr], #-0x1fc"
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asm_text: "vstr p0, [sp], #-0x18"
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asm_text: "vldr vpr, [r6, #0x1f4]"
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asm_text: "vldr p0, [lr, #-0x1fc]"
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asm_text: "vldr vpr, [r6, #0x1f4]!"
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asm_text: "vldr p0, [lr, #-0x1fc]!"
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asm_text: "vldr vpr, [r6], #0x1f4"
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asm_text: "vldr p0, [lr], #-0x1fc"
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asm_text: "vldr p0, [sp], #-0x18"
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