mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-04-23 01:01:26 +00:00
347 lines
8.6 KiB
C++
347 lines
8.6 KiB
C++
#pragma once
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#include <cstdint>
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#include <cstdlib>
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#include <cstring>
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#include <cmath>
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#ifdef __clang__
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#include <x86intrin.h>
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#define __restrict __restrict__
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#define _byteswap_ushort __builtin_bswap16
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#define _byteswap_ulong __builtin_bswap32
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#define _byteswap_uint64 __builtin_bswap64
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#define isnan __builtin_isnan
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#define PPC_FUNC __attribute__((weak,noinline))
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#else
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#include <intrin.h>
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#define PPC_FUNC __declspec(noinline)
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#endif
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#define PPC_LOAD_U8(x) *(uint8_t*)(base + (x))
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#define PPC_LOAD_U16(x) _byteswap_ushort(*(uint16_t*)(base + (x)))
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#define PPC_LOAD_U32(x) _byteswap_ulong(*(uint32_t*)(base + (x)))
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#define PPC_LOAD_U64(x) _byteswap_uint64(*(uint64_t*)(base + (x)))
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#define PPC_STORE_U8(x, y) *(uint8_t*)(base + (x)) = (y)
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#define PPC_STORE_U16(x, y) *(uint16_t*)(base + (x)) = _byteswap_ushort(y)
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#define PPC_STORE_U32(x, y) *(uint32_t*)(base + (x)) = _byteswap_ulong(y)
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#define PPC_STORE_U64(x, y) *(uint64_t*)(base + (x)) = _byteswap_uint64(y)
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typedef void PPCFunc(struct PPCContext& __restrict ctx, uint8_t* base);
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struct PPCRegister
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{
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union
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{
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int8_t s8;
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uint8_t u8;
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int16_t s16;
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uint16_t u16;
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int32_t s32;
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uint32_t u32;
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int64_t s64;
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uint64_t u64;
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float f32;
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double f64;
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};
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};
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struct PPCXERRegister
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{
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uint8_t so;
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uint8_t ov;
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uint8_t ca;
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};
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struct PPCCRRegister
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{
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uint8_t lt;
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uint8_t gt;
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uint8_t eq;
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union
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{
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uint8_t so;
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uint8_t un;
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};
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template<typename T>
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void compare(T left, T right, const PPCXERRegister& xer)
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{
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lt = left < right;
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gt = left > right;
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eq = left == right;
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so = xer.so;
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}
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void compare(double left, double right)
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{
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lt = left < right;
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gt = left > right;
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eq = left == right;
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un = isnan(left) || isnan(right);
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}
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};
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struct alignas(0x10) PPCVRegister
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{
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union
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{
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int8_t s8[16];
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uint8_t u8[16];
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int16_t s16[8];
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uint16_t u16[8];
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int32_t s32[4];
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uint32_t u32[4];
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int64_t s64[2];
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uint64_t u64[2];
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float f32[4];
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double f64[2];
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};
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};
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struct PPCContext
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{
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PPCFunc** fn;
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uint64_t lr;
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uint64_t ctr;
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PPCXERRegister xer;
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PPCRegister reserved;
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union
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{
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struct
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{
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PPCCRRegister cr0;
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PPCCRRegister cr1;
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PPCCRRegister cr2;
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PPCCRRegister cr3;
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PPCCRRegister cr4;
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PPCCRRegister cr5;
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PPCCRRegister cr6;
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PPCCRRegister cr7;
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};
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PPCCRRegister cr[8];
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};
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union
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{
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struct
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{
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PPCRegister r0;
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PPCRegister r1;
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PPCRegister r2;
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PPCRegister r3;
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PPCRegister r4;
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PPCRegister r5;
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PPCRegister r6;
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PPCRegister r7;
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PPCRegister r8;
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PPCRegister r9;
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PPCRegister r10;
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PPCRegister r11;
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PPCRegister r12;
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PPCRegister r13;
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PPCRegister r14;
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PPCRegister r15;
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PPCRegister r16;
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PPCRegister r17;
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PPCRegister r18;
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PPCRegister r19;
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PPCRegister r20;
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PPCRegister r21;
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PPCRegister r22;
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PPCRegister r23;
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PPCRegister r24;
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PPCRegister r25;
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PPCRegister r26;
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PPCRegister r27;
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PPCRegister r28;
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PPCRegister r29;
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PPCRegister r30;
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PPCRegister r31;
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};
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PPCRegister r[32];
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};
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union
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{
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struct
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{
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PPCRegister f0;
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PPCRegister f1;
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PPCRegister f2;
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PPCRegister f3;
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PPCRegister f4;
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PPCRegister f5;
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PPCRegister f6;
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PPCRegister f7;
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PPCRegister f8;
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PPCRegister f9;
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PPCRegister f10;
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PPCRegister f11;
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PPCRegister f12;
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PPCRegister f13;
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PPCRegister f14;
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PPCRegister f15;
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PPCRegister f16;
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PPCRegister f17;
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PPCRegister f18;
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PPCRegister f19;
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PPCRegister f20;
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PPCRegister f21;
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PPCRegister f22;
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PPCRegister f23;
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PPCRegister f24;
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PPCRegister f25;
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PPCRegister f26;
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PPCRegister f27;
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PPCRegister f28;
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PPCRegister f29;
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PPCRegister f30;
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PPCRegister f31;
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};
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PPCRegister f[32];
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};
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union
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{
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struct
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{
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PPCVRegister v0;
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PPCVRegister v1;
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PPCVRegister v2;
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PPCVRegister v3;
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PPCVRegister v4;
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PPCVRegister v5;
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PPCVRegister v6;
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PPCVRegister v7;
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PPCVRegister v8;
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PPCVRegister v9;
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PPCVRegister v10;
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PPCVRegister v11;
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PPCVRegister v12;
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PPCVRegister v13;
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PPCVRegister v14;
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PPCVRegister v15;
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PPCVRegister v16;
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PPCVRegister v17;
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PPCVRegister v18;
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PPCVRegister v19;
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PPCVRegister v20;
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PPCVRegister v21;
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PPCVRegister v22;
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PPCVRegister v23;
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PPCVRegister v24;
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PPCVRegister v25;
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PPCVRegister v26;
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PPCVRegister v27;
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PPCVRegister v28;
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PPCVRegister v29;
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PPCVRegister v30;
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PPCVRegister v31;
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PPCVRegister v32;
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PPCVRegister v33;
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PPCVRegister v34;
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PPCVRegister v35;
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PPCVRegister v36;
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PPCVRegister v37;
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PPCVRegister v38;
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PPCVRegister v39;
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PPCVRegister v40;
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PPCVRegister v41;
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PPCVRegister v42;
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PPCVRegister v43;
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PPCVRegister v44;
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PPCVRegister v45;
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PPCVRegister v46;
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PPCVRegister v47;
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PPCVRegister v48;
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PPCVRegister v49;
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PPCVRegister v50;
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PPCVRegister v51;
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PPCVRegister v52;
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PPCVRegister v53;
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PPCVRegister v54;
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PPCVRegister v55;
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PPCVRegister v56;
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PPCVRegister v57;
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PPCVRegister v58;
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PPCVRegister v59;
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PPCVRegister v60;
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PPCVRegister v61;
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PPCVRegister v62;
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PPCVRegister v63;
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PPCVRegister v64;
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PPCVRegister v65;
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PPCVRegister v66;
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PPCVRegister v67;
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PPCVRegister v68;
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PPCVRegister v69;
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PPCVRegister v70;
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PPCVRegister v71;
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PPCVRegister v72;
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PPCVRegister v73;
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PPCVRegister v74;
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PPCVRegister v75;
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PPCVRegister v76;
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PPCVRegister v77;
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PPCVRegister v78;
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PPCVRegister v79;
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PPCVRegister v80;
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PPCVRegister v81;
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PPCVRegister v82;
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PPCVRegister v83;
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PPCVRegister v84;
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PPCVRegister v85;
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PPCVRegister v86;
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PPCVRegister v87;
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PPCVRegister v88;
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PPCVRegister v89;
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PPCVRegister v90;
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PPCVRegister v91;
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PPCVRegister v92;
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PPCVRegister v93;
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PPCVRegister v94;
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PPCVRegister v95;
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PPCVRegister v96;
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PPCVRegister v97;
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PPCVRegister v98;
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PPCVRegister v99;
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PPCVRegister v100;
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PPCVRegister v101;
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PPCVRegister v102;
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PPCVRegister v103;
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PPCVRegister v104;
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PPCVRegister v105;
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PPCVRegister v106;
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PPCVRegister v107;
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PPCVRegister v108;
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PPCVRegister v109;
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PPCVRegister v110;
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PPCVRegister v111;
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PPCVRegister v112;
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PPCVRegister v113;
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PPCVRegister v114;
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PPCVRegister v115;
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PPCVRegister v116;
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PPCVRegister v117;
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PPCVRegister v118;
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PPCVRegister v119;
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PPCVRegister v120;
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PPCVRegister v121;
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PPCVRegister v122;
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PPCVRegister v123;
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PPCVRegister v124;
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PPCVRegister v125;
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PPCVRegister v126;
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PPCVRegister v127;
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};
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PPCVRegister v[128];
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};
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};
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inline __m128i _mm_adds_epu32(__m128i a, __m128i b)
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{
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return _mm_add_epi32(_mm_min_epu32(a, _mm_xor_si128(b, _mm_cmpeq_epi32(b, b))), b);
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}
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