mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
1000 lines
26 KiB
C++
1000 lines
26 KiB
C++
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AArch64 addressing mode implementation stuff.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H
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#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <capstone/platform.h>
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#include "../../MathExtras.h"
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#include <assert.h>
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#include "../../MathExtras.h"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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/// AArch64_AM - AArch64 Addressing Mode Stuff
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// CS namespace begin: AArch64_AM
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//===----------------------------------------------------------------------===//
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// Shifts
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//
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typedef enum ShiftExtendType {
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AArch64_AM_InvalidShiftExtend = -1,
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AArch64_AM_LSL = 0,
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AArch64_AM_LSR,
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AArch64_AM_ASR,
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AArch64_AM_ROR,
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AArch64_AM_MSL,
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AArch64_AM_UXTB,
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AArch64_AM_UXTH,
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AArch64_AM_UXTW,
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AArch64_AM_UXTX,
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AArch64_AM_SXTB,
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AArch64_AM_SXTH,
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AArch64_AM_SXTW,
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AArch64_AM_SXTX,
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} AArch64_AM_ShiftExtendType;
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/// getShiftName - Get the string encoding for the shift type.
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static inline const char *
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AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST)
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{
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switch (ST) {
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default:
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assert(0 && "unhandled shift type!");
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case AArch64_AM_LSL:
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return "lsl";
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case AArch64_AM_LSR:
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return "lsr";
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case AArch64_AM_ASR:
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return "asr";
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case AArch64_AM_ROR:
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return "ror";
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case AArch64_AM_MSL:
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return "msl";
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case AArch64_AM_UXTB:
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return "uxtb";
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case AArch64_AM_UXTH:
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return "uxth";
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case AArch64_AM_UXTW:
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return "uxtw";
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case AArch64_AM_UXTX:
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return "uxtx";
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case AArch64_AM_SXTB:
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return "sxtb";
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case AArch64_AM_SXTH:
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return "sxth";
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case AArch64_AM_SXTW:
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return "sxtw";
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case AArch64_AM_SXTX:
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return "sxtx";
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}
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return NULL;
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}
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/// getShiftType - Extract the shift type.
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static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm)
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{
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switch ((Imm >> 6) & 0x7) {
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default:
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return AArch64_AM_InvalidShiftExtend;
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case 0:
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return AArch64_AM_LSL;
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case 1:
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return AArch64_AM_LSR;
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case 2:
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return AArch64_AM_ASR;
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case 3:
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return AArch64_AM_ROR;
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case 4:
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return AArch64_AM_MSL;
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}
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}
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/// getShiftValue - Extract the shift value.
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static inline unsigned AArch64_AM_getShiftValue(unsigned Imm)
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{
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return Imm & 0x3f;
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}
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/// getShifterImm - Encode the shift type and amount:
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/// imm: 6-bit shift amount
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/// shifter: 000 ==> lsl
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/// 001 ==> lsr
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/// 010 ==> asr
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/// 011 ==> ror
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/// 100 ==> msl
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/// {8-6} = shifter
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/// {5-0} = imm
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static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST,
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unsigned Imm)
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{
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unsigned STEnc = 0;
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switch (ST) {
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default:
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assert(0 && "Invalid shift requested");
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case AArch64_AM_LSL:
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STEnc = 0;
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break;
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case AArch64_AM_LSR:
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STEnc = 1;
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break;
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case AArch64_AM_ASR:
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STEnc = 2;
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break;
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case AArch64_AM_ROR:
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STEnc = 3;
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break;
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case AArch64_AM_MSL:
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STEnc = 4;
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break;
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}
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return (STEnc << 6) | (Imm & 0x3f);
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}
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//===----------------------------------------------------------------------===//
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// Extends
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//
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/// getArithShiftValue - get the arithmetic shift value.
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static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm)
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{
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return Imm & 0x7;
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}
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/// getExtendType - Extract the extend type for operands of arithmetic ops.
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static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm)
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{
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switch (Imm) {
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default:
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assert(0 && "Compiler bug!");
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case 0:
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return AArch64_AM_UXTB;
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case 1:
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return AArch64_AM_UXTH;
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case 2:
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return AArch64_AM_UXTW;
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case 3:
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return AArch64_AM_UXTX;
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case 4:
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return AArch64_AM_SXTB;
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case 5:
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return AArch64_AM_SXTH;
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case 6:
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return AArch64_AM_SXTW;
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case 7:
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return AArch64_AM_SXTX;
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}
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}
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static inline AArch64_AM_ShiftExtendType
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AArch64_AM_getArithExtendType(unsigned Imm)
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{
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return AArch64_AM_getExtendType((Imm >> 3) & 0x7);
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}
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/// Mapping from extend bits to required operation:
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/// shifter: 000 ==> uxtb
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/// 001 ==> uxth
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/// 010 ==> uxtw
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/// 011 ==> uxtx
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/// 100 ==> sxtb
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/// 101 ==> sxth
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/// 110 ==> sxtw
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/// 111 ==> sxtx
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static inline unsigned
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AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET)
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{
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switch (ET) {
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default:
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assert(0 && "Invalid extend type requested");
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case AArch64_AM_UXTB:
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return 0;
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break;
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case AArch64_AM_UXTH:
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return 1;
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break;
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case AArch64_AM_UXTW:
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return 2;
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break;
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case AArch64_AM_UXTX:
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return 3;
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break;
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case AArch64_AM_SXTB:
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return 4;
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break;
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case AArch64_AM_SXTH:
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return 5;
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break;
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case AArch64_AM_SXTW:
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return 6;
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break;
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case AArch64_AM_SXTX:
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return 7;
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break;
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}
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}
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/// getArithExtendImm - Encode the extend type and shift amount for an
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/// arithmetic instruction:
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/// imm: 3-bit extend amount
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/// {5-3} = shifter
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/// {2-0} = imm3
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static inline unsigned
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AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm)
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{
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return (AArch64_AM_getExtendEncoding(ET) << 3) | (Imm & 0x7);
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}
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/// getMemDoShift - Extract the "do shift" flag value for load/store
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/// instructions.
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static inline bool AArch64_AM_getMemDoShift(unsigned Imm)
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{
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return (Imm & 0x1) != 0;
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}
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/// getExtendType - Extract the extend type for the offset operand of
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/// loads/stores.
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static inline AArch64_AM_ShiftExtendType
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AArch64_AM_getMemExtendType(unsigned Imm)
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{
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return AArch64_AM_getExtendType((Imm >> 1) & 0x7);
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}
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/// getExtendImm - Encode the extend type and amount for a load/store inst:
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/// doshift: should the offset be scaled by the access size
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/// shifter: 000 ==> uxtb
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/// 001 ==> uxth
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/// 010 ==> uxtw
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/// 011 ==> uxtx
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/// 100 ==> sxtb
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/// 101 ==> sxth
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/// 110 ==> sxtw
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/// 111 ==> sxtx
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/// {3-1} = shifter
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/// {0} = doshift
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static inline unsigned AArch64_AM_getMemExtendImm(AArch64_AM_ShiftExtendType ET,
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bool DoShift)
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{
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return (AArch64_AM_getExtendEncoding(ET) << 1) | (unsigned)DoShift;
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}
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static inline uint64_t AArch64_AM_ror(uint64_t elt, unsigned size)
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{
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return ((elt & 1) << (size - 1)) | (elt >> 1);
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}
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/// processLogicalImmediate - Determine if an immediate value can be encoded
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/// as the immediate operand of a logical instruction for the given register
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/// size. If so, return true with "encoding" set to the encoded value in
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/// the form N:immr:imms.
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static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm,
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unsigned RegSize,
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uint64_t *Encoding)
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{
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if (Imm == 0ULL || Imm == ~0ULL ||
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(RegSize != 64 &&
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(Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize)))))
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return false;
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// First, determine the element size.
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unsigned Size = RegSize;
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do {
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Size /= 2;
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uint64_t Mask = (1ULL << Size) - 1;
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if ((Imm & Mask) != ((Imm >> Size) & Mask)) {
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Size *= 2;
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break;
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}
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} while (Size > 2);
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// Second, determine the rotation to make the element be: 0^m 1^n.
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uint32_t CTO, I;
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uint64_t Mask = ((uint64_t)-1LL) >> (64 - Size);
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Imm &= Mask;
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if (isShiftedMask_64(Imm)) {
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I = CountTrailingZeros_64(Imm);
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CTO = CountTrailingOnes_64(Imm >> I);
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} else {
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Imm |= ~Mask;
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if (!isShiftedMask_64(~Imm))
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return false;
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unsigned CLO = CountLeadingOnes_64(Imm);
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I = 64 - CLO;
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CTO = CLO + CountTrailingOnes_64(Imm) - (64 - Size);
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}
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// Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
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// to our target value, where I is the number of RORs to go the opposite
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// direction.
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unsigned Immr = (Size - I) & (Size - 1);
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// If size has a 1 in the n'th bit, create a value that has zeroes in
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// bits [0, n] and ones above that.
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uint64_t NImms = ~(Size - 1) << 1;
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// Or the CTO value into the low bits, which must be below the Nth bit
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// bit mentioned above.
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NImms |= (CTO - 1);
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// Extract the seventh bit and toggle it to create the N field.
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unsigned N = ((NImms >> 6) & 1) ^ 1;
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*Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f);
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return true;
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}
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/// isLogicalImmediate - Return true if the immediate is valid for a logical
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/// immediate instruction of the given register size. Return false otherwise.
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static inline bool AArch64_AM_isLogicalImmediate(uint64_t imm, unsigned regSize)
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{
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uint64_t encoding = 0;
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return AArch64_AM_processLogicalImmediate(imm, regSize, &encoding);
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}
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/// encodeLogicalImmediate - Return the encoded immediate value for a logical
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/// immediate instruction of the given register size.
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static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm,
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unsigned regSize)
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{
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uint64_t encoding = 0;
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bool res = AArch64_AM_processLogicalImmediate(imm, regSize, &encoding);
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(void)res;
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return encoding;
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}
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/// decodeLogicalImmediate - Decode a logical immediate value in the form
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/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
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/// integer value it represents with regSize bits.
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static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val,
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unsigned regSize)
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{
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// Extract the N, imms, and immr fields.
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unsigned N = (val >> 12) & 1;
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unsigned immr = (val >> 6) & 0x3f;
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unsigned imms = val & 0x3f;
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int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
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assert(len >= 1);
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unsigned size = (1 << len);
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unsigned R = immr & (size - 1);
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unsigned S = imms & (size - 1);
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uint64_t pattern = (1ULL << (S + 1)) - 1;
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for (unsigned i = 0; i < R; ++i)
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pattern = AArch64_AM_ror(pattern, size);
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// Replicate the pattern to fill the regSize.
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while (size != regSize) {
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pattern |= (pattern << size);
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size *= 2;
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}
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return pattern;
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}
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/// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
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/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
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/// is a valid encoding for an integer value with regSize bits.
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static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val,
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unsigned regSize)
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{
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// Extract the N and imms fields needed for checking.
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unsigned N = (val >> 12) & 1;
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unsigned imms = val & 0x3f;
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if (regSize == 32 && N != 0) // undefined logical immediate encoding
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return false;
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int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
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if (len < 0) // undefined logical immediate encoding
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return false;
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unsigned size = (1 << len);
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unsigned S = imms & (size - 1);
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if (S == size - 1) // undefined logical immediate encoding
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return false;
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return true;
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}
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//===----------------------------------------------------------------------===//
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// Floating-point Immediates
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//
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static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
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{
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// We expect an 8-bit binary encoding of a floating-point number here.
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uint8_t Sign = (Imm >> 7) & 0x1;
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uint8_t Exp = (Imm >> 4) & 0x7;
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uint8_t Mantissa = Imm & 0xf;
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// 8-bit FP IEEE Float Encoding
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// abcd efgh aBbbbbbc defgh000 00000000 00000000
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//
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// where B = NOT(b);
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uint32_t I = 0;
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I |= Sign << 31;
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I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
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I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
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I |= (Exp & 0x3) << 23;
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I |= Mantissa << 19;
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return BitsToFloat(I);
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}
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//===--------------------------------------------------------------------===//
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// AdvSIMD Modified Immediates
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//===--------------------------------------------------------------------===//
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// 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh
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static inline bool AArch64_AM_isAdvSIMDModImmType1(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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((Imm & 0xffffff00ffffff00ULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm)
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{
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return (Imm & 0xffULL);
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}
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static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm)
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{
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uint64_t EncVal = Imm;
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return (EncVal << 32) | EncVal;
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}
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// 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00
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static inline bool AArch64_AM_isAdvSIMDModImmType2(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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((Imm & 0xffff00ffffff00ffULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType2(uint64_t Imm)
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{
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return (Imm & 0xff00ULL) >> 8;
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}
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static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType2(uint8_t Imm)
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{
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uint64_t EncVal = Imm;
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return (EncVal << 40) | (EncVal << 8);
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}
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// 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00
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static inline bool AArch64_AM_isAdvSIMDModImmType3(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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((Imm & 0xff00ffffff00ffffULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType3(uint64_t Imm)
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{
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return (Imm & 0xff0000ULL) >> 16;
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}
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|
|
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType3(uint8_t Imm)
|
|
{
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 48) | (EncVal << 16);
|
|
}
|
|
|
|
// abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00
|
|
static inline bool AArch64_AM_isAdvSIMDModImmType4(uint64_t Imm)
|
|
{
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
((Imm & 0x00ffffff00ffffffULL) == 0);
|
|
}
|
|
|
|
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType4(uint64_t Imm)
|
|
{
|
|
return (Imm & 0xff000000ULL) >> 24;
|
|
}
|
|
|
|
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType4(uint8_t Imm)
|
|
{
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 56) | (EncVal << 24);
|
|
}
|
|
|
|
// 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh
|
|
static inline bool AArch64_AM_isAdvSIMDModImmType5(uint64_t Imm)
|
|
{
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
(((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
|
|
((Imm & 0xff00ff00ff00ff00ULL) == 0);
|
|
}
|
|
|
|
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType5(uint64_t Imm)
|
|
{
|
|
return (Imm & 0xffULL);
|
|
}
|
|
|
|
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType5(uint8_t Imm)
|
|
{
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal;
|
|
}
|
|
|
|
// abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00
|
|
static inline bool AArch64_AM_isAdvSIMDModImmType6(uint64_t Imm)
|
|
{
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
(((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
|
|
((Imm & 0x00ff00ff00ff00ffULL) == 0);
|
|
}
|
|
|
|
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType6(uint64_t Imm)
|
|
{
|
|
return (Imm & 0xff00ULL) >> 8;
|
|
}
|
|
|
|
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType6(uint8_t Imm)
|
|
{
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8);
|
|
}
|
|
|
|
// 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF
|
|
static inline bool AArch64_AM_isAdvSIMDModImmType7(uint64_t Imm)
|
|
{
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
|
|
}
|
|
|
|
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType7(uint64_t Imm)
|
|
{
|
|
return (Imm & 0xff00ULL) >> 8;
|
|
}
|
|
|
|
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType7(uint8_t Imm)
|
|
{
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL;
|
|
}
|
|
|
|
// 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF
|
|
static inline bool AArch64_AM_isAdvSIMDModImmType8(uint64_t Imm)
|
|
{
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
|
|
}
|
|
|
|
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType8(uint8_t Imm)
|
|
{
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL;
|
|
}
|
|
|
|
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType8(uint64_t Imm)
|
|
{
|
|
return (Imm & 0x00ff0000ULL) >> 16;
|
|
}
|
|
|
|
// abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh
|
|
static inline bool AArch64_AM_isAdvSIMDModImmType9(uint64_t Imm)
|
|
{
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
|
|
((Imm >> 56) == (Imm & 0x000000ffULL));
|
|
}
|
|
|
|
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType9(uint64_t Imm)
|
|
{
|
|
return (Imm & 0xffULL);
|
|
}
|
|
|
|
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType9(uint8_t Imm)
|
|
{
|
|
uint64_t EncVal = Imm;
|
|
EncVal |= (EncVal << 8);
|
|
EncVal |= (EncVal << 16);
|
|
EncVal |= (EncVal << 32);
|
|
return EncVal;
|
|
}
|
|
|
|
// aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
|
|
// cmode: 1110, op: 1
|
|
static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm)
|
|
{
|
|
#if defined(_MSC_VER) && _MSC_VER == 1937 && !defined(__clang__) && \
|
|
defined(_M_ARM64)
|
|
// The MSVC compiler 19.37 for ARM64 has an optimization bug that
|
|
// causes an incorrect behavior with the orignal version. Work around
|
|
// by using a slightly different variation.
|
|
// https://developercommunity.visualstudio.com/t/C-ARM64-compiler-optimization-bug/10481261
|
|
constexpr uint64_t Mask = 0xFFULL;
|
|
uint64_t ByteA = (Imm >> 56) & Mask;
|
|
uint64_t ByteB = (Imm >> 48) & Mask;
|
|
uint64_t ByteC = (Imm >> 40) & Mask;
|
|
uint64_t ByteD = (Imm >> 32) & Mask;
|
|
uint64_t ByteE = (Imm >> 24) & Mask;
|
|
uint64_t ByteF = (Imm >> 16) & Mask;
|
|
uint64_t ByteG = (Imm >> 8) & Mask;
|
|
uint64_t ByteH = Imm & Mask;
|
|
|
|
return (ByteA == 0ULL || ByteA == Mask) &&
|
|
(ByteB == 0ULL || ByteB == Mask) &&
|
|
(ByteC == 0ULL || ByteC == Mask) &&
|
|
(ByteD == 0ULL || ByteD == Mask) &&
|
|
(ByteE == 0ULL || ByteE == Mask) &&
|
|
(ByteF == 0ULL || ByteF == Mask) &&
|
|
(ByteG == 0ULL || ByteG == Mask) &&
|
|
(ByteH == 0ULL || ByteH == Mask);
|
|
#else
|
|
uint64_t ByteA = Imm & 0xff00000000000000ULL;
|
|
uint64_t ByteB = Imm & 0x00ff000000000000ULL;
|
|
uint64_t ByteC = Imm & 0x0000ff0000000000ULL;
|
|
uint64_t ByteD = Imm & 0x000000ff00000000ULL;
|
|
uint64_t ByteE = Imm & 0x00000000ff000000ULL;
|
|
uint64_t ByteF = Imm & 0x0000000000ff0000ULL;
|
|
uint64_t ByteG = Imm & 0x000000000000ff00ULL;
|
|
uint64_t ByteH = Imm & 0x00000000000000ffULL;
|
|
|
|
return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&
|
|
(ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
|
|
(ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
|
|
(ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
|
|
(ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
|
|
(ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
|
|
(ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
|
|
(ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
|
|
#endif
|
|
}
|
|
|
|
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm)
|
|
{
|
|
uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0;
|
|
uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0;
|
|
uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0;
|
|
uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0;
|
|
uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0;
|
|
uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0;
|
|
uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0;
|
|
uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0;
|
|
|
|
uint8_t EncVal = BitA;
|
|
EncVal <<= 1;
|
|
EncVal |= BitB;
|
|
EncVal <<= 1;
|
|
EncVal |= BitC;
|
|
EncVal <<= 1;
|
|
EncVal |= BitD;
|
|
EncVal <<= 1;
|
|
EncVal |= BitE;
|
|
EncVal <<= 1;
|
|
EncVal |= BitF;
|
|
EncVal <<= 1;
|
|
EncVal |= BitG;
|
|
EncVal <<= 1;
|
|
EncVal |= BitH;
|
|
return EncVal;
|
|
}
|
|
|
|
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm)
|
|
{
|
|
uint64_t EncVal = 0;
|
|
if (Imm & 0x80)
|
|
EncVal |= 0xff00000000000000ULL;
|
|
if (Imm & 0x40)
|
|
EncVal |= 0x00ff000000000000ULL;
|
|
if (Imm & 0x20)
|
|
EncVal |= 0x0000ff0000000000ULL;
|
|
if (Imm & 0x10)
|
|
EncVal |= 0x000000ff00000000ULL;
|
|
if (Imm & 0x08)
|
|
EncVal |= 0x00000000ff000000ULL;
|
|
if (Imm & 0x04)
|
|
EncVal |= 0x0000000000ff0000ULL;
|
|
if (Imm & 0x02)
|
|
EncVal |= 0x000000000000ff00ULL;
|
|
if (Imm & 0x01)
|
|
EncVal |= 0x00000000000000ffULL;
|
|
return EncVal;
|
|
}
|
|
|
|
// aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00
|
|
static inline bool AArch64_AM_isAdvSIMDModImmType11(uint64_t Imm)
|
|
{
|
|
uint64_t BString = (Imm & 0x7E000000ULL) >> 25;
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
(BString == 0x1f || BString == 0x20) &&
|
|
((Imm & 0x0007ffff0007ffffULL) == 0);
|
|
}
|
|
|
|
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm)
|
|
{
|
|
uint8_t BitA = (Imm & 0x80000000ULL) != 0;
|
|
uint8_t BitB = (Imm & 0x20000000ULL) != 0;
|
|
uint8_t BitC = (Imm & 0x01000000ULL) != 0;
|
|
uint8_t BitD = (Imm & 0x00800000ULL) != 0;
|
|
uint8_t BitE = (Imm & 0x00400000ULL) != 0;
|
|
uint8_t BitF = (Imm & 0x00200000ULL) != 0;
|
|
uint8_t BitG = (Imm & 0x00100000ULL) != 0;
|
|
uint8_t BitH = (Imm & 0x00080000ULL) != 0;
|
|
|
|
uint8_t EncVal = BitA;
|
|
EncVal <<= 1;
|
|
EncVal |= BitB;
|
|
EncVal <<= 1;
|
|
EncVal |= BitC;
|
|
EncVal <<= 1;
|
|
EncVal |= BitD;
|
|
EncVal <<= 1;
|
|
EncVal |= BitE;
|
|
EncVal <<= 1;
|
|
EncVal |= BitF;
|
|
EncVal <<= 1;
|
|
EncVal |= BitG;
|
|
EncVal <<= 1;
|
|
EncVal |= BitH;
|
|
return EncVal;
|
|
}
|
|
|
|
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType11(uint8_t Imm)
|
|
{
|
|
uint64_t EncVal = 0;
|
|
if (Imm & 0x80)
|
|
EncVal |= 0x80000000ULL;
|
|
if (Imm & 0x40)
|
|
EncVal |= 0x3e000000ULL;
|
|
else
|
|
EncVal |= 0x40000000ULL;
|
|
if (Imm & 0x20)
|
|
EncVal |= 0x01000000ULL;
|
|
if (Imm & 0x10)
|
|
EncVal |= 0x00800000ULL;
|
|
if (Imm & 0x08)
|
|
EncVal |= 0x00400000ULL;
|
|
if (Imm & 0x04)
|
|
EncVal |= 0x00200000ULL;
|
|
if (Imm & 0x02)
|
|
EncVal |= 0x00100000ULL;
|
|
if (Imm & 0x01)
|
|
EncVal |= 0x00080000ULL;
|
|
return (EncVal << 32) | EncVal;
|
|
}
|
|
|
|
// aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00
|
|
static inline bool AArch64_AM_isAdvSIMDModImmType12(uint64_t Imm)
|
|
{
|
|
uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54;
|
|
return ((BString == 0xff || BString == 0x100) &&
|
|
((Imm & 0x0000ffffffffffffULL) == 0));
|
|
}
|
|
|
|
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm)
|
|
{
|
|
uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0;
|
|
uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0;
|
|
uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0;
|
|
uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0;
|
|
uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0;
|
|
uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0;
|
|
uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0;
|
|
uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0;
|
|
|
|
uint8_t EncVal = BitA;
|
|
EncVal <<= 1;
|
|
EncVal |= BitB;
|
|
EncVal <<= 1;
|
|
EncVal |= BitC;
|
|
EncVal <<= 1;
|
|
EncVal |= BitD;
|
|
EncVal <<= 1;
|
|
EncVal |= BitE;
|
|
EncVal <<= 1;
|
|
EncVal |= BitF;
|
|
EncVal <<= 1;
|
|
EncVal |= BitG;
|
|
EncVal <<= 1;
|
|
EncVal |= BitH;
|
|
return EncVal;
|
|
}
|
|
|
|
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType12(uint8_t Imm)
|
|
{
|
|
uint64_t EncVal = 0;
|
|
if (Imm & 0x80)
|
|
EncVal |= 0x8000000000000000ULL;
|
|
if (Imm & 0x40)
|
|
EncVal |= 0x3fc0000000000000ULL;
|
|
else
|
|
EncVal |= 0x4000000000000000ULL;
|
|
if (Imm & 0x20)
|
|
EncVal |= 0x0020000000000000ULL;
|
|
if (Imm & 0x10)
|
|
EncVal |= 0x0010000000000000ULL;
|
|
if (Imm & 0x08)
|
|
EncVal |= 0x0008000000000000ULL;
|
|
if (Imm & 0x04)
|
|
EncVal |= 0x0004000000000000ULL;
|
|
if (Imm & 0x02)
|
|
EncVal |= 0x0002000000000000ULL;
|
|
if (Imm & 0x01)
|
|
EncVal |= 0x0001000000000000ULL;
|
|
return (EncVal << 32) | EncVal;
|
|
}
|
|
|
|
/// Returns true if Imm is the concatenation of a repeating pattern of type T.
|
|
#define DEFINE_isSVEMaskOfIdenticalElements(T) \
|
|
static inline bool CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, \
|
|
T)(int64_t Imm) \
|
|
{ \
|
|
union { \
|
|
int64_t In; \
|
|
T Out[sizeof(int64_t) / sizeof(T)]; \
|
|
} U_Parts; \
|
|
U_Parts.In = Imm; \
|
|
T *Parts = U_Parts.Out; \
|
|
for (int i = 0; i < (sizeof(int64_t) / sizeof(T)); i++) { \
|
|
if (Parts[i] != Parts[0]) \
|
|
return false; \
|
|
} \
|
|
return true; \
|
|
}
|
|
DEFINE_isSVEMaskOfIdenticalElements(int8_t);
|
|
DEFINE_isSVEMaskOfIdenticalElements(int16_t);
|
|
DEFINE_isSVEMaskOfIdenticalElements(int32_t);
|
|
DEFINE_isSVEMaskOfIdenticalElements(int64_t);
|
|
|
|
static inline bool isSVECpyImm8(int64_t Imm)
|
|
{
|
|
bool IsImm8 = (int8_t)Imm == Imm;
|
|
|
|
return IsImm8 || (uint8_t)Imm == Imm;
|
|
}
|
|
|
|
static inline bool isSVECpyImm16(int64_t Imm)
|
|
{
|
|
bool IsImm8 = (int8_t)Imm == Imm;
|
|
bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm;
|
|
|
|
return IsImm8 || IsImm16 || (uint16_t)(Imm & ~0xff) == Imm;
|
|
}
|
|
|
|
static inline bool isSVECpyImm32(int64_t Imm)
|
|
{
|
|
bool IsImm8 = (int8_t)Imm == Imm;
|
|
bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm;
|
|
|
|
return IsImm8 || IsImm16;
|
|
}
|
|
|
|
static inline bool isSVECpyImm64(int64_t Imm)
|
|
{
|
|
bool IsImm8 = (int8_t)Imm == Imm;
|
|
bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm;
|
|
|
|
return IsImm8 || IsImm16;
|
|
}
|
|
|
|
/// Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent.
|
|
static inline bool
|
|
AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm)
|
|
{
|
|
if (isSVECpyImm64(Imm))
|
|
return false;
|
|
|
|
union {
|
|
int64_t In;
|
|
int32_t Out[2];
|
|
} U_S;
|
|
U_S.In = Imm;
|
|
int32_t *S = U_S.Out;
|
|
union {
|
|
int64_t In;
|
|
int16_t Out[4];
|
|
} U_H;
|
|
U_H.In = Imm;
|
|
int16_t *H = U_H.Out;
|
|
union {
|
|
int64_t In;
|
|
int8_t Out[8];
|
|
} U_B;
|
|
U_B.In = Imm;
|
|
int8_t *B = U_B.Out;
|
|
|
|
if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int32_t)(Imm) &&
|
|
isSVECpyImm32(S[0]))
|
|
return false;
|
|
if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int16_t)(Imm) &&
|
|
isSVECpyImm16(H[0]))
|
|
return false;
|
|
if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int8_t)(Imm) &&
|
|
isSVECpyImm8(B[0]))
|
|
return false;
|
|
return AArch64_AM_isLogicalImmediate(Imm, 64);
|
|
}
|
|
|
|
inline static bool AArch64_AM_isAnyMOVZMovAlias(uint64_t Value, int RegWidth)
|
|
{
|
|
for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16)
|
|
if ((Value & ~(0xffffULL << Shift)) == 0)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
inline static bool AArch64_AM_isMOVZMovAlias(uint64_t Value, int Shift,
|
|
int RegWidth)
|
|
{
|
|
if (RegWidth == 32)
|
|
Value &= 0xffffffffULL;
|
|
|
|
// "lsl #0" takes precedence: in practice this only affects "#0, lsl #0".
|
|
if (Value == 0 && Shift != 0)
|
|
return false;
|
|
|
|
return (Value & ~(0xffffULL << Shift)) == 0;
|
|
}
|
|
|
|
inline static bool AArch64_AM_isMOVNMovAlias(uint64_t Value, int Shift,
|
|
int RegWidth)
|
|
{
|
|
// MOVZ takes precedence over MOVN.
|
|
if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth))
|
|
return false;
|
|
|
|
Value = ~Value;
|
|
if (RegWidth == 32)
|
|
Value &= 0xffffffffULL;
|
|
|
|
return AArch64_AM_isMOVZMovAlias(Value, Shift, RegWidth);
|
|
}
|
|
|
|
inline static bool AArch64_AM_isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
|
|
{
|
|
if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth))
|
|
return true;
|
|
|
|
// It's not a MOVZ, but it might be a MOVN.
|
|
Value = ~Value;
|
|
if (RegWidth == 32)
|
|
Value &= 0xffffffffULL;
|
|
|
|
return AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth);
|
|
}
|
|
|
|
// CS namespace end: AArch64_AM
|
|
|
|
// end namespace AArch64_AM
|
|
|
|
// end namespace llvm
|
|
|
|
#endif
|