mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-10 09:35:06 +00:00
119 lines
4.4 KiB
YAML
119 lines
4.4 KiB
YAML
test_cases:
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input:
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bytes: [ 0x82, 0xee, 0x07, 0x0f, 0x92, 0xee, 0x07, 0x0f, 0xa2, 0xee, 0x07, 0x0f, 0x82, 0xfe, 0x07, 0x0f, 0x92, 0xfe, 0x07, 0x0f, 0xa2, 0xfe, 0x07, 0x0f, 0xf5, 0xee, 0x00, 0xef, 0xf5, 0xee, 0x0c, 0x0f, 0xf5, 0xee, 0x20, 0xef, 0xc9, 0xee, 0x04, 0x0f, 0x89, 0xfe, 0x02, 0x0f, 0xe2, 0xee, 0x80, 0xef, 0xe6, 0xee, 0x80, 0xef, 0xea, 0xee, 0x84, 0xef, 0xe2, 0xfe, 0x80, 0x0f, 0xea, 0xfe, 0x86, 0xaf, 0xe4, 0xee, 0x80, 0x0f, 0xe0, 0xee, 0x82, 0x0f, 0xe8, 0xee, 0x82, 0xef, 0xe2, 0xee, 0x08, 0xef, 0xe6, 0xee, 0x00, 0xef, 0xea, 0xee, 0x02, 0x1f, 0xe2, 0xfe, 0x08, 0x0f, 0xe6, 0xfe, 0x02, 0x0f, 0xea, 0xfe, 0x00, 0x1f, 0xe0, 0xee, 0x0c, 0xef, 0xe4, 0xee, 0x0c, 0x0f, 0xe8, 0xee, 0x0e, 0xaf, 0xf0, 0xee, 0x0e, 0xee, 0xf1, 0xee, 0x08, 0xee, 0xf0, 0xfe, 0x0e, 0xee, 0xf1, 0xfe, 0x00, 0xee, 0xf0, 0xee, 0x28, 0xee, 0xf0, 0xee, 0x0e, 0x1e, 0xf0, 0xee, 0x2e, 0xfe, 0xf6, 0xee, 0x00, 0xef, 0xf2, 0xfe, 0x0e, 0xef, 0x8c, 0xee, 0x04, 0xef, 0x8a, 0xfe, 0x04, 0xef, 0x8a, 0xfe, 0x04, 0xef, 0x86, 0xee, 0x20, 0xff, 0xdc, 0xfe, 0x0b, 0xee, 0xf0, 0xee, 0x07, 0xee, 0x8c, 0xee, 0x04, 0xef, 0x8a, 0xfe, 0x04, 0xef, 0x86, 0xee, 0x2c, 0xef, 0x8e, 0xfe, 0x22, 0xef, 0xf0, 0xee, 0x07, 0xee, 0xf5, 0xee, 0x0d, 0xee, 0xf2, 0xee, 0x29, 0xfe, 0xf0, 0xee, 0x0e, 0xee, 0x88, 0xee, 0x02, 0xee, 0xd9, 0xee, 0x02, 0xee, 0x8f, 0xee, 0x0c, 0x0e, 0xda, 0xfe, 0x08, 0xee ]
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arch: "CS_ARCH_ARM"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
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expected:
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insns:
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asm_text: "vabav.s8 r0, q1, q3"
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asm_text: "vabav.s16 r0, q1, q3"
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asm_text: "vabav.s32 r0, q1, q3"
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asm_text: "vabav.u8 r0, q1, q3"
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asm_text: "vabav.u16 r0, q1, q3"
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asm_text: "vabav.u32 r0, q1, q3"
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asm_text: "vaddv.s16 lr, q0"
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asm_text: "vaddv.s16 r0, q6"
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asm_text: "vaddva.s16 lr, q0"
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asm_text: "vaddlv.s32 r0, r9, q2"
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asm_text: "vaddlv.u32 r0, r1, q1"
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asm_text: "vminv.s8 lr, q0"
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asm_text: "vminv.s16 lr, q0"
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asm_text: "vminv.s32 lr, q2"
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asm_text: "vminv.u8 r0, q0"
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asm_text: "vminv.u32 r10, q3"
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asm_text: "vminav.s16 r0, q0"
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asm_text: "vminav.s8 r0, q1"
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asm_text: "vminav.s32 lr, q1"
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asm_text: "vmaxv.s8 lr, q4"
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asm_text: "vmaxv.s16 lr, q0"
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asm_text: "vmaxv.s32 r1, q1"
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asm_text: "vmaxv.u8 r0, q4"
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asm_text: "vmaxv.u16 r0, q1"
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asm_text: "vmaxv.u32 r1, q0"
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asm_text: "vmaxav.s8 lr, q6"
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asm_text: "vmaxav.s16 r0, q6"
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asm_text: "vmaxav.s32 r10, q7"
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asm_text: "vmlav.s16 lr, q0, q7"
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asm_text: "vmlav.s32 lr, q0, q4"
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asm_text: "vmlav.u16 lr, q0, q7"
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asm_text: "vmlav.u32 lr, q0, q0"
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asm_text: "vmlava.s16 lr, q0, q4"
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asm_text: "vmladavx.s16 r0, q0, q7"
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asm_text: "vmladavax.s16 lr, q0, q7"
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asm_text: "vmlav.s8 lr, q3, q0"
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asm_text: "vmlav.u8 lr, q1, q7"
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asm_text: "vrmlalvh.s32 lr, r1, q6, q2"
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asm_text: "vrmlalvh.u32 lr, r1, q5, q2"
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asm_text: "vrmlalvh.u32 lr, r1, q5, q2"
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asm_text: "vrmlaldavhax.s32 lr, r1, q3, q0"
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asm_text: "vrmlsldavh.s32 lr, r11, q6, q5"
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asm_text: "vmlsdav.s16 lr, q0, q3"
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asm_text: "vrmlalvh.s32 lr, r1, q6, q2"
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asm_text: "vrmlalvh.u32 lr, r1, q5, q2"
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asm_text: "vrmlalvha.s32 lr, r1, q3, q6"
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asm_text: "vrmlalvha.u32 lr, r1, q7, q1"
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asm_text: "vmlsdav.s16 lr, q0, q3"
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asm_text: "vmlsdav.s32 lr, q2, q6"
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asm_text: "vmlsdavax.s16 lr, q1, q4"
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asm_text: "vmlav.s16 lr, q0, q7"
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asm_text: "vmlalv.s16 lr, r1, q4, q1"
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asm_text: "vmlalv.s32 lr, r11, q4, q1"
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asm_text: "vmlalv.s32 r0, r1, q7, q6"
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asm_text: "vmlalv.u16 lr, r11, q5, q4"
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