mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-12 02:25:08 +00:00
125 lines
4.3 KiB
YAML
125 lines
4.3 KiB
YAML
test_cases:
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input:
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bytes: [ 0xa0, 0x03, 0xf1, 0xf2, 0xa0, 0x05, 0xf1, 0xf2, 0xe0, 0x03, 0xf2, 0xf2, 0xe0, 0x07, 0xf2, 0xf2, 0xa0, 0x06, 0xf1, 0xf2, 0xe0, 0x0c, 0xf2, 0xf2, 0xe0, 0x08, 0xf2, 0xf2, 0xa0, 0x13, 0xf1, 0xf2, 0x0b, 0x75, 0xb7, 0xf2, 0x60, 0x63, 0xb6, 0xf2, 0xc8, 0x27, 0xf2, 0xf2, 0x2a, 0x16, 0xb1, 0xf2, 0x60, 0xac, 0xba, 0xf2, 0x60, 0xa8, 0xba, 0xf2, 0xa0, 0x10, 0xf2, 0xf3, 0xa0, 0x10, 0xf6, 0xf3, 0xa0, 0x10, 0xfa, 0xf3, 0xe0, 0x20, 0xf2, 0xf3, 0xe0, 0x20, 0xf6, 0xf3, 0xe0, 0x20, 0xfa, 0xf3, 0x20, 0x11, 0xf2, 0xf3, 0x20, 0x11, 0xf6, 0xf3, 0x60, 0x21, 0xf2, 0xf3, 0x60, 0x21, 0xf6, 0xf3, 0x60, 0x21, 0xfa, 0xf3, 0xa0, 0x11, 0xf2, 0xf3, 0xa0, 0x11, 0xf6, 0xf3, 0xe0, 0x21, 0xf2, 0xf3, 0xe0, 0x21, 0xf6, 0xf3, 0xe0, 0x21, 0xfa, 0xf3, 0x83, 0x20, 0xba, 0xf3, 0x83, 0x20, 0xba, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3 ]
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arch: "CS_ARCH_ARM"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
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expected:
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insns:
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asm_text: "vext.8 d16, d17, d16, #3"
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asm_text: "vext.8 d16, d17, d16, #5"
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asm_text: "vext.8 q8, q9, q8, #3"
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asm_text: "vext.8 q8, q9, q8, #7"
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asm_text: "vext.16 d16, d17, d16, #3"
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asm_text: "vext.32 q8, q9, q8, #3"
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asm_text: "vext.64 q8, q9, q8, #1"
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asm_text: "vext.8 d17, d17, d16, #3"
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asm_text: "vext.8 d7, d7, d11, #5"
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asm_text: "vext.8 q3, q3, q8, #3"
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asm_text: "vext.8 q9, q9, q4, #7"
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asm_text: "vext.16 d1, d1, d26, #3"
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asm_text: "vext.32 q5, q5, q8, #3"
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asm_text: "vext.64 q5, q5, q8, #1"
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asm_text: "vtrn.8 d17, d16"
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asm_text: "vtrn.16 d17, d16"
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asm_text: "vtrn.32 d17, d16"
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asm_text: "vtrn.8 q9, q8"
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asm_text: "vtrn.16 q9, q8"
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asm_text: "vtrn.32 q9, q8"
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asm_text: "vuzp.8 d17, d16"
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asm_text: "vuzp.16 d17, d16"
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asm_text: "vuzp.8 q9, q8"
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asm_text: "vuzp.16 q9, q8"
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asm_text: "vuzp.32 q9, q8"
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asm_text: "vzip.8 d17, d16"
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asm_text: "vzip.16 d17, d16"
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asm_text: "vzip.8 q9, q8"
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asm_text: "vzip.16 q9, q8"
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asm_text: "vzip.32 q9, q8"
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asm_text: "vtrn.32 d2, d3"
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asm_text: "vtrn.32 d2, d3"
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asm_text: "vtrn.8 d3, d9"
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asm_text: "vtrn.8 d3, d9"
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asm_text: "vtrn.8 d3, d9"
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asm_text: "vtrn.8 d3, d9"
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asm_text: "vtrn.16 d3, d9"
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asm_text: "vtrn.16 d3, d9"
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asm_text: "vtrn.16 d3, d9"
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asm_text: "vtrn.16 d3, d9"
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asm_text: "vtrn.32 d3, d9"
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asm_text: "vtrn.32 d3, d9"
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asm_text: "vtrn.32 d3, d9"
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asm_text: "vtrn.32 d3, d9"
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asm_text: "vtrn.32 d3, d9"
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asm_text: "vtrn.8 q14, q6"
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asm_text: "vtrn.8 q14, q6"
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asm_text: "vtrn.8 q14, q6"
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asm_text: "vtrn.8 q14, q6"
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asm_text: "vtrn.16 q14, q6"
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asm_text: "vtrn.16 q14, q6"
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asm_text: "vtrn.16 q14, q6"
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asm_text: "vtrn.16 q14, q6"
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asm_text: "vtrn.32 q14, q6"
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asm_text: "vtrn.32 q14, q6"
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asm_text: "vtrn.32 q14, q6"
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asm_text: "vtrn.32 q14, q6"
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asm_text: "vtrn.32 q14, q6"
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