mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
500 lines
14 KiB
C
500 lines
14 KiB
C
/* Capstone Disassembly Engine */
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/* By Jiajie Chen <c@jia.je>, 2024 */
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/* Yanglin Xun <1109673069@qq.com>, 2024 */
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#ifdef CAPSTONE_HAS_LOONGARCH
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#include <stdio.h>
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#include <string.h>
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#include <capstone/capstone.h>
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#include <capstone/loongarch.h>
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#include "../../Mapping.h"
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#include "../../MCDisassembler.h"
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#include "../../cs_priv.h"
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#include "../../cs_simple_types.h"
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#include "LoongArchMapping.h"
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#include "LoongArchLinkage.h"
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#define GET_REGINFO_ENUM
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#define GET_REGINFO_MC_DESC
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#include "LoongArchGenRegisterInfo.inc"
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#define GET_INSTRINFO_ENUM
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#include "LoongArchGenInstrInfo.inc"
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void LoongArch_init_mri(MCRegisterInfo *MRI)
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{
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MCRegisterInfo_InitMCRegisterInfo(MRI, LoongArchRegDesc,
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sizeof(LoongArchRegDesc), 0, 0,
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LoongArchMCRegisterClasses,
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ARR_SIZE(LoongArchMCRegisterClasses),
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0, 0, LoongArchRegDiffLists, 0,
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LoongArchSubRegIdxLists,
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ARR_SIZE(LoongArchSubRegIdxLists), 0);
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}
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const char *LoongArch_reg_name(csh handle, unsigned int reg)
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{
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int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax;
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if (syntax_opt & CS_OPT_SYNTAX_NOREGNAME) {
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return LoongArch_LLVM_getRegisterName(reg,
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LoongArch_NoRegAltName);
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}
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return LoongArch_LLVM_getRegisterName(reg, LoongArch_RegAliasName);
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}
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void LoongArch_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
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{
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// Not used by LoongArch. Information is set after disassembly.
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}
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static const char *const insn_name_maps[] = {
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#include "LoongArchGenCSMappingInsnName.inc"
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};
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const char *LoongArch_insn_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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if (id < ARR_SIZE(insn_name_maps))
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return insn_name_maps[id];
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// not found
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return NULL;
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#else
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return NULL;
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#endif
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}
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#ifndef CAPSTONE_DIET
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static const name_map group_name_maps[] = {
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{ LOONGARCH_GRP_INVALID, NULL },
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{ LOONGARCH_GRP_JUMP, "jump" },
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{ LOONGARCH_GRP_CALL, "call" },
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{ LOONGARCH_GRP_RET, "return" },
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{ LOONGARCH_GRP_INT, "int" },
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{ LOONGARCH_GRP_IRET, "iret" },
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{ LOONGARCH_GRP_PRIVILEGE, "privilege" },
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{ LOONGARCH_GRP_BRANCH_RELATIVE, "branch_relative" },
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// architecture-specific groups
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#include "LoongArchGenCSFeatureName.inc"
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};
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#endif
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const char *LoongArch_group_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
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#else
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return NULL;
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#endif
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}
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void LoongArch_reg_access(const cs_insn *insn, cs_regs regs_read,
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uint8_t *regs_read_count, cs_regs regs_write,
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uint8_t *regs_write_count)
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{
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uint8_t i;
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uint8_t read_count, write_count;
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cs_loongarch *loongarch = &(insn->detail->loongarch);
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read_count = insn->detail->regs_read_count;
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write_count = insn->detail->regs_write_count;
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// implicit registers
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memcpy(regs_read, insn->detail->regs_read,
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read_count * sizeof(insn->detail->regs_read[0]));
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memcpy(regs_write, insn->detail->regs_write,
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write_count * sizeof(insn->detail->regs_write[0]));
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// explicit registers
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for (i = 0; i < loongarch->op_count; i++) {
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cs_loongarch_op *op = &(loongarch->operands[i]);
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switch ((int)op->type) {
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case LOONGARCH_OP_REG:
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if ((op->access & CS_AC_READ) &&
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!arr_exist(regs_read, read_count, op->reg)) {
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regs_read[read_count] = (uint16_t)op->reg;
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read_count++;
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}
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if ((op->access & CS_AC_WRITE) &&
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!arr_exist(regs_write, write_count, op->reg)) {
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regs_write[write_count] = (uint16_t)op->reg;
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write_count++;
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}
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break;
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case LOONGARCH_OP_MEM:
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// registers appeared in memory references always being read
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if ((op->mem.base != LOONGARCH_REG_INVALID) &&
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!arr_exist(regs_read, read_count, op->mem.base)) {
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regs_read[read_count] = (uint16_t)op->mem.base;
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read_count++;
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}
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if ((insn->detail->writeback) &&
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(op->mem.base != LOONGARCH_REG_INVALID) &&
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!arr_exist(regs_write, write_count, op->mem.base)) {
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regs_write[write_count] =
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(uint16_t)op->mem.base;
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write_count++;
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}
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default:
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break;
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}
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}
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*regs_read_count = read_count;
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*regs_write_count = write_count;
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}
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const insn_map loongarch_insns[] = {
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#include "LoongArchGenCSMappingInsn.inc"
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};
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void LoongArch_rewrite_memory_operand(MCInst *MI)
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{
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// rewrite base + disp operands to memory operands in memory instructions
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// convert e.g.
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// ld.d $t3, $t2, 0x410
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// op_count: 3
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// operands[0].type: REG = t3
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// operands[0].access: WRITE
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// operands[1].type: REG = t2
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// operands[1].access: READ
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// operands[2].type: IMM = 0x410
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// operands[2].access: READ
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// to:
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// op_count: 3
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// operands[0].type: REG = t3
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// operands[0].access: WRITE
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// operands[1].type: MEM
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// operands[1].mem.base: REG = t2
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// operands[1].mem.disp: 0x410
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// operands[1].access: READ
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if (!detail_is_set(MI))
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return;
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const loongarch_suppl_info *suppl_info =
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map_get_suppl_info(MI, loongarch_insns);
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if (suppl_info->memory_access == CS_AC_INVALID) {
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// not memory instruction
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return;
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}
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// handle special cases
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unsigned int base;
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switch (MI->flat_insn->id) {
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case LOONGARCH_INS_SC_Q:
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case LOONGARCH_INS_LLACQ_W:
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case LOONGARCH_INS_LLACQ_D:
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case LOONGARCH_INS_SCREL_W:
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case LOONGARCH_INS_SCREL_D:
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// last register rj is memory operand
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LoongArch_get_detail_op(MI, -1)->type = LOONGARCH_OP_MEM;
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base = LoongArch_get_detail_op(MI, -1)->reg;
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LoongArch_get_detail_op(MI, -1)->mem.base = base;
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LoongArch_get_detail_op(MI, -1)->access =
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suppl_info->memory_access;
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return;
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case LOONGARCH_INS_LDGT_B:
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case LOONGARCH_INS_LDGT_H:
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case LOONGARCH_INS_LDGT_W:
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case LOONGARCH_INS_LDGT_D:
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case LOONGARCH_INS_LDLE_B:
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case LOONGARCH_INS_LDLE_H:
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case LOONGARCH_INS_LDLE_W:
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case LOONGARCH_INS_LDLE_D:
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case LOONGARCH_INS_STGT_B:
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case LOONGARCH_INS_STGT_H:
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case LOONGARCH_INS_STGT_W:
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case LOONGARCH_INS_STGT_D:
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case LOONGARCH_INS_STLE_B:
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case LOONGARCH_INS_STLE_H:
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case LOONGARCH_INS_STLE_W:
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case LOONGARCH_INS_STLE_D:
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case LOONGARCH_INS_FLDLE_S:
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case LOONGARCH_INS_FLDLE_D:
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case LOONGARCH_INS_FLDGT_S:
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case LOONGARCH_INS_FLDGT_D:
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case LOONGARCH_INS_FSTLE_S:
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case LOONGARCH_INS_FSTLE_D:
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case LOONGARCH_INS_FSTGT_S:
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case LOONGARCH_INS_FSTGT_D:
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// second register rj is memory operand
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LoongArch_get_detail_op(MI, -2)->type = LOONGARCH_OP_MEM;
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base = LoongArch_get_detail_op(MI, -2)->reg;
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LoongArch_get_detail_op(MI, -2)->mem.base = base;
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LoongArch_get_detail_op(MI, -2)->access =
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suppl_info->memory_access;
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return;
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default:
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break;
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}
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switch (suppl_info->form) {
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case LOONGARCH_INSN_FORM_FMT2RI12: // ld, ldl, ldr, st, stl, str
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case LOONGARCH_INSN_FORM_FMT2RI14: // ll, sc, ldptr, stptr
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case LOONGARCH_INSN_FORM_FMT2RI9_VRI: // vldrepl.d
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case LOONGARCH_INSN_FORM_FMT2RI10_VRI: // vldrepl.w
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case LOONGARCH_INSN_FORM_FMT2RI11_VRI: // vldrepl.h
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case LOONGARCH_INSN_FORM_FMT2RI12_VRI: // vld, vldrepl, vst
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case LOONGARCH_INSN_FORM_FMT2RI8I1_VRII: // vstelm.d
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case LOONGARCH_INSN_FORM_FMT2RI8I2_VRII: // vstelm.w
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case LOONGARCH_INSN_FORM_FMT2RI8I3_VRII: // vstelm.h
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case LOONGARCH_INSN_FORM_FMT2RI8I4_VRII: // vstelm.b
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case LOONGARCH_INSN_FORM_FMT2RI9_XRI: // xvldrepl.d
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case LOONGARCH_INSN_FORM_FMT2RI10_XRI: // xvldrepl.w
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case LOONGARCH_INSN_FORM_FMT2RI11_XRI: // xvldrepl.h
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case LOONGARCH_INSN_FORM_FMT2RI12_XRI: // xvld, xvldrepl, xvst
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case LOONGARCH_INSN_FORM_FMT2RI8I2_XRII: // xvstelm.d
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case LOONGARCH_INSN_FORM_FMT2RI8I3_XRII: // xvstelm.w
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case LOONGARCH_INSN_FORM_FMT2RI8I4_XRII: // xvstelm.h
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case LOONGARCH_INSN_FORM_FMT2RI8I5_XRII: // xvstelm.b
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case LOONGARCH_INSN_FORM_FMTPRELD: // preld
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case LOONGARCH_INSN_FORM_FPFMT2RI12: // fld, fst
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// immediate offset
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LoongArch_get_detail_op(MI, -2)->type = LOONGARCH_OP_MEM;
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base = LoongArch_get_detail_op(MI, -2)->reg;
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LoongArch_get_detail_op(MI, -2)->mem.base = base;
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LoongArch_get_detail_op(MI, -2)->mem.disp =
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LoongArch_get_detail_op(MI, -1)->imm;
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LoongArch_get_detail_op(MI, -2)->access =
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suppl_info->memory_access;
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LoongArch_dec_op_count(MI);
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break;
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case LOONGARCH_INSN_FORM_FMT3R: // ldx, stx, amo
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if (suppl_info->memory_access == CS_AC_READ_WRITE) {
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// amo: read + write
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// last register rj is memory operand
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LoongArch_get_detail_op(MI, -1)->type =
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LOONGARCH_OP_MEM;
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base = LoongArch_get_detail_op(MI, -1)->reg;
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LoongArch_get_detail_op(MI, -1)->mem.base = base;
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LoongArch_get_detail_op(MI, -1)->access =
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suppl_info->memory_access;
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break;
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}
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// fallthrough
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case LOONGARCH_INSN_FORM_FPFMTMEM: // fldx, fstx
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case LOONGARCH_INSN_FORM_FMT3R_VRR: // vldx, vstx
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case LOONGARCH_INSN_FORM_FMT3R_XRR: // xvldx, xvstx
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case LOONGARCH_INSN_FORM_FMTPRELDX: // preldx
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// register offset
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LoongArch_get_detail_op(MI, -2)->type = LOONGARCH_OP_MEM;
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base = LoongArch_get_detail_op(MI, -2)->reg;
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LoongArch_get_detail_op(MI, -2)->mem.base = base;
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LoongArch_get_detail_op(MI, -2)->mem.index =
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LoongArch_get_detail_op(MI, -1)->reg;
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LoongArch_get_detail_op(MI, -2)->access =
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suppl_info->memory_access;
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LoongArch_dec_op_count(MI);
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break;
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default:
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assert(0 && "Unknown LoongArch memory instruction");
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break;
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}
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}
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void LoongArch_set_instr_map_data(MCInst *MI)
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{
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map_cs_id(MI, loongarch_insns, ARR_SIZE(loongarch_insns));
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map_implicit_reads(MI, loongarch_insns);
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map_implicit_writes(MI, loongarch_insns);
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map_groups(MI, loongarch_insns);
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const loongarch_suppl_info *suppl_info =
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map_get_suppl_info(MI, loongarch_insns);
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if (suppl_info) {
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LoongArch_get_detail(MI)->format = suppl_info->form;
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}
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}
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bool LoongArch_getInstruction(csh handle, const uint8_t *code, size_t code_len,
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MCInst *instr, uint16_t *size, uint64_t address,
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void *info)
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{
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uint64_t temp_size;
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LoongArch_init_cs_detail(instr);
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bool Result = LoongArch_LLVM_getInstruction(instr, &temp_size, code,
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code_len, address, info) !=
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MCDisassembler_Fail;
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LoongArch_set_instr_map_data(instr);
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*size = temp_size;
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return Result;
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}
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/// Adds group to the instruction which are not defined in LLVM.
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static void LoongArch_add_cs_groups(MCInst *MI)
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{
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if (!MI->flat_insn->detail)
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return;
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unsigned Opcode = MI->flat_insn->id;
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cs_loongarch *loongarch = &(MI->flat_insn->detail->loongarch);
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switch (Opcode) {
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default:
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return;
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case LOONGARCH_INS_BL:
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add_group(MI, LOONGARCH_GRP_CALL);
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break;
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case LOONGARCH_INS_JIRL:
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if (loongarch->op_count == 3 &&
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loongarch->operands[0].reg == LOONGARCH_REG_RA) {
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// call: jirl ra, rj, offs16
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add_group(MI, LOONGARCH_GRP_CALL);
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} else if (loongarch->op_count == 0) {
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// ret
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add_group(MI, LOONGARCH_GRP_RET);
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} else if (loongarch->op_count == 1) {
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// jr rj
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add_group(MI, LOONGARCH_GRP_JUMP);
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}
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break;
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case LOONGARCH_INS_B:
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case LOONGARCH_INS_BCEQZ:
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case LOONGARCH_INS_BEQ:
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case LOONGARCH_INS_BEQZ:
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case LOONGARCH_INS_BGE:
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case LOONGARCH_INS_BGEU:
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case LOONGARCH_INS_BLT:
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case LOONGARCH_INS_BLTU:
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case LOONGARCH_INS_BNE:
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case LOONGARCH_INS_BNEZ:
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add_group(MI, LOONGARCH_GRP_JUMP);
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add_group(MI, LOONGARCH_GRP_BRANCH_RELATIVE);
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break;
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case LOONGARCH_INS_SYSCALL:
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add_group(MI, LOONGARCH_GRP_INT);
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break;
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case LOONGARCH_INS_ERTN:
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add_group(MI, LOONGARCH_GRP_IRET);
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add_group(MI, LOONGARCH_GRP_PRIVILEGE);
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break;
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case LOONGARCH_INS_CSRXCHG:
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case LOONGARCH_INS_CACOP:
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case LOONGARCH_INS_LDDIR:
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case LOONGARCH_INS_LDPTE:
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case LOONGARCH_INS_IOCSRRD_B:
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case LOONGARCH_INS_IOCSRRD_H:
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case LOONGARCH_INS_IOCSRRD_W:
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case LOONGARCH_INS_IOCSRRD_D:
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case LOONGARCH_INS_IOCSRWR_B:
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case LOONGARCH_INS_IOCSRWR_H:
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case LOONGARCH_INS_IOCSRWR_W:
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case LOONGARCH_INS_IOCSRWR_D:
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case LOONGARCH_INS_TLBCLR:
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case LOONGARCH_INS_TLBFLUSH:
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case LOONGARCH_INS_TLBSRCH:
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case LOONGARCH_INS_TLBRD:
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case LOONGARCH_INS_TLBWR:
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case LOONGARCH_INS_INVTLB:
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add_group(MI, LOONGARCH_GRP_PRIVILEGE);
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break;
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}
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}
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void LoongArch_printer(MCInst *MI, SStream *O,
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void * /* MCRegisterInfo* */ info)
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{
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MCRegisterInfo *MRI = (MCRegisterInfo *)info;
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MI->MRI = MRI;
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LoongArch_LLVM_printInst(MI, MI->address, "", O);
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LoongArch_rewrite_memory_operand(MI);
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LoongArch_add_cs_groups(MI);
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}
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void LoongArch_setup_op(cs_loongarch_op *op)
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{
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memset(op, 0, sizeof(cs_loongarch_op));
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op->type = LOONGARCH_OP_INVALID;
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}
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void LoongArch_init_cs_detail(MCInst *MI)
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{
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if (detail_is_set(MI)) {
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unsigned int i;
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memset(get_detail(MI), 0,
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offsetof(cs_detail, loongarch) + sizeof(cs_loongarch));
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for (i = 0; i < ARR_SIZE(LoongArch_get_detail(MI)->operands);
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i++)
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LoongArch_setup_op(
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&LoongArch_get_detail(MI)->operands[i]);
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}
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}
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static const map_insn_ops insn_operands[] = {
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#include "LoongArchGenCSMappingInsnOp.inc"
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};
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void LoongArch_set_detail_op_imm(MCInst *MI, unsigned OpNum,
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loongarch_op_type ImmType, int64_t Imm)
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{
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if (!detail_is_set(MI))
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return;
|
|
assert((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM);
|
|
assert(ImmType == LOONGARCH_OP_IMM);
|
|
|
|
LoongArch_get_detail_op(MI, 0)->type = ImmType;
|
|
LoongArch_get_detail_op(MI, 0)->imm = Imm;
|
|
LoongArch_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
|
|
LoongArch_inc_op_count(MI);
|
|
}
|
|
|
|
void LoongArch_set_detail_op_reg(MCInst *MI, unsigned OpNum, loongarch_reg Reg)
|
|
{
|
|
if (!detail_is_set(MI))
|
|
return;
|
|
assert((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
|
|
|
|
LoongArch_get_detail_op(MI, 0)->type = LOONGARCH_OP_REG;
|
|
LoongArch_get_detail_op(MI, 0)->reg = Reg;
|
|
LoongArch_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
|
|
LoongArch_inc_op_count(MI);
|
|
}
|
|
|
|
void LoongArch_add_cs_detail(MCInst *MI, int /* loongarch_op_group */ op_group,
|
|
va_list args)
|
|
{
|
|
if (!detail_is_set(MI))
|
|
return;
|
|
|
|
unsigned OpNum = va_arg(args, unsigned);
|
|
// Handle memory operands later
|
|
cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
|
|
|
|
// Fill cs_detail
|
|
switch (op_group) {
|
|
default:
|
|
printf("ERROR: Operand group %d not handled!\n", op_group);
|
|
assert(0);
|
|
case LOONGARCH_OP_GROUP_OPERAND:
|
|
if (op_type == CS_OP_IMM) {
|
|
LoongArch_set_detail_op_imm(MI, OpNum, LOONGARCH_OP_IMM,
|
|
MCInst_getOpVal(MI, OpNum));
|
|
} else if (op_type == CS_OP_REG) {
|
|
LoongArch_set_detail_op_reg(MI, OpNum,
|
|
MCInst_getOpVal(MI, OpNum));
|
|
} else
|
|
assert(0 && "Op type not handled.");
|
|
break;
|
|
case LOONGARCH_OP_GROUP_ATOMICMEMOP:
|
|
assert(op_type == CS_OP_REG);
|
|
// converted to MEM operand later in LoongArch_rewrite_memory_operand
|
|
LoongArch_set_detail_op_reg(MI, OpNum,
|
|
MCInst_getOpVal(MI, OpNum));
|
|
break;
|
|
}
|
|
}
|
|
|
|
#endif
|