mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
1021 lines
22 KiB
YAML
1021 lines
22 KiB
YAML
![]() |
test_cases:
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input:
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bytes: [ 0xe0, 0xff, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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asm_text: "uqdecw x0"
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input:
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bytes: [ 0xe0, 0xff, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0"
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-
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input:
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bytes: [ 0xe0, 0xff, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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asm_text: "uqdecw x0"
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input:
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bytes: [ 0xe0, 0xff, 0xbf, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, all, mul #16"
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input:
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bytes: [ 0xe0, 0xff, 0xa0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw w0"
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-
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input:
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bytes: [ 0xe0, 0xff, 0xa0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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asm_text: "uqdecw w0"
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-
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input:
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bytes: [ 0xe0, 0xff, 0xa0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw w0"
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input:
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bytes: [ 0xe0, 0xff, 0xaf, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw w0, all, mul #16"
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-
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input:
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bytes: [ 0x00, 0xfc, 0xa0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw w0, pow2"
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input:
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bytes: [ 0x00, 0xfc, 0xaf, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw w0, pow2, mul #16"
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-
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input:
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bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw z0.s"
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input:
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bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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asm_text: "uqdecw z0.s"
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input:
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bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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asm_text: "uqdecw z0.s"
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input:
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bytes: [ 0xe0, 0xcf, 0xaf, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw z0.s, all, mul #16"
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-
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input:
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bytes: [ 0x00, 0xcc, 0xa0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw z0.s, pow2"
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input:
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bytes: [ 0x00, 0xcc, 0xaf, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw z0.s, pow2, mul #16"
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input:
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bytes: [ 0x00, 0xfc, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, pow2"
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-
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input:
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bytes: [ 0x20, 0xfc, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, vl1"
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-
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input:
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bytes: [ 0x40, 0xfc, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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asm_text: "uqdecw x0, vl2"
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-
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input:
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bytes: [ 0x60, 0xfc, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, vl3"
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-
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input:
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bytes: [ 0x80, 0xfc, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, vl4"
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-
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input:
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bytes: [ 0xa0, 0xfc, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, vl5"
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-
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input:
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bytes: [ 0xc0, 0xfc, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, vl6"
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-
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input:
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bytes: [ 0xe0, 0xfc, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, vl7"
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-
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input:
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bytes: [ 0x00, 0xfd, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, vl8"
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-
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input:
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bytes: [ 0x20, 0xfd, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, vl16"
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-
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input:
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bytes: [ 0x40, 0xfd, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, vl32"
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-
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input:
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bytes: [ 0x60, 0xfd, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, vl64"
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-
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input:
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bytes: [ 0x80, 0xfd, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, vl128"
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-
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input:
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bytes: [ 0xa0, 0xfd, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, vl256"
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-
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input:
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bytes: [ 0xc0, 0xfd, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, #14"
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-
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input:
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bytes: [ 0xe0, 0xfd, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, #15"
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-
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input:
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bytes: [ 0x00, 0xfe, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, #16"
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-
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input:
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bytes: [ 0x20, 0xfe, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, #17"
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-
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input:
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bytes: [ 0x40, 0xfe, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, #18"
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-
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input:
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bytes: [ 0x60, 0xfe, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, #19"
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-
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input:
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bytes: [ 0x80, 0xfe, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, #20"
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-
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input:
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bytes: [ 0xa0, 0xfe, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, #21"
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-
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input:
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bytes: [ 0xc0, 0xfe, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, #22"
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-
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input:
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bytes: [ 0xe0, 0xfe, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, #23"
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-
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input:
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bytes: [ 0x00, 0xff, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, #24"
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-
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input:
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bytes: [ 0x20, 0xff, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
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insns:
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-
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asm_text: "uqdecw x0, #25"
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-
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input:
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bytes: [ 0x40, 0xff, 0xb0, 0x04 ]
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arch: "CS_ARCH_AARCH64"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
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expected:
|
||
|
insns:
|
||
|
-
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|
asm_text: "uqdecw x0, #26"
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|
-
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||
|
input:
|
||
|
bytes: [ 0x60, 0xff, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #27"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x80, 0xff, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #28"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "movprfx z0, z7"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw z0.s"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "movprfx z0, z7"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x00, 0xcc, 0xaf, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw z0.s, pow2, mul #16"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "movprfx z0, z7"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x00, 0xcc, 0xa0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw z0.s, pow2"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xff, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xff, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xff, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xff, 0xbf, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, all, mul #16"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xff, 0xa0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw w0"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xff, 0xa0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw w0"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xff, 0xa0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw w0"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xff, 0xaf, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw w0, all, mul #16"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x00, 0xfc, 0xa0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw w0, pow2"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x00, 0xfc, 0xaf, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw w0, pow2, mul #16"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw z0.s"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw z0.s"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw z0.s"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xcf, 0xaf, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw z0.s, all, mul #16"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x00, 0xcc, 0xa0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw z0.s, pow2"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x00, 0xcc, 0xaf, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw z0.s, pow2, mul #16"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x00, 0xfc, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, pow2"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x20, 0xfc, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, vl1"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x40, 0xfc, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, vl2"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x60, 0xfc, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, vl3"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x80, 0xfc, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, vl4"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xa0, 0xfc, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, vl5"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xc0, 0xfc, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, vl6"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xfc, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, vl7"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x00, 0xfd, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, vl8"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x20, 0xfd, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, vl16"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x40, 0xfd, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, vl32"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x60, 0xfd, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, vl64"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x80, 0xfd, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, vl128"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xa0, 0xfd, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, vl256"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xc0, 0xfd, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #14"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xfd, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #15"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x00, 0xfe, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #16"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x20, 0xfe, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #17"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x40, 0xfe, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #18"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x60, 0xfe, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #19"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x80, 0xfe, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #20"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xa0, 0xfe, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #21"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xc0, 0xfe, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #22"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xfe, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #23"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x00, 0xff, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #24"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x20, 0xff, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #25"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x40, 0xff, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #26"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x60, 0xff, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #27"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x80, 0xff, 0xb0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw x0, #28"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "movprfx z0, z7"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw z0.s"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "movprfx z0, z7"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x00, 0xcc, 0xaf, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw z0.s, pow2, mul #16"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "movprfx z0, z7"
|
||
|
|
||
|
-
|
||
|
input:
|
||
|
bytes: [ 0x00, 0xcc, 0xa0, 0x04 ]
|
||
|
arch: "CS_ARCH_AARCH64"
|
||
|
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
|
||
|
expected:
|
||
|
insns:
|
||
|
-
|
||
|
asm_text: "uqdecw z0.s, pow2"
|