mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-06 18:31:03 +00:00
57 lines
1.6 KiB
YAML
57 lines
1.6 KiB
YAML
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test_cases:
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input:
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bytes: [ 0x08, 0x44, 0x08, 0x44, 0x40, 0x18, 0x40, 0x18, 0x08, 0x44, 0x08, 0x44, 0x40, 0x18, 0x40, 0x18, 0x01, 0xbf, 0x40, 0x18, 0x08, 0x44, 0x10, 0xeb, 0x01, 0x00, 0x10, 0xeb, 0x01, 0x00, 0x40, 0x1a, 0x40, 0x1a, 0xa0, 0xeb, 0x01, 0x00, 0xa0, 0xeb, 0x01, 0x00, 0x40, 0x1a, 0x40, 0x1a, 0x01, 0xbf, 0x40, 0x1a, 0x40, 0x1a, 0xb0, 0xeb, 0x01, 0x00, 0xb0, 0xeb, 0x01, 0x00 ]
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arch: "CS_ARCH_ARM"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
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expected:
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insns:
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asm_text: "add r0, r1"
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asm_text: "add r0, r1"
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asm_text: "adds r0, r0, r1"
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asm_text: "adds r0, r0, r1"
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asm_text: "add r0, r1"
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asm_text: "add r0, r1"
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asm_text: "adds r0, r0, r1"
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asm_text: "adds r0, r0, r1"
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asm_text: "itttt eq"
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asm_text: "addeq r0, r0, r1"
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asm_text: "addeq r0, r1"
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asm_text: "addseq.w r0, r0, r1"
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asm_text: "addseq.w r0, r0, r1"
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asm_text: "subs r0, r0, r1"
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asm_text: "subs r0, r0, r1"
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asm_text: "sub.w r0, r0, r1"
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asm_text: "sub.w r0, r0, r1"
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asm_text: "subs r0, r0, r1"
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asm_text: "subs r0, r0, r1"
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asm_text: "itttt eq"
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asm_text: "subeq r0, r0, r1"
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asm_text: "subeq r0, r0, r1"
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asm_text: "subseq.w r0, r0, r1"
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asm_text: "subseq.w r0, r0, r1"
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