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https://github.com/hedge-dev/XenonRecomp.git
synced 2025-04-19 19:01:17 +00:00
Check for redundant operations.
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@ -1305,26 +1305,44 @@ bool Recompiler::Recompile(const Function& fn, uint32_t base, const ppc_insn& in
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case PPC_INST_VCTSXS:
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case PPC_INST_VCFPSXWS128:
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println("\tctx.fpscr.setFlushMode(true);");
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println("\t_mm_store_si128((__m128i*)ctx.v{}.s32, _mm_vctsxs(_mm_mul_ps(_mm_load_ps(ctx.v{}.f32), _mm_set1_ps({}))));", insn.operands[0], insn.operands[1], 1u << insn.operands[2]);
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print("\t_mm_store_si128((__m128i*)ctx.v{}.s32, _mm_vctsxs(", insn.operands[0]);
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if (insn.operands[2] != 0)
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println("_mm_mul_ps(_mm_load_ps(ctx.v{}.f32), _mm_set1_ps({}))));", insn.operands[1], 1u << insn.operands[2]);
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else
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println("_mm_load_ps(ctx.v{}.f32)));", insn.operands[1]);
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break;
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case PPC_INST_VCFSX:
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case PPC_INST_VCSXWFP128:
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{
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const float v = ldexp(1.0f, -int32_t(insn.operands[2]));
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println("\tctx.fpscr.setFlushMode(true);");
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_mul_ps(_mm_cvtepi32_ps(_mm_load_si128((__m128i*)ctx.v{}.u32)), _mm_castsi128_ps(_mm_set1_epi32(int(0x{:X})))));", insn.operands[0], insn.operands[1], *reinterpret_cast<const uint32_t*>(&v));
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print("\t_mm_store_ps(ctx.v{}.f32, ", insn.operands[0]);
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if (insn.operands[2] != 0)
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{
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const float v = ldexp(1.0f, -int32_t(insn.operands[2]));
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println("_mm_mul_ps(_mm_cvtepi32_ps(_mm_load_si128((__m128i*)ctx.v{}.u32)), _mm_castsi128_ps(_mm_set1_epi32(int(0x{:X})))));", insn.operands[1], *reinterpret_cast<const uint32_t*>(&v));
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}
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else
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{
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println("_mm_cvtepi32_ps(_mm_load_si128((__m128i*)ctx.v{}.u32)));", insn.operands[1]);
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}
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break;
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}
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case PPC_INST_VCFUX:
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case PPC_INST_VCUXWFP128:
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{
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const float v = ldexp(1.0f, -int32_t(insn.operands[2]));
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println("\tctx.fpscr.setFlushMode(true);");
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_mul_ps(_mm_cvtepu32_ps_(_mm_load_si128((__m128i*)ctx.v{}.u32)), _mm_castsi128_ps(_mm_set1_epi32(int(0x{:X})))));", insn.operands[0], insn.operands[1], *reinterpret_cast<const uint32_t*>(&v));
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print("\t_mm_store_ps(ctx.v{}.f32, ", insn.operands[0]);
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if (insn.operands[2] != 0)
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{
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const float v = ldexp(1.0f, -int32_t(insn.operands[2]));
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println("_mm_mul_ps(_mm_cvtepu32_ps_(_mm_load_si128((__m128i*)ctx.v{}.u32)), _mm_castsi128_ps(_mm_set1_epi32(int(0x{:X})))));", insn.operands[1], *reinterpret_cast<const uint32_t*>(&v));
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}
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else
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{
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println("_mm_cvtepu32_ps_(_mm_load_si128((__m128i*)ctx.v{}.u32)));", insn.operands[1]);
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}
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break;
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}
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@ -1467,7 +1485,13 @@ bool Recompiler::Recompile(const Function& fn, uint32_t base, const ppc_insn& in
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case PPC_INST_VOR:
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case PPC_INST_VOR128:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_or_si128(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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print("\t_mm_store_si128((__m128i*)ctx.v{}.u8, ", insn.operands[0]);
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if (insn.operands[1] != insn.operands[2])
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println("_mm_or_si128(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8)));", insn.operands[1], insn.operands[2]);
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else
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println("_mm_load_si128((__m128i*)ctx.v{}.u8));", insn.operands[1]);
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break;
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case PPC_INST_VPERM:
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@ -1706,7 +1730,13 @@ bool Recompiler::Recompile(const Function& fn, uint32_t base, const ppc_insn& in
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case PPC_INST_VXOR:
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case PPC_INST_VXOR128:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_xor_si128(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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print("\t_mm_store_si128((__m128i*)ctx.v{}.u8, ", insn.operands[0]);
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if (insn.operands[1] != insn.operands[2])
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println("_mm_xor_si128(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_load_si128((__m128i*)ctx.v{}.u8)));", insn.operands[1], insn.operands[2]);
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else
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println("_mm_setzero_si128());");
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break;
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case PPC_INST_XOR:
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