Remove capstone, use libopcodes

CMakeLists.txt

@@ -1,4 +1,4 @@
-cmake_minimum_required (VERSION 3.20)
+cmake_minimum_required (VERSION 3.20)
 set(THIRDPARTY_ROOT ${CMAKE_SOURCE_DIR}/thirdparty)
 set(CMAKE_CXX_STANDARD 23)
 
@@ -10,11 +10,10 @@ endif()
 
 set(CMAKE_MSVC_RUNTIME_LIBRARY "MultiThreaded$<$<CONFIG:Debug>:Debug>")
 
-add_subdirectory(${THIRDPARTY_ROOT}/capstone)
-include_directories(${THIRDPARTY_ROOT}/capstone/include)
+add_subdirectory(${THIRDPARTY_ROOT}/disasm)
 
 project ("PowerRecomp-ALL")
 
 add_subdirectory(PowerAnalyse)
 add_subdirectory(PowerRecomp)
-add_subdirectory(PowerUtils)
+add_subdirectory(PowerUtils)

PowerAnalyse/main.cpp

@@ -25,21 +25,21 @@ int main()
 
         if (section.flags & SectionFlags_Code)
         {
+            ppc_insn insn;
             while(base < end)
             {
-                auto* instruction = ppc::DisassembleSingle(reinterpret_cast<uint8_t*>(data), base);
-
+                ppc::Disassemble(data, 4, base, insn);
+                
                 base += 4;
                 ++data;
 
-                if (instruction == nullptr)
+                if (insn.opcode == nullptr)
                 {
-                    printf("\t%X\t.long %Xh\n", static_cast<uint32_t>(base - 4), *(data - 1));
+                    printf("\t%X\t%s\n", static_cast<uint32_t>(base - 4), insn.op_str);
                 }
                 else
                 {
-                    std::printf("\t%X\t%s %s\n", static_cast<uint32_t>(base - 4), instruction->mnemonic, instruction->op_str);
-                    cs_free(instruction, 1);
+                    std::printf("\t%X\t%s %s\n", static_cast<uint32_t>(base - 4), insn.opcode->name, insn.op_str);
                 }
             }
         }

PowerUtils/CMakeLists.txt

@@ -2,4 +2,4 @@ project("PowerUtils")
 add_library(PowerUtils "disasm.h" "disasm.cpp" "file.h" "xex.cpp" "image.h" "image.cpp" "elf.h" "ppc_context.h" "symbol.h" "symbol_table.h" "section.h")
 
 target_include_directories(PowerUtils PUBLIC .)
-target_link_libraries(PowerUtils PUBLIC capstone)
+target_link_libraries(PowerUtils PUBLIC disasm)

PowerUtils/disasm.cpp

@@ -1,23 +1,24 @@
 #include "disasm.h"
 
-DisassemblerEngine ppc::gPPCBigEndianDisassembler{ CS_ARCH_PPC, CS_MODE_BIG_ENDIAN };
+thread_local ppc::DisassemblerEngine ppc::gBigEndianDisassembler{ BFD_ENDIAN_BIG, "cell 32"};
 
-DisassemblerEngine::DisassemblerEngine(cs_arch arch, cs_mode mode)
+ppc::DisassemblerEngine::DisassemblerEngine(bfd_endian endian, const char* options)
 {
-    cs_open(arch, mode, &handle);
+    INIT_DISASSEMBLE_INFO(info, stdout, fprintf);
+    info.arch = bfd_arch_powerpc;
+    info.endian = endian;
+    info.disassembler_options = options;
 }
 
-size_t DisassemblerEngine::Disassemble(const uint8_t* code, size_t size, uint64_t base, size_t count, cs_insn** instructions) const
+int ppc::DisassemblerEngine::Disassemble(const void* code, size_t size, uint64_t base, ppc_insn& out)
 {
-    return cs_disasm(handle, code, size, base, count, instructions);
-}
+    if (size < 4)
+    {
+        return 0;
+    }
 
-void DisassemblerEngine::SetOption(cs_opt_type option, size_t value)
-{
-    cs_option(handle, option, value);
-}
-
-DisassemblerEngine::~DisassemblerEngine()
-{
-    cs_close(&handle);
+    info.buffer = (bfd_byte*)code;
+    info.buffer_vma = base;
+    info.buffer_length = size;
+    return decode_insn_ppc(base, &info, &out);
 }

PowerUtils/disasm.h

@@ -1,43 +1,27 @@
 #pragma once
-#include <capstone/capstone.h>
-
-struct DisassemblerEngine
-{
-    csh handle{};
-
-    DisassemblerEngine(const DisassemblerEngine&) = default;
-    DisassemblerEngine& operator=(const DisassemblerEngine&) = delete;
-
-    DisassemblerEngine(cs_arch arch, cs_mode mode);
-    ~DisassemblerEngine();
-    size_t Disassemble(const uint8_t* code, size_t size, uint64_t base, size_t count, cs_insn** instructions) const;
-    void SetOption(cs_opt_type option, size_t value);
-
-    void SetDetail(bool value)
-    {
-        SetOption(CS_OPT_DETAIL, value);
-    }
-};
+#include <dis-asm.h>
 
 namespace ppc
 {
-    extern DisassemblerEngine gPPCBigEndianDisassembler;
-
-    static size_t Disassemble(const uint8_t* code, size_t size, uint64_t base, size_t count, cs_insn** instructions)
+    struct DisassemblerEngine
     {
-        return gPPCBigEndianDisassembler.Disassemble(code, size, base, count, instructions);
-    }
+        disassemble_info info{};
+        DisassemblerEngine(const DisassemblerEngine&) = default;
+        DisassemblerEngine& operator=(const DisassemblerEngine&) = delete;
 
-    static cs_insn* DisassembleSingle(const uint8_t* code, uint64_t base)
+        DisassemblerEngine(bfd_endian endian, const char* options);
+        ~DisassemblerEngine() = default;
+
+        /**
+         * \return Numbers of bytes decoded
+         */
+        int Disassemble(const void* code, size_t size, uint64_t base, ppc_insn& out);
+    };
+
+    thread_local extern DisassemblerEngine gBigEndianDisassembler;
+
+    static int Disassemble(const void* code, size_t size, uint64_t base, ppc_insn& out)
     {
-        cs_insn* instruction{};
-        gPPCBigEndianDisassembler.Disassemble(code, 4, base, 1, &instruction);
-
-        return instruction;
+        return gBigEndianDisassembler.Disassemble(code, size, base, out);
     }
-
-    static void SetDetail(bool value)
-    {
-        gPPCBigEndianDisassembler.SetDetail(value);
-    }
-}
+}

thirdparty/capstone/.appveyor.yml

@@ -1,14 +0,0 @@
-version: 4.0-{build}
-
-os:
-  - Visual Studio 2015
-
-before_build:
-  - call "C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\vcvarsall.bat" amd64
-
-build_script:
-  - mkdir build
-  - cd build
-  - cmake -DCMAKE_BUILD_TYPE=RELEASE -G "NMake Makefiles" ..
-  - nmake
-

thirdparty/capstone/.clang-format

@@ -1,120 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# clang-format configuration file. Intended for clang-format >= 11.
-#
-# For more information, see:
-#
-#   Documentation/process/clang-format.rst
-#   https://clang.llvm.org/docs/ClangFormat.html
-#   https://clang.llvm.org/docs/ClangFormatStyleOptions.html
-#
----
-AccessModifierOffset: -4
-AlignAfterOpenBracket: Align
-AlignConsecutiveAssignments: false
-AlignConsecutiveDeclarations: false
-AlignEscapedNewlines: DontAlign
-AlignOperands: true
-AlignTrailingComments:
-  Kind: Always
-  OverEmptyLines: 2
-AllowAllParametersOfDeclarationOnNextLine: false
-AllowShortBlocksOnASingleLine: false
-AllowShortCaseLabelsOnASingleLine: false
-AllowShortFunctionsOnASingleLine: None
-AllowShortIfStatementsOnASingleLine: false
-AllowShortLoopsOnASingleLine: false
-AlwaysBreakAfterDefinitionReturnType: None
-AlwaysBreakAfterReturnType: None
-AlwaysBreakBeforeMultilineStrings: false
-AlwaysBreakTemplateDeclarations: false
-BinPackArguments: true
-BinPackParameters: true
-BraceWrapping:
-  AfterClass: false
-  AfterControlStatement: false
-  AfterEnum: false
-  AfterFunction: true
-  AfterNamespace: true
-  AfterObjCDeclaration: false
-  AfterStruct: false
-  AfterUnion: false
-  AfterExternBlock: false
-  BeforeCatch: false
-  BeforeElse: false
-  IndentBraces: false
-  SplitEmptyFunction: true
-  SplitEmptyRecord: true
-  SplitEmptyNamespace: true
-BreakBeforeBinaryOperators: None
-BreakBeforeBraces: Custom
-BreakBeforeInheritanceComma: false
-BreakBeforeTernaryOperators: false
-BreakConstructorInitializersBeforeComma: false
-BreakConstructorInitializers: BeforeComma
-BreakAfterJavaFieldAnnotations: false
-BreakStringLiterals: false
-ColumnLimit: 80
-CommentPragmas: '^ IWYU pragma:'
-CompactNamespaces: false
-ConstructorInitializerAllOnOneLineOrOnePerLine: false
-ConstructorInitializerIndentWidth: 8
-ContinuationIndentWidth: 8
-Cpp11BracedListStyle: false
-DerivePointerAlignment: false
-DisableFormat: false
-ExperimentalAutoDetectBinPacking: false
-FixNamespaceComments: false
-
-IncludeBlocks: Preserve
-IncludeCategories:
-  - Regex: '.*'
-    Priority: 1
-IncludeIsMainRegex: '(Test)?$'
-IndentCaseLabels: false
-IndentGotoLabels: false
-IndentPPDirectives: None
-IndentWidth: 8
-IndentWrappedFunctionNames: false
-JavaScriptQuotes: Leave
-JavaScriptWrapImports: true
-KeepEmptyLinesAtTheStartOfBlocks: false
-MacroBlockBegin: ''
-MacroBlockEnd: ''
-MaxEmptyLinesToKeep: 1
-NamespaceIndentation: None
-ObjCBinPackProtocolList: Auto
-ObjCBlockIndentWidth: 8
-ObjCSpaceAfterProperty: true
-ObjCSpaceBeforeProtocolList: true
-
-# Taken from git's rules
-PenaltyBreakAssignment: 10
-PenaltyBreakBeforeFirstCallParameter: 30
-PenaltyBreakComment: 10
-PenaltyBreakFirstLessLess: 0
-PenaltyBreakString: 10
-PenaltyExcessCharacter: 100
-PenaltyReturnTypeOnItsOwnLine: 60
-
-PointerAlignment: Right
-ReflowComments: false
-SortIncludes: false
-SortUsingDeclarations: false
-SpaceAfterCStyleCast: false
-SpaceAfterTemplateKeyword: true
-SpaceBeforeAssignmentOperators: true
-SpaceBeforeCtorInitializerColon: true
-SpaceBeforeInheritanceColon: true
-SpaceBeforeParens: ControlStatementsExceptForEachMacros
-SpaceBeforeRangeBasedForLoopColon: true
-SpaceInEmptyParentheses: false
-SpacesBeforeTrailingComments: 1
-SpacesInAngles: false
-SpacesInContainerLiterals: false
-SpacesInCStyleCastParentheses: false
-SpacesInParentheses: false
-SpacesInSquareBrackets: false
-Standard: Cpp03
-TabWidth: 8
-UseTab: Always

thirdparty/capstone/.editorconfig

@@ -1,22 +0,0 @@
-root = true
-
-[*]
-end_of_line = lf
-insert_final_newline = true
-
-[*.{py,pyx,pxd}]
-indent_style = space
-indent_size = 4
-
-# Follow Linux kernel coding style
-[*.{c,h,cpp,hpp,inc}]
-indent_style = tab
-indent_size = 8
-
-# OCaml bindings
-[*.ml]
-indent_style = tab
-indent_size = 4
-
-[Makefile]
-indent_style = tab

thirdparty/capstone/.gitattributes

@@ -1 +0,0 @@
-/arch/**/*.inc linguist-language=C

thirdparty/capstone/.github/ISSUE_TEMPLATE/bug_report_asm.md

@@ -1,58 +0,0 @@
----
-name: Bug report - Incorrect disassembly
-about: Create a report about incorrect disassembly.
----
-
-<!-- This template is meant for disassembly related bug reports, please be as descriptive as possible -->
-
-### Work environment
-
-<!-- Filling this table is mandatory -->
-
-| Questions                                | Answers
-|------------------------------------------|--------------------
-| OS/arch/bits                             | Debian arm 64, MacOS AArch64, MacOS x86, Windows x86 etc.
-| Architecture                             | ppc, x86, cortexm, armv8 etc.
-| Source of Capstone                       | `git clone`, brew, pip, release binaries etc.
-| Version/git commit                       | v5.0.1, <commit hash>
-
-<!-- INCORRECT DISASSEMBLY BUGS -->
-
-### Instruction bytes giving faulty results
-
-```
-0x00,0x00,0x00,0x00
-```
-
-### Expected results
-
-It should be:
-```
-<this or that>
-```
-
-### Steps to get the wrong result
-
-With `cstool`:
-
-```sh
-cstool arm -d 0x00,0x00,0x00,0x00
-```
-
-or with `Python`
-
-```python
-CODE = b'\x90\x90\x90\x90'
-
-md = Cs(CS_ARCH_ARM, CS_MODE_THUMB)
-md.detail = True
-for insn in md.disasm(CODE, 0x1000):
-  # Print the faulty disassembly
-```
-
-<!-- ADDITIONAL CONTEXT -->
-
-### Additional Logs, screenshots, source code,  configuration dump, ...
-
-Drag and drop zip archives containing the Additional info here, don't use external services or link.
-Screenshots can be directly dropped here.

thirdparty/capstone/.github/ISSUE_TEMPLATE/bug_report_general.md

@@ -1,40 +0,0 @@
----
-name: Bug report - Other bugs
-about: Create a report to help us improve
-
----
-
-<!-- This template is meant for GENERAL bug reports.
-For bugs regarding incorrect disassembly,
-please use the "Bug report - Incorrect disassembly" template.
-
-Please be as descriptive as possible
--->
-
-### Work environment
-
-<!-- Filling this table is mandatory -->
-
-| Questions                                | Answers
-|------------------------------------------|--------------------
-| OS/arch/bits                             | Debian arm 64, MacOS AArch64, MacOS x86, Windows x86 etc.
-| Architecture                             | ppc, x86, cortexm, armv8 etc.
-| Source of Capstone                       | `git clone`, brew, pip, release binaries etc.
-| Version/git commit                       | v5.0.1, <commit hash>
-
-<!-- OTHER BUGS -->
-
-### Expected behavior
-
-### Actual behavior
-
-### Steps to reproduce the behavior
-
-- Use code markdown `CODE` to make your code visible
-
-<!-- ADDITIONAL CONTEXT -->
-
-### Additional Logs, screenshots, source code,  configuration dump, ...
-
-Drag and drop zip archives containing the Additional info here, don't use external services or link.
-Screenshots can be directly dropped here.

thirdparty/capstone/.github/ISSUE_TEMPLATE/feature_request.md

@@ -1,19 +0,0 @@
----
-name: Feature request
-about: Suggest an idea for this project
-
----
-
-### Feature
-
-- [ ] New architecture module
-- [ ] Support for processor extension
-- [ ] Add more instruction details (elaborated below)
-- [ ] Binding support for: `language`
-- [ ] Other (elaborated below)
-
-**Describe the feature you'd like**
-A clear and concise description of what you want to happen.
-
-**Additional context**
-Add any other context about the feature request here.

thirdparty/capstone/.github/PULL_REQUEST_TEMPLATE.md

@@ -1,23 +0,0 @@
- <!-- Filling this template is mandatory -->
-
-**Your checklist for this pull request**
-- [ ] I've documented or updated the documentation of every API function and struct this PR changes.
-- [ ] I've added tests that prove my fix is effective or that my feature works (if possible)
-
-**Detailed description**
-
-<!-- Explain the **details** for making this change. Is a new feature implemented? What existing problem does the pull request solve? How does the pull request solve these issues? Please provide enough information so that others can review your pull request. -->
-
-...
-
-**Test plan**
-
-<!-- What steps should the reviewer take to test your pull request? Demonstrate the code is solid. Or what test cases you added. Disassembly tests should be added in suite/cs_test/issues.cs -->
-
-...
-
-**Closing issues**
-
-<!-- put "closes #XXXX" in your comment to auto-close the issue that your PR fixes (if any). -->
-
-...

thirdparty/capstone/.github/labeler.yml

@@ -1,175 +0,0 @@
-Auto-Sync-files:
-  - suite/auto-sync/**
-
-LLVM-core-files:
-  - MC*.[ch]
-
-LLVM-generated-files:
-  - arch/*/*.inc
-
-Documentation:
-  - '**/*.md'
-
-CS-core-files:
-  - cs*.[ch]
-  - SStream.[ch]
-  - utis.[ch]
-  - MathExtras.h
-  - Mapping.[ch]
-  - LEB128.h
-  - cstool/cstool.[ch]
-  - cstool/getopt.[ch]
-  - include/capstone/capstone.h
-  - include/capstone/cs_operand.h
-  - include/capstone/platform.h
-
-ARM:
-  - arch/ARM/**
-  - cstool/cstool_arm.c
-  - include/capstone/arm.h
-  - suite/MC/ARM/**
-  - tests/test_arm.c
-
-AArch64:
-  - arch/AArch64/**
-  - cstool/cstool_aarch64.c
-  - include/capstone/aarch64.h
-  - suite/MC/AArch64/**
-  - tests/test_aarch64.c
-
-Alpha:
-  - arch/Alpha/**
-  - cstool/cstool_alpha.c
-  - include/capstone/alpha.h
-  - suite/MC/Alpha/**
-  - tests/test_alpha.c
-
-BPF:
-  - arch/BPF/**
-  - cstool/cstool_bpf.c
-  - include/capstone/bpf.h
-  - suite/MC/BPF/**
-  - tests/test_bpf.c
-
-EVM:
-  - arch/EVM/**
-  - cstool/cstool_evm.c
-  - include/capstone/evm.h
-  - tests/test_evm.c
-
-HPPA:
-  - arch/HPPA/**
-  - cstool/cstool_hppa.c
-  - include/capstone/hppa.h
-  - suite/MC/HPPA/**
-  - tests/test_hppa.c
-
-LoongArch:
-  - arch/LoongArch/**
-  - cstool/cstool_loongarch.c
-  - include/capstone/loongarch.h
-  - suite/MC/LoongArch/**
-  - tests/test_loongarch.c
-
-M680X:
-  - arch/M680X/**
-  - cstool/cstool_m680x.c
-  - include/capstone/m680x.h
-  - tests/test_m680x.c
-
-M68K:
-  - arch/M68K/**
-  - cstool/cstool_m68k.c
-  - include/capstone/m68k.h
-  - tests/test_m68k.c
-
-MOS65XX:
-  - arch/MOS65XX/**
-  - cstool/cstool_mos65xx.c
-  - include/capstone/mos65xx.h
-  - tests/test_mos65xx.c
-
-Mips:
-  - arch/Mips/**
-  - cstool/cstool_mips.c
-  - include/capstone/mips.h
-  - suite/MC/Mips/**
-  - tests/test_mips.c
-
-PowerPC:
-  - arch/PowerPC/**
-  - cstool/cstool_powerpc.c
-  - include/capstone/ppc.h
-  - suite/MC/PowerPC/**
-  - tests/test_powerpc.c
-
-RISCV:
-  - arch/RISCV/**
-  - cstool/cstool_riscv.c
-  - include/capstone/riscv.h
-  - suite/MC/RISCV/**
-  - tests/test_riscv.c
-
-SH:
-  - arch/SH/**
-  - cstool/cstool_sh.c
-  - include/capstone/sh.h
-  - tests/test_sh.c
-
-Sparc:
-  - arch/Sparc/**
-  - cstool/cstool_sparc.c
-  - include/capstone/sparc.h
-  - suite/MC/Sparc/**
-  - tests/test_sparc.c
-
-SystemZ:
-  - arch/SystemZ/**
-  - cstool/cstool_systemz.c
-  - include/capstone/systemz.h
-  - suite/MC/SystemZ/**
-  - tests/test_systemz.c
-
-TMS320C64x:
-  - arch/TMS320C6x/**
-  - cstool/cstool_tms320c64x.c
-  - include/capstone/tms320x64x.h
-  - tests/test_tms320c64x.c
-
-TriCore:
-  - arch/TriCore/**
-  - cstool/cstool_tricore.c
-  - include/capstone/tricore.h
-  - suite/MC/Tricore/**
-  - tests/test_tricore.c
-
-WASM:
-  - arch/WASM/**
-  - cstool/cstool_wasm.c
-  - include/capstone/wasm.h
-  - tests/test_wasm.c
-
-X86:
-  - arch/X86/**
-  - cstool/cstool_x86.c
-  - include/capstone/x86.h
-  - suite/MC/X86/**
-  - tests/test_x86.c
-
-XCore:
-  - arch/XCore/**
-  - cstool/cstool_xcore.c
-  - include/capstone/xcore.h
-  - tests/test_xcore.c
-
-python:
-  - bindings/python/**
-
-ocaml:
-  - bindings/ocaml/**
-
-java:
-  - bindings/java/**
-
-Github-files:
-  - .github/**

thirdparty/capstone/.github/workflows/CITest.yml

@@ -1,172 +0,0 @@
-name: Run Test
-on:
-  push:
-    paths-ignore:
-      - ".gitignore"
-      - "docs/**"
-      - "ChangeLog"
-      - "CREDITS.TXT"
-      - "COMPILE_MAKE.TXT"
-      - "COMPILE_MSVC.TXT"
-      - "COMPILE_CMAKE.TXT"
-      - "HACK.TXT"
-      - "LICENSE.TXT"
-      - "LICENSE_LLVM.TXT"
-      - "README.md"
-      - "RELEASE_NOTES"
-      - "SPONSORS.TXT"
-      - "TODO"
-  pull_request:
-
-env:
-  CI: true
-
-jobs:
-  Linux:
-    runs-on: ${{ matrix.config.os }}
-    name: ${{ matrix.config.name }}
-    strategy:
-      fail-fast: false
-      matrix:
-        config:
-          - {
-              name: 'ubuntu-22.04 x64 make',
-              os: ubuntu-22.04,
-              arch: x64,
-              build-system: 'make',
-              diet-build: 'OFF',
-              enable-asan: 'OFF'
-            }
-          - {
-              name: 'ubuntu-22.04 x64 cmake',
-              os: ubuntu-22.04,
-              arch: x64,
-              build-system: 'cmake',
-              diet-build: 'OFF',
-              enable-asan: 'OFF'
-            }
-          - {
-              name: 'ubuntu-24.04 x64 ASAN',
-              os: ubuntu-24.04,
-              arch: x64,
-              build-system: 'cmake',
-              diet-build: 'OFF',
-              enable-asan: 'ON'
-            }
-
-    steps:
-    - uses: actions/checkout@v3
-
-    - name: Set up Python
-      uses: actions/setup-python@v4
-      with:
-        python-version: ${{ matrix.config.python-version }}
-
-    - name: Prepare fuzzing
-      run: |
-        export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH
-        wget https://github.com/groundx/capstonefuzz/raw/master/corpus/corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip
-        unzip -q corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip -d suite/fuzz
-
-    - name: make
-      if: startsWith(matrix.config.build-system, 'make')
-      run: |
-        ./make.sh
-        sudo make install
-
-    - name: cmake
-      if: startsWith(matrix.config.build-system, 'cmake')
-      env:
-        asan: ${{ matrix.config.enable-asan }}
-      run: |
-        mkdir build && cd build
-        # build static library
-        cmake -DCAPSTONE_INSTALL=1 -DCMAKE_INSTALL_PREFIX=/usr -DENABLE_ASAN=${asan} -DCAPSTONE_BUILD_DIET=${diet_build} ..
-        cmake --build . --config Release
-        # build shared library
-        cmake -DCAPSTONE_INSTALL=1 -DBUILD_SHARED_LIBS=1 -DCMAKE_INSTALL_PREFIX=/usr -DCAPSTONE_BUILD_CSTEST=ON -DENABLE_ASAN=${asan} ..
-        sudo cmake --build . --config Release --target install
-
-    - name: Lower number of KASL randomized address bits
-      run: |
-        # Work-around ASAN bug https://github.com/google/sanitizers/issues/1716
-        sudo sysctl vm.mmap_rnd_bits=28
-
-    - name: "Compatibility header test"
-      if: startsWith(matrix.config.build-system, 'cmake') && matrix.config.diet-build == 'OFF'
-      run: |
-        ctest --test-dir build --output-on-failure -R ASCompatibilityHeaderTest
-
-    - name: cstool - reaches disassembler engine
-      run: |
-        sh suite/run_invalid_cstool.sh
-
-    - name: cstest unit tests
-      if: startsWith(matrix.config.build-system, 'cmake')
-      run: |
-        ctest --test-dir build --output-on-failure -R UnitCSTest
-
-    - name: cstest integration tests
-      if: startsWith(matrix.config.build-system, 'cmake')
-      run: |
-        ctest --test-dir build --output-on-failure -R IntegrationCSTest
-
-    - name: cstest MC
-      if: startsWith(matrix.config.build-system, 'cmake')
-      run: |
-        ctest --test-dir build --output-on-failure -R MCTests
-
-    - name: cstest details
-      if: startsWith(matrix.config.build-system, 'cmake')
-      run: |
-        ctest --test-dir build --output-on-failure -R DetailTests
-
-    - name: cstest issues
-      if: startsWith(matrix.config.build-system, 'cmake')
-      run: |
-        ctest --test-dir build --output-on-failure -R IssueTests
-
-    - name: cstest features
-      if: startsWith(matrix.config.build-system, 'cmake')
-      run: |
-        ctest --test-dir build --output-on-failure -R FeaturesTests
-
-    - name: Legacy integration tests
-      if: startsWith(matrix.config.build-system, 'cmake')
-      run: |
-        ctest --test-dir build --output-on-failure -R legacy*
-
-  Windows:
-    runs-on: ${{ matrix.config.os }}
-    name: ${{ matrix.config.name }}
-    strategy:
-      fail-fast: false
-      matrix:
-        config:
-          - name: 'windows x64 MSVC 64bit'
-            os: windows-latest
-            arch: x64
-            platform: windows
-            python-arch: x64
-            python-version: '3.9'
-
-    steps:
-    - uses: actions/checkout@v3
-
-    - uses: lukka/get-cmake@latest
-      name: Get CMake
-
-    - name: '🛠️ Win MSVC 64 setup'
-      if: contains(matrix.config.name, 'MSVC 64')
-      uses: ilammy/msvc-dev-cmd@v1
-      with:
-        arch: 'x64'
-
-    - name: '🚧 Win MSVC 64 build'
-      if: contains(matrix.config.name, 'MSVC 64')
-      shell: bash
-      run: |
-        cmake --version
-        cmake --preset=${{ matrix.config.platform }}-x64
-        cmake --build --preset build-${{ matrix.config.platform }}-release
-        cmake --build --preset install-${{ matrix.config.platform }}-release

thirdparty/capstone/.github/workflows/auto-sync.yml

@@ -1,101 +0,0 @@
-name: Auto-Sync
-on:
-  push:
-    paths:
-      - "suite/auto-sync/**"
-      - ".github/workflows/auto-sync.yml"
-  pull_request:
-
-# Stop previous runs on the same branch on new push
-concurrency:
-  group: ${{ github.workflow }}-${{ github.ref }}
-  cancel-in-progress: true
-
-jobs:
-  check:
-    runs-on: ubuntu-24.04
-    defaults:
-      run:
-        working-directory: suite/auto-sync/
-    steps:
-      - name: Set up Python
-        uses: actions/setup-python@v4
-        with:
-          python-version: '3.11'
-
-      - name: Check out repository
-        uses: actions/checkout@v4
-        with:
-          submodules: true
-
-      - name: Install auto-sync package
-        run: |
-          pip install .
-
-      - name: Check formatting
-        run: |
-          python3.11 -m black --check src/autosync
-
-      - name: Install llvm-mc
-        run: |
-          sudo apt install llvm-18
-          llvm-mc-18 --version
-          FileCheck-18 --version
-          sudo ln -s $(whereis -b llvm-mc-18 | grep -Eo "/.*") /usr/local/bin/llvm-mc
-          sudo ln -s $(whereis -b FileCheck-18 | grep -Eo "/.*") /usr/local/bin/FileCheck
-          llvm-mc --version
-          FileCheck --version
-
-      - name: Clone llvm-capstone
-        run: |
-          git clone https://github.com/capstone-engine/llvm-capstone.git vendor/llvm_root
-
-      - name: Build llvm-tblgen
-        run: |
-          cd vendor/llvm_root
-          mkdir build
-          cd build
-          cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug ../llvm
-          cmake --build . --target llvm-tblgen --config Debug
-          cd ../../../
-
-      - name: Test Header patcher
-        run: |
-          python -m unittest src/autosync/Tests/test_header_patcher.py
-          python -m unittest src/autosync/Tests/test_mcupdater.py
-
-      - name: Remove llvm-mc
-        run: |
-          sudo apt remove llvm-18
-          sudo rm /usr/local/bin/llvm-mc
-          sudo rm /usr/local/bin/FileCheck
-
-      - name: Test generation of inc files
-        run: |
-          ./src/autosync/ASUpdater.py -d -a AArch64 -s IncGen
-          ./src/autosync/ASUpdater.py -d -a Alpha -s IncGen
-          ./src/autosync/ASUpdater.py -d -a ARM -s IncGen
-          ./src/autosync/ASUpdater.py -d -a PPC -s IncGen
-          ./src/autosync/ASUpdater.py -d -a LoongArch -s IncGen
-
-      - name: CppTranslator - Patch tests
-        run: |
-          python -m unittest src/autosync/cpptranslator/Tests/test_patches.py
-
-      - name: CppTranslator - Differ tests
-        run: |
-          python -m unittest src/autosync/cpptranslator/Tests/test_differ.py
-
-      - name: CppTranslator - Test translation
-        run: |
-          ./src/autosync/ASUpdater.py --ci -d -a AArch64 -s Translate
-          ./src/autosync/ASUpdater.py --ci -d -a ARM -s Translate
-          ./src/autosync/ASUpdater.py --ci -d -a PPC -s Translate
-          ./src/autosync/ASUpdater.py --ci -d -a LoongArch -s Translate
-
-      - name: Differ - Test save file is up-to-date
-        run: |
-          ./src/autosync/cpptranslator/Differ.py -a AArch64 --check_saved
-          ./src/autosync/cpptranslator/Differ.py -a ARM --check_saved
-          ./src/autosync/cpptranslator/Differ.py -a PPC --check_saved
-          ./src/autosync/cpptranslator/Differ.py -a LoongArch --check_saved

thirdparty/capstone/.github/workflows/build_release.yml

@@ -1,50 +0,0 @@
-name: Build Source Release
-
-# Trigger whenever a release is created
-on:
-  release:
-    types:
-      - created
-
-jobs:
-  build:
-    name: build
-    runs-on: ubuntu-latest
-    steps:
-    - uses: actions/checkout@v3
-      with:
-        submodules: true
-
-    - name: archive
-      id: archive
-      run: |
-        VERSION=${{ github.event.release.tag_name }}
-        PKGNAME="capstone-$VERSION"
-        SHASUM=$PKGNAME.tar.xz.sha256
-        mkdir -p /tmp/$PKGNAME
-        mv * /tmp/$PKGNAME
-        mv /tmp/$PKGNAME .
-        TARBALL=$PKGNAME.tar.xz
-        tar cJf $TARBALL $PKGNAME
-        sha256sum $TARBALL > $SHASUM
-        echo "::set-output name=tarball::$TARBALL"
-        echo "::set-output name=shasum::$SHASUM"
-    - name: upload tarball
-      uses: actions/upload-release-asset@v1
-      env:
-        GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-      with:
-        upload_url: ${{ github.event.release.upload_url }}
-        asset_path: ./${{ steps.archive.outputs.tarball }}
-        asset_name: ${{ steps.archive.outputs.tarball }}
-        asset_content_type: application/gzip
-
-    - name: upload shasum
-      uses: actions/upload-release-asset@v1
-      env:
-        GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-      with:
-        upload_url: ${{ github.event.release.upload_url }}
-        asset_path: ./${{ steps.archive.outputs.shasum }}
-        asset_name: ${{ steps.archive.outputs.shasum }}
-        asset_content_type: text/plain

thirdparty/capstone/.github/workflows/clang-tidy.yml

@@ -1,43 +0,0 @@
-name: Run clang-tidy
-on:
-  push:
-    paths:
-    - '**.c'
-    - '**.h'
-  pull_request:
-
-jobs:
-  analyze:
-    runs-on: ubuntu-24.04
-
-    name: clang-tidy
-    steps:
-    - uses: actions/checkout@v4
-      with:
-        fetch-depth: 0
-    - name: Install clang-tidy
-      run: |
-        sudo apt install clang-tidy
-
-    - name: Build
-      run: |
-        mkdir build && cd build
-        CC=clang cmake -DCMAKE_EXPORT_COMPILE_COMMANDS=ON -DBUILD_SHARED_LIBS=1 ..
-        CC=clang sudo cmake --build . --config Release
-        cd ..
-
-    - name: Install clang-tidy-18
-      run: |
-        sudo apt install clang-tidy-18
-
-    - name: Check for warnings
-      env:
-        base_sha: ${{ github.event.pull_request.base.sha }}
-        head_sha: ${{ github.event.pull_request.head.sha }}
-      run: |
-        ./run-clang-tidy.sh build
-
-    - uses: actions/upload-artifact@v4
-      if: ${{ failure() }}
-      with:
-        path: ct-warnings.txt

thirdparty/capstone/.github/workflows/coverity.yml

@@ -1,60 +0,0 @@
-name: Coverity Scan
-on:
-  workflow_dispatch:
-  schedule:
-    - cron: '0 0 01 * *' # On the 1st every month at midnight UTC
-
-
-# Automatically cancel any previous workflow on new push.
-concurrency:
-  group: ${{ github.workflow }}-${{ github.ref }}-${{ github.event_name }}
-  cancel-in-progress: true
-
-jobs:
-  latest:
-    runs-on: ubuntu-latest
-    steps:
-      - name: Determine current repository
-        id: "determine-repo"
-        run: echo "repo=${GITHUB_REPOSITORY}" >> $GITHUB_OUTPUT
-
-      - uses: actions/checkout@v4
-      - name: Download Coverity Build Tool
-        run: |
-          wget -q https://scan.coverity.com/download/cxx/linux64 --post-data "token=$TOKEN&project=capstone-next" -O cov-analysis-linux64.tar.gz
-          mkdir cov-analysis-linux64
-          tar xzf cov-analysis-linux64.tar.gz --strip 1 -C cov-analysis-linux64
-        env:
-          TOKEN: ${{ secrets.COVERITY_TOKEN }}
-        
-      - name: Installing build dependencies
-        run: |
-           sudo apt-get --assume-yes install cmake
-
-      - name: Setup
-        run: |
-          cmake . -B build -DCAPSTONE_BUILD_CSTEST=ON
-
-      - name: Build with cov-build
-        run: |
-          export PATH=`pwd`/cov-analysis-linux64/bin:$PATH
-          cov-build --dir cov-int cmake --build build
-          tar czvf capstone.tgz cov-int
-
-
-      - uses: actions/upload-artifact@v4
-        with:
-          path: capstone.tgz
-
-      - name: Submit the result to Coverity Scan
-        run: |
-          curl \
-            --form token=$TOKEN \
-            --form email=capstone.engine@gmail.com \
-            --form file=@capstone.tgz \
-            --form version=trunk \
-            --form description="capstone" \
-            https://scan.coverity.com/builds?project=capstone-next
-        env:
-          TOKEN: ${{ secrets.COVERITY_TOKEN }}
-        if: steps.determine-repo.outputs.repo == 'capstone-engine/capstone'

thirdparty/capstone/.github/workflows/fuzz.yml

@@ -1,23 +0,0 @@
-name: CIFuzz
-on: [pull_request]
-jobs:
-  Fuzzing:
-    runs-on: ubuntu-latest
-    steps:
-    - name: Build Fuzzers
-      uses: google/oss-fuzz/infra/cifuzz/actions/build_fuzzers@master
-      with:
-        oss-fuzz-project-name: 'capstone'
-        dry-run: false
-    - name: Run Fuzzers
-      uses: google/oss-fuzz/infra/cifuzz/actions/run_fuzzers@master
-      with:
-        oss-fuzz-project-name: 'capstone'
-        fuzz-seconds: 600
-        dry-run: false
-    - name: Upload Crash
-      uses: actions/upload-artifact@v3
-      if: failure()
-      with:
-        name: artifacts
-        path: ./out/artifacts

thirdparty/capstone/.github/workflows/labeler.yml

@@ -1,20 +0,0 @@
-name: "Pull Request Labeler"
-on:
-- pull_request_target
-
-# Automatically cancel any previous workflow on new push.
-concurrency:
-  group: ${{ github.workflow }}-${{ github.ref }}-${{ github.event_name }}
-  cancel-in-progress: true
-
-jobs:
-  triage:
-    permissions:
-      contents: read
-      pull-requests: write
-    runs-on: ubuntu-22.04
-    steps:
-    - uses: actions/labeler@v4
-      with:
-        repo-token: "${{ secrets.GITHUB_TOKEN }}"
-  

thirdparty/capstone/.github/workflows/python-publish-release.yml

@@ -1,90 +0,0 @@
-name: RELEASE BUILD - PyPI 📦 Distribution
-
-on: [push, pull_request, release, workflow_dispatch]
-
-jobs:
-  build_wheels:
-    name: Build wheels on ${{ matrix.os }}
-    runs-on: ${{ matrix.os }}
-    strategy:
-      matrix:
-        os: [ubuntu-latest, windows-latest, macos-latest]
-    steps:
-      - uses: actions/checkout@v4
-
-      - name: Set up MSVC x64
-        if: matrix.os == 'windows-latest'
-        uses: ilammy/msvc-dev-cmd@v1
-
-      - name: Set up QEMU
-        if: runner.os == 'Linux'
-        uses: docker/setup-qemu-action@v3
-        with:
-          platforms: all
-
-      - name: Build wheels
-        uses: pypa/cibuildwheel@v2.20.0
-        env:
-          CIBW_ARCHS_MACOS: "x86_64 universal2 arm64"
-          CIBW_ARCHS_LINUX: "x86_64 i686 aarch64" # ppc64le s390x really slow
-          CIBW_ARCHS_WINDOWS: "AMD64" # ARM64  Seems ARM64 will rebuild amd64 wheel for unknow reason.
-          CIBW_BUILD: "cp38-* cp39-* cp310-* cp311-* cp312-*"
-          CIBW_SKIP: ""
-        with:
-          package-dir: bindings/python
-
-      - uses: actions/upload-artifact@v4
-        with:
-          path: ./wheelhouse/*.whl
-          name: artifacts-${{ matrix.os }}
-
-      - name: Check binaries (Windows)
-        if: matrix.os == 'windows-latest'
-        run: |
-          python3.exe suite/check_wheel_bin_arch.py ./wheelhouse/
-
-      - name: Check binaries (Unix)
-        if: matrix.os != 'windows-latest'
-        run: |
-          ./suite/check_wheel_bin_arch.py ./wheelhouse/
-
-  make_sdist:
-    name: Make SDist
-    runs-on: ubuntu-latest
-    steps:
-    - uses: actions/checkout@v4
-      with:
-        fetch-depth: 0  # Optional, use if you use setuptools_scm
-        submodules: true  # Optional, use if you have submodules
-
-    - name: Build SDist
-      run: |
-        cd bindings/python
-        pipx run build --sdist
-
-    - uses: actions/upload-artifact@v4
-      with:
-        path: bindings/python/dist/*.tar.gz
-
-  publish:
-    needs: [build_wheels]
-    runs-on: ubuntu-latest
-    if: github.event_name == 'release' && github.event.prerelease == false && github.event.action == 'published'
-    permissions:
-      id-token: write
-    steps:
-      - uses: actions/download-artifact@v4
-        with:
-          merge-multiple: true
-          path: dist
-
-      - name: Show downloaded artifacts
-        run: ls -laR dist
-
-      - name: Publish distribution 📦 to PyPI
-        if: ${{ success() }}
-        uses: pypa/gh-action-pypi-publish@release/v1
-        with:
-          verbose: true
-          user: __token__
-          password: ${{ secrets.pypi_pass }}

thirdparty/capstone/.github/workflows/python-tests.yml

@@ -1,57 +0,0 @@
-name: Python Package CI
-
-on:
-  push:
-  pull_request:
-
-jobs:
-  build:
-    runs-on: ${{ matrix.os }}
-    strategy:
-      fail-fast: false
-      matrix:
-        os: [ubuntu-24.04, windows-2022, macOS-14]
-        python-version: ["3.8", "3.12"]
-
-    steps:
-    - uses: actions/checkout@v4
-
-    - name: Set up Python ${{ matrix.python-version }}
-      uses: actions/setup-python@v5
-      with:
-        python-version: ${{ matrix.python-version }}
-
-    - name: Setup MSVC
-      if: runner.os == 'Windows'
-      uses: ilammy/msvc-dev-cmd@v1
-
-    - name: Build and install capstone
-      run: pip install ./bindings/python
-
-    - name: Install cstest_py
-      run: pip install ./bindings/python/cstest_py
-
-    - name: Run legacy tests
-      run: python ./bindings/python/tests/test_all.py
-
-    - name: cstest_py integration tests
-      run: |
-        cd suite/cstest/test/
-        python3 ./integration_tests.py cstest_py
-        cd ../../../
-
-    - name: cstest_py MC
-      run: |
-        cstest_py tests/MC/
-
-    - name: cstest_py details
-      run: |
-        cstest_py tests/details/
-
-    - name: cstest_py issues
-      run: |
-        cstest_py tests/issues/
-
-    - name: cstest_py features
-      run: |
-        cstest_py tests/features/

thirdparty/capstone/.gitignore

@@ -1,152 +0,0 @@
-.DS_Store
-
-# Object files
-*.o
-*.ko
-
-# Gcc dependency-tracking files
-*.d
-
-# Libraries
-*.lib
-*.a
-
-# Shared objects (inc. Windows DLLs)
-*.dll
-*.so
-*.so.*
-*.dylib
-
-# Executables
-*.exe
-*.out
-*.app
-
-# python
-bindings/python/build/
-bindings/python/capstone.egg-info/
-bindings/python/cstest_py/src/cstest_py.egg**
-bindings/cython/capstone.egg-info/
-*.pyc
-
-# java
-bindings/java/capstone.jar
-
-# ocaml
-bindings/ocaml/*.cmi
-bindings/ocaml/*.cmx
-bindings/ocaml/*.cmxa
-bindings/ocaml/*.mli
-bindings/ocaml/test
-bindings/ocaml/test_arm
-bindings/ocaml/test_aarch64
-bindings/ocaml/test_basic
-bindings/ocaml/test_mips
-bindings/ocaml/test_x86
-bindings/ocaml/test_detail
-bindings/ocaml/test_ppc
-bindings/ocaml/test_sparc
-bindings/ocaml/test_systemz
-bindings/ocaml/test_xcore
-bindings/ocaml/test_m680x
-
-
-# test binaries
-tests/test_basic
-tests/test_detail
-tests/test_iter
-tests/test_arm
-tests/test_aarch64
-tests/test_mips
-tests/test_x86
-tests/test_ppc
-tests/test_skipdata
-tests/test_sparc
-tests/test_systemz
-tests/test_xcore
-tests/test_tricore
-tests/*.static
-tests/test_customized_mnem
-tests/test_m68k
-tests/test_tms320c64x
-tests/test_m680x
-tests/test_evm
-tests/test_wasm
-tests/test_mos65xx
-tests/test_bpf
-tests/test_sh
-tests/test_riscv
-tests/test_sh
-tests/test_alpha
-tests/test_hppa
-
-# regress binaries
-suite/regress/invalid_read_in_print_operand
-
-# vim tmp file
-*.swp
-*~
-
-capstone.pc
-
-# local files
-_*
-
-# freebsd ports: generated file with "make makesum" command
-packages/freebsd/ports/devel/capstone/distinfo
-
-# VisualStudio
-ProjectUpgradeLog.log
-Debug/
-Release/
-ipch/
-build*/
-*.sdf
-*.opensdf
-*.suo
-*.user
-*.backup
-*.VC.db
-*.VC.opendb
-.vscode/
-
-# CMake build directories
-build*/
-/build
-/out
-
-# Xcode
-xcode/Capstone.xcodeproj/xcuserdata
-xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata
-
-# IntelliJ IDEs
-.idea/
-
-# suite/
-corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip
-test_arm_regression
-test_arm_regression.o
-fuzz_harness
-test_iter_benchmark
-test_file_benchmark
-fuzz_bindisasm
-fuzz_disasm
-fuzz_decode_platform
-capstone_get_setup
-suite/fuzz/corpus
-
-*.s
-
-cstool/cstool
-
-# android
-android-ndk-*
-
-# python virtual env
-.venv/
-
-# Auto-sync files
-suite/auto-sync/src/autosync.egg-info
-
-# clangd cache
-/.cache

thirdparty/capstone/.gitmodules

@@ -1,3 +0,0 @@
-[submodule "suite/auto-sync/vendor/tree-sitter-cpp"]
-	path = suite/auto-sync/vendor/tree-sitter-cpp
-	url = https://github.com/tree-sitter/tree-sitter-cpp.git

thirdparty/capstone/.reuse/dep5

@@ -1,20 +0,0 @@
-Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
-Upstream-Name: CapstoneEngine
-Source: https://github.com/capstone-engine/capstone
-
-Files: src/autosync/cpptranslator/Tests/test_config.json
-Copyright: 2022 Rot127 <unisono@quyllur.org>
-License: BSD-3
-
-Files: src/autosync/cpptranslator/arch_config.json
-Copyright: 2022 Rot127 <unisono@quyllur.org>
-License: BSD-3
-
-Files: src/autosync/cpptranslator/saved_patches.json
-Copyright: 2022 Rot127 <unisono@quyllur.org>
-License: BSD-3
-
-Files: src/autosync/path_vars.json
-Copyright: 2022 Rot127 <unisono@quyllur.org>
-License: BSD-3
-

thirdparty/capstone/.reuse/templates/license-template.jinja2

@@ -1,9 +0,0 @@
-{% for copyright_line in copyright_lines %}
-{{ copyright_line }}
-{% endfor %}
-{% for contributor_line in contributor_lines %}
-SPDX-FileContributor: {{ contributor_line }}
-{% endfor %}
-{% for expression in spdx_expressions %}
-SPDX-License-Identifier: {{ expression }}
-{% endfor %}

thirdparty/capstone/.travis.yml

@@ -1,66 +0,0 @@
-language: cpp
-sudo: false
-before_install:
-        - export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH
-before_script:
-        - wget https://github.com/groundx/capstonefuzz/raw/master/corpus/corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip
-        - unzip -q corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip -d suite/fuzz
-        # TODO remove built in cmocka compile and use system cmocka (including brewfile) once xenial is default
-        - git clone https://git.cryptomilk.org/projects/cmocka.git suite/cstest/cmocka
-        - chmod +x suite/cstest/build_cstest.sh
-        - if [[ ${TRAVIS_OS_NAME} = linux ]]; then export PATH="/usr/lib/llvm-9/bin:${PATH}"; fi
-script:
-        - ./make.sh
-        - make check
-        - sudo make install
-        - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then cp libcapstone.so.* bindings/python/libcapstone.so; fi
-        - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then cp libcapstone.*.dylib bindings/python/libcapstone.dylib; fi
-        - if [[ "$NOPYTEST" != "true" ]]; then cd bindings/python && make check; cd ../..; fi
-        - if [[ "$NOPYTEST" != "true" ]]; then cd suite/cstest && ./build_cstest.sh; fi
-        - if [[ "$NOPYTEST" != "true" ]]; then python cstest_report.py -D -t build/cstest -d ../MC; fi
-        - if [[ "$NOPYTEST" != "true" ]]; then python cstest_report.py -D -t build/cstest -f issues.cs; fi
-        - if [ -n "$QA_FUZZIT" ]; then suite/fuzz/fuzzit.sh; fi
-compiler:
-        - clang
-        - gcc
-os:
-        - linux
-        - osx
-matrix:
-    include:
-        - name: xenial gcc
-          os: linux
-          dist: xenial
-          compiler: gcc
-          addons:
-            apt:
-              packages:
-                - libcmocka-dev
-        - name: xenial clang
-          os: linux
-          dist: xenial
-          compiler: clang
-          addons:
-            apt:
-              packages:
-                - libcmocka-dev
-        - name: fuzza
-          env: ASAN_OPTIONS=detect_leaks=0 CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address -fsanitize=fuzzer-no-link" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address -fsanitize=fuzzer-no-link" LDFLAGS="-fsanitize=address" NOPYTEST=true QA_FUZZIT=asan
-          compiler: clang
-          os: linux
-        - name: fuzzm
-          env: CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=memory -fsanitize=fuzzer-no-link" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=memory -fsanitize=fuzzer-no-link" LDFLAGS="-fsanitize=memory" NOPYTEST=true QA_FUZZIT=msan
-          compiler: clang
-          os: linux
-        - name: fuzzu
-          env: CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=undefined -fsanitize=fuzzer-no-link" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=undefined -fno-sanitize-recover=undefined,integer -fsanitize=fuzzer-no-link" LDFLAGS="-fsanitize=undefined" NOPYTEST=true QA_FUZZIT=ubsan
-          compiler: clang
-          os: linux
-
-addons:
-  apt:
-    sources:
-      - llvm-toolchain-trusty
-      - ubuntu-toolchain-r-test
-    packages:
-      - clang-9

thirdparty/capstone/CMakeLists.txt

@@ -1,905 +0,0 @@
-# For MSVC_RUNTIME_LIBRARY
-cmake_minimum_required(VERSION 3.15)
-
-if(CMAKE_SOURCE_DIR STREQUAL CMAKE_BINARY_DIR)
-    message(FATAL_ERROR "In-tree builds are not supported. Run CMake from a separate directory: cmake -B build")
-endif()
-
-# Detect whether capstone is compiled as top-level or a subdirectory
-set(PROJECT_IS_TOP_LEVEL OFF)
-if(CMAKE_CURRENT_SOURCE_DIR STREQUAL CMAKE_SOURCE_DIR)
-    set(PROJECT_IS_TOP_LEVEL ON)
-
-    # Enable folder support
-    set_property(GLOBAL PROPERTY USE_FOLDERS ON)
-endif()
-
-# https://cmake.org/cmake/help/latest/policy/CMP0042.html
-cmake_policy(SET CMP0042 NEW)
-
-# https://cmake.org/cmake/help/latest/policy/CMP0091.html
-# Enable support for MSVC_RUNTIME_LIBRARY
-cmake_policy(SET CMP0091 NEW)
-
-project(capstone
-    VERSION 5.0
-)
-
-set(UNIX_COMPILER_OPTIONS -Werror -Wall -Warray-bounds -Wshift-negative-value -Wreturn-type -Wformat -Wmissing-braces -Wunused-function -Warray-bounds -Wunused-variable -Wparentheses -Wint-in-bool-context -Wmisleading-indentation)
-
-# maybe-uninitialized is only supported by newer versions of GCC.
-# Unfortunately, it is pretty unreliable and reports wrong results.
-# So we disable it for all compilers versions which support it.
-include(CheckCCompilerFlag)
-check_c_compiler_flag("-Wno-maybe-uninitialized" SUPPORTS_MU)
-check_c_compiler_flag("-Wshadow=local" SUPPORTS_SHADOWING)
-check_c_compiler_flag("-Wsometimes-uninitialized" SUPPORTS_SUNINIT)
-
-if (SUPPORTS_MU)
-    set(UNIX_COMPILER_OPTIONS ${UNIX_COMPILER_OPTIONS} -Wno-maybe-uninitialized)
-endif()
-
-if (SUPPORTS_SHADOWING)
-    set(UNIX_COMPILER_OPTIONS ${UNIX_COMPILER_OPTIONS} -Wshadow=local)
-endif()
-
-if (SUPPORTS_SUNINIT)
-    set(UNIX_COMPILER_OPTIONS ${UNIX_COMPILER_OPTIONS} -Wsometimes-uninitialized)
-endif()
-
-if (MSVC)
-    add_compile_options(/W1 /w14189)
-else()
-    add_compile_options(${UNIX_COMPILER_OPTIONS})
-endif()
-
-
-# to configure the options specify them in the command line or change them in the cmake UI.
-# Don't edit the makefile!
-option(BUILD_SHARED_LIBS "Build shared library" OFF)
-option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" ${BUILD_SHARED_LIBS})
-option(CAPSTONE_BUILD_MACOS_THIN "Disable universal2 builds on macOS" OFF)
-option(CAPSTONE_BUILD_DIET "Build diet library" OFF)
-option(CAPSTONE_BUILD_LEGACY_TESTS "Build legacy tests" ${PROJECT_IS_TOP_LEVEL})
-option(CAPSTONE_BUILD_CSTOOL "Build cstool" ${PROJECT_IS_TOP_LEVEL})
-option(CAPSTONE_BUILD_CSTEST "Build cstest" OFF)
-option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON)
-option(CAPSTONE_USE_ARCH_REGISTRATION "Use explicit architecture registration" OFF)
-option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by default" ON)
-option(CAPSTONE_DEBUG "Whether to enable extra debug assertions" OFF)
-option(CAPSTONE_INSTALL "Generate install target" ${PROJECT_IS_TOP_LEVEL})
-option(ENABLE_ASAN "Enable address sanitizer" OFF)
-option(ENABLE_COVERAGE "Enable test coverage" OFF)
-
-if (ENABLE_ASAN)
-    message("Enabling ASAN")
-    add_definitions(-DASAN_ENABLED)
-    add_compile_options(-fsanitize=address)
-    add_link_options(-fsanitize=address)
-endif()
-
-if (ENABLE_COVERAGE)
-    message("Enabling COVERAGE")
-    add_compile_options(--coverage)
-    add_link_options(--coverage)
-endif()
-
-# If building for OSX it's best to allow CMake to handle building both architectures
-if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN)
-    set(CMAKE_OSX_ARCHITECTURES "x86_64;arm64")
-endif()
-
-set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA HPPA LOONGARCH)
-set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha HPPA LoongArch)
-
-# If building for OSX it's best to allow CMake to handle building both architectures
-if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN)
-    # The cibuildwheel on Github Actions sets this env variable
-    # with the architecture flags it wants to build for.
-    if(DEFINED ENV{ARCHFLAGS})
-        if("$ENV{ARCHFLAGS}" STREQUAL "-arch arm64 -arch x86_64")
-            set(CMAKE_OSX_ARCHITECTURES "x86_64;arm64")
-        elseif("$ENV{ARCHFLAGS}" STREQUAL "-arch arm64")
-            set(CMAKE_OSX_ARCHITECTURES "arm64")
-        elseif("$ENV{ARCHFLAGS}" STREQUAL "-arch x86_64")
-            set(CMAKE_OSX_ARCHITECTURES "x86_64")
-        endif()
-    else()
-        set(CMAKE_OSX_ARCHITECTURES "x86_64;arm64")
-    endif()
-endif()
-
-list(LENGTH SUPPORTED_ARCHITECTURES count)
-math(EXPR count "${count}-1")
-# create options controlling whether support for a particular architecture is needed
-foreach(i RANGE ${count})
-    list(GET SUPPORTED_ARCHITECTURES ${i} supported_architecture)
-    list(GET SUPPORTED_ARCHITECTURE_LABELS ${i} supported_architecture_label)
-    option("CAPSTONE_${supported_architecture}_SUPPORT" "${supported_architecture_label} support" ${CAPSTONE_ARCHITECTURE_DEFAULT})
-endforeach()
-
-option(CAPSTONE_X86_REDUCE "x86 with reduce instruction sets to minimize library" OFF)
-option(CAPSTONE_X86_ATT_DISABLE "Disable x86 AT&T syntax" OFF)
-option(CAPSTONE_OSXKERNEL_SUPPORT "Support to embed Capstone into OS X Kernel extensions" OFF)
-
-if(CAPSTONE_BUILD_DIET)
-    add_definitions(-DCAPSTONE_DIET)
-endif()
-
-if(CAPSTONE_USE_DEFAULT_ALLOC)
-    add_definitions(-DCAPSTONE_USE_SYS_DYN_MEM)
-endif()
-
-if(CAPSTONE_USE_ARCH_REGISTRATION)
-    add_definitions(-DCAPSTONE_USE_ARCH_REGISTRATION)
-elseif(CAPSTONE_ARCHITECTURE_DEFAULT)
-    # propagate architecture support variables to preprocessor
-    foreach(supported_architecture ${SUPPORTED_ARCHITECTURES})
-        set(option_name "CAPSTONE_${supported_architecture}_SUPPORT")
-        if(${option_name})
-            message("Enabling ${option_name}")
-            add_definitions("-D${option_name}")
-        endif()
-    endforeach()
-endif()
-
-if(CAPSTONE_X86_REDUCE)
-    add_definitions(-DCAPSTONE_X86_REDUCE)
-endif()
-
-if(CAPSTONE_X86_ATT_DISABLE)
-    add_definitions(-DCAPSTONE_X86_ATT_DISABLE)
-endif()
-
-if(CAPSTONE_DEBUG)
-    add_definitions(-DCAPSTONE_DEBUG)
-endif()
-
-# Force static runtime libraries
-if(CAPSTONE_BUILD_STATIC_RUNTIME)
-    set(CMAKE_MSVC_RUNTIME_LIBRARY "MultiThreaded$<$<CONFIG:Debug>:Debug>")
-endif()
-
-## sources
-set(SOURCES_ENGINE
-    cs.c
-    Mapping.c
-    MCInst.c
-    MCInstrDesc.c
-    MCInstPrinter.c
-    MCRegisterInfo.c
-    SStream.c
-    utils.c
-)
-set(HEADERS_ENGINE
-    cs_simple_types.h
-    cs_priv.h
-    LEB128.h
-    Mapping.h
-    MathExtras.h
-    MCDisassembler.h
-    MCFixedLenDisassembler.h
-    MCInst.h
-    MCInstrDesc.h
-    MCInstPrinter.h
-    MCRegisterInfo.h
-    SStream.h
-    utils.h
-)
-
-set(HEADERS_COMMON
-    include/capstone/aarch64.h
-    include/capstone/arm64.h
-    include/capstone/arm.h
-    include/capstone/capstone.h
-    include/capstone/cs_operand.h
-    include/capstone/evm.h
-    include/capstone/wasm.h
-    include/capstone/mips.h
-    include/capstone/ppc.h
-    include/capstone/x86.h
-    include/capstone/sparc.h
-    include/capstone/systemz.h
-    include/capstone/xcore.h
-    include/capstone/m68k.h
-    include/capstone/tms320c64x.h
-    include/capstone/m680x.h
-    include/capstone/mos65xx.h
-    include/capstone/bpf.h
-    include/capstone/riscv.h
-    include/capstone/sh.h
-    include/capstone/tricore.h
-    include/capstone/platform.h
-    include/capstone/sh.h
-    include/capstone/alpha.h
-    include/capstone/hppa.h
-    include/capstone/loongarch.h
-)
-
-## architecture support
-if(CAPSTONE_ARM_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_ARM)
-    set(SOURCES_ARM
-        arch/ARM/ARMBaseInfo.c
-        arch/ARM/ARMDisassembler.c
-        arch/ARM/ARMDisassemblerExtension.c
-        arch/ARM/ARMInstPrinter.c
-        arch/ARM/ARMMapping.c
-        arch/ARM/ARMModule.c
-    )
-    set(HEADERS_ARM
-        arch/ARM/ARMAddressingModes.h
-        arch/ARM/ARMBaseInfo.h
-        arch/ARM/ARMDisassemblerExtension.h
-        arch/ARM/ARMInstPrinter.h
-        arch/ARM/ARMLinkage.h
-        arch/ARM/ARMMapping.h
-        arch/ARM/ARMGenAsmWriter.inc
-        arch/ARM/ARMGenDisassemblerTables.inc
-        arch/ARM/ARMGenInstrInfo.inc
-        arch/ARM/ARMGenRegisterInfo.inc
-        arch/ARM/ARMGenSubtargetInfo.inc
-        arch/ARM/ARMGenCSFeatureName.inc
-        arch/ARM/ARMGenCSMappingInsn.inc
-        arch/ARM/ARMGenCSMappingInsnOp.inc
-        arch/ARM/ARMGenCSMappingInsnName.inc
-        arch/ARM/ARMGenSystemRegister.inc
-    )
-endif()
-
-if(CAPSTONE_AARCH64_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_AARCH64)
-    set(SOURCES_AARCH64
-        arch/AArch64/AArch64BaseInfo.c
-        arch/AArch64/AArch64Disassembler.c
-        arch/AArch64/AArch64DisassemblerExtension.c
-        arch/AArch64/AArch64InstPrinter.c
-        arch/AArch64/AArch64Mapping.c
-        arch/AArch64/AArch64Module.c
-    )
-    set(HEADERS_AARCH64
-        arch/AArch64/AArch64AddressingModes.h
-        arch/AArch64/AArch64BaseInfo.h
-        arch/AArch64/AArch64DisassemblerExtension.h
-        arch/AArch64/AArch64InstPrinter.h
-        arch/AArch64/AArch64Linkage.h
-        arch/AArch64/AArch64Mapping.h
-        arch/AArch64/AArch64GenAsmWriter.inc
-        arch/AArch64/AArch64GenDisassemblerTables.inc
-        arch/AArch64/AArch64GenInstrInfo.inc
-        arch/AArch64/AArch64GenRegisterInfo.inc
-        arch/AArch64/AArch64GenRegisterName.inc
-        arch/AArch64/AArch64GenSubtargetInfo.inc
-        arch/AArch64/AArch64GenSystemOperands.inc
-        arch/AArch64/AArch64GenCSMappingInsn.inc
-        arch/AArch64/AArch64GenCSMappingInsnName.inc
-        arch/AArch64/AArch64GenCSMappingInsnOp.inc
-    )
-endif()
-
-if(CAPSTONE_MIPS_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_MIPS)
-    set(SOURCES_MIPS
-        arch/Mips/MipsDisassembler.c
-        arch/Mips/MipsInstPrinter.c
-        arch/Mips/MipsMapping.c
-        arch/Mips/MipsModule.c
-    )
-    set(HEADERS_MIPS
-        arch/Mips/MipsDisassembler.h
-        arch/Mips/MipsGenAsmWriter.inc
-        arch/Mips/MipsGenDisassemblerTables.inc
-        arch/Mips/MipsGenInstrInfo.inc
-        arch/Mips/MipsGenRegisterInfo.inc
-        arch/Mips/MipsGenSubtargetInfo.inc
-        arch/Mips/MipsInstPrinter.h
-        arch/Mips/MipsMapping.h
-        arch/Mips/MipsMappingInsn.inc
-    )
-    set(HEADERS_MIPS
-        arch/Mips/MipsDisassembler.h
-        arch/Mips/MipsGenAsmWriter.inc
-        arch/Mips/MipsGenDisassemblerTables.inc
-        arch/Mips/MipsGenInstrInfo.inc
-        arch/Mips/MipsGenRegisterInfo.inc
-        arch/Mips/MipsGenSubtargetInfo.inc
-        arch/Mips/MipsInstPrinter.h
-        arch/Mips/MipsMapping.h
-    )
-endif()
-
-if(CAPSTONE_PPC_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_POWERPC)
-    set(SOURCES_PPC
-        arch/PowerPC/PPCDisassembler.c
-        arch/PowerPC/PPCInstPrinter.c
-        arch/PowerPC/PPCMapping.c
-        arch/PowerPC/PPCModule.c
-    )
-    set(HEADERS_PPC
-        arch/PowerPC/PPCInstrInfo.h
-        arch/PowerPC/PPCInstPrinter.h
-        arch/PowerPC/PPCLinkage.h
-        arch/PowerPC/PPCMapping.h
-        arch/PowerPC/PPCMCTargetDesc.h
-        arch/PowerPC/PPCPredicates.h
-        arch/PowerPC/PPCRegisterInfo.h
-        arch/PowerPC/PPCGenAsmWriter.inc
-        arch/PowerPC/PPCGenCSFeatureName.inc
-        arch/PowerPC/PPCGenCSMappingInsn.inc
-        arch/PowerPC/PPCGenCSMappingInsnOp.inc
-        arch/PowerPC/PPCGenCSMappingInsnName.inc
-        arch/PowerPC/PPCGenCSOpGroup.inc
-        arch/PowerPC/PPCGenDisassemblerTables.inc
-        arch/PowerPC/PPCGenInstrInfo.inc
-        arch/PowerPC/PPCGenSubtargetInfo.inc
-        arch/PowerPC/PPCGenRegisterInfo.inc
-    )
-endif()
-
-if(CAPSTONE_X86_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_X86)
-    set(SOURCES_X86
-        arch/X86/X86Disassembler.c
-        arch/X86/X86DisassemblerDecoder.c
-        arch/X86/X86IntelInstPrinter.c
-        arch/X86/X86InstPrinterCommon.c
-        arch/X86/X86Mapping.c
-        arch/X86/X86Module.c
-    )
-    set(HEADERS_X86
-        arch/X86/X86BaseInfo.h
-        arch/X86/X86Disassembler.h
-        arch/X86/X86DisassemblerDecoder.h
-        arch/X86/X86DisassemblerDecoderCommon.h
-        arch/X86/X86GenAsmWriter.inc
-        arch/X86/X86GenAsmWriter1.inc
-        arch/X86/X86GenAsmWriter1_reduce.inc
-        arch/X86/X86GenAsmWriter_reduce.inc
-        arch/X86/X86GenDisassemblerTables.inc
-        arch/X86/X86GenDisassemblerTables_reduce.inc
-        arch/X86/X86GenInstrInfo.inc
-        arch/X86/X86GenInstrInfo_reduce.inc
-        arch/X86/X86GenRegisterInfo.inc
-        arch/X86/X86InstPrinter.h
-        arch/X86/X86Mapping.h
-        arch/X86/X86MappingInsn.inc
-        arch/X86/X86MappingInsnOp.inc
-        arch/X86/X86MappingInsnOp_reduce.inc
-        arch/X86/X86MappingInsn_reduce.inc
-    )
-    set(HEADERS_X86
-        arch/X86/X86BaseInfo.h
-        arch/X86/X86Disassembler.h
-        arch/X86/X86DisassemblerDecoder.h
-        arch/X86/X86DisassemblerDecoderCommon.h
-        arch/X86/X86GenAsmWriter.inc
-        arch/X86/X86GenAsmWriter1.inc
-        arch/X86/X86GenAsmWriter1_reduce.inc
-        arch/X86/X86GenAsmWriter_reduce.inc
-        arch/X86/X86GenDisassemblerTables.inc
-        arch/X86/X86GenDisassemblerTables_reduce.inc
-        arch/X86/X86GenInstrInfo.inc
-        arch/X86/X86GenInstrInfo_reduce.inc
-        arch/X86/X86GenRegisterInfo.inc
-        arch/X86/X86InstPrinter.h
-        arch/X86/X86Mapping.h
-    )
-    if(NOT CAPSTONE_BUILD_DIET)
-        set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c)
-    endif()
-endif()
-
-if(CAPSTONE_SPARC_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_SPARC)
-    set(SOURCES_SPARC
-        arch/Sparc/SparcDisassembler.c
-        arch/Sparc/SparcInstPrinter.c
-        arch/Sparc/SparcMapping.c
-        arch/Sparc/SparcModule.c
-    )
-    set(HEADERS_SPARC
-        arch/Sparc/Sparc.h
-        arch/Sparc/SparcDisassembler.h
-        arch/Sparc/SparcGenAsmWriter.inc
-        arch/Sparc/SparcGenDisassemblerTables.inc
-        arch/Sparc/SparcGenInstrInfo.inc
-        arch/Sparc/SparcGenRegisterInfo.inc
-        arch/Sparc/SparcGenSubtargetInfo.inc
-        arch/Sparc/SparcInstPrinter.h
-        arch/Sparc/SparcMapping.h
-        arch/Sparc/SparcMappingInsn.inc
-    )
-endif()
-
-if(CAPSTONE_SYSZ_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_SYSZ)
-    set(SOURCES_SYSZ
-        arch/SystemZ/SystemZDisassembler.c
-        arch/SystemZ/SystemZInstPrinter.c
-        arch/SystemZ/SystemZMapping.c
-        arch/SystemZ/SystemZModule.c
-        arch/SystemZ/SystemZMCTargetDesc.c
-    )
-    set(HEADERS_SYSZ
-        arch/SystemZ/SystemZDisassembler.h
-        arch/SystemZ/SystemZGenAsmWriter.inc
-        arch/SystemZ/SystemZGenDisassemblerTables.inc
-        arch/SystemZ/SystemZGenInsnNameMaps.inc
-        arch/SystemZ/SystemZGenInstrInfo.inc
-        arch/SystemZ/SystemZGenRegisterInfo.inc
-        arch/SystemZ/SystemZGenSubtargetInfo.inc
-        arch/SystemZ/SystemZInstPrinter.h
-        arch/SystemZ/SystemZMapping.h
-        arch/SystemZ/SystemZMappingInsn.inc
-        arch/SystemZ/SystemZMCTargetDesc.h
-    )
-endif()
-
-if(CAPSTONE_XCORE_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_XCORE)
-    set(SOURCES_XCORE
-        arch/XCore/XCoreDisassembler.c
-        arch/XCore/XCoreInstPrinter.c
-        arch/XCore/XCoreMapping.c
-        arch/XCore/XCoreModule.c
-    )
-    set(HEADERS_XCORE
-        arch/XCore/XCoreDisassembler.h
-        arch/XCore/XCoreGenAsmWriter.inc
-        arch/XCore/XCoreGenDisassemblerTables.inc
-        arch/XCore/XCoreGenInstrInfo.inc
-        arch/XCore/XCoreGenRegisterInfo.inc
-        arch/XCore/XCoreInstPrinter.h
-        arch/XCore/XCoreMapping.h
-        arch/XCore/XCoreMappingInsn.inc
-    )
-endif()
-
-if(CAPSTONE_M68K_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_M68K)
-    set(SOURCES_M68K
-        arch/M68K/M68KDisassembler.c
-        arch/M68K/M68KInstPrinter.c
-        arch/M68K/M68KModule.c
-    )
-    set(HEADERS_M68K
-        arch/M68K/M68KDisassembler.h
-    )
-endif()
-
-if(CAPSTONE_TMS320C64X_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_TMS320C64X)
-    set(SOURCES_TMS320C64X
-        arch/TMS320C64x/TMS320C64xDisassembler.c
-        arch/TMS320C64x/TMS320C64xInstPrinter.c
-        arch/TMS320C64x/TMS320C64xMapping.c
-        arch/TMS320C64x/TMS320C64xModule.c
-    )
-    set(HEADERS_TMS320C64X
-        arch/TMS320C64x/TMS320C64xDisassembler.h
-        arch/TMS320C64x/TMS320C64xGenAsmWriter.inc
-        arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc
-        arch/TMS320C64x/TMS320C64xGenInstrInfo.inc
-        arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc
-        arch/TMS320C64x/TMS320C64xInstPrinter.h
-        arch/TMS320C64x/TMS320C64xMapping.h
-    )
-endif()
-
-if(CAPSTONE_M680X_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_M680X)
-    set(SOURCES_M680X
-        arch/M680X/M680XDisassembler.c
-        arch/M680X/M680XInstPrinter.c
-        arch/M680X/M680XModule.c
-    )
-    set(HEADERS_M680X
-        arch/M680X/M680XInstPrinter.h
-        arch/M680X/M680XDisassembler.h
-        arch/M680X/M680XDisassemblerInternals.h
-    )
-endif()
-
-if(CAPSTONE_EVM_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_EVM)
-    set(SOURCES_EVM
-        arch/EVM/EVMDisassembler.c
-        arch/EVM/EVMInstPrinter.c
-        arch/EVM/EVMMapping.c
-        arch/EVM/EVMModule.c
-    )
-    set(HEADERS_EVM
-        arch/EVM/EVMDisassembler.h
-        arch/EVM/EVMInstPrinter.h
-        arch/EVM/EVMMapping.h
-        arch/EVM/EVMMappingInsn.inc
-    )
-endif()
-
-if(CAPSTONE_WASM_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_WASM)
-    set(SOURCES_WASM
-        arch/WASM/WASMDisassembler.c
-        arch/WASM/WASMInstPrinter.c
-        arch/WASM/WASMMapping.c
-        arch/WASM/WASMModule.c
-    )
-    set(HEADERS_WASM
-        arch/WASM/WASMDisassembler.h
-        arch/WASM/WASMInstPrinter.h
-        arch/WASM/WASMMapping.h
-    )
-endif()
-
-if(CAPSTONE_MOS65XX_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_MOS65XX)
-    set(SOURCES_MOS65XX
-            arch/MOS65XX/MOS65XXModule.c
-            arch/MOS65XX/MOS65XXDisassembler.c)
-    set(HEADERS_SOURCES_MOS65XX
-            arch/MOS65XX/MOS65XXDisassembler.h
-    )
-endif()
-
-if(CAPSTONE_BPF_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_BPF)
-    set(SOURCES_BPF
-        arch/BPF/BPFDisassembler.c
-        arch/BPF/BPFInstPrinter.c
-        arch/BPF/BPFMapping.c
-        arch/BPF/BPFModule.c
-    )
-    set(HEADERS_BPF
-        arch/BPF/BPFConstants.h
-        arch/BPF/BPFDisassembler.h
-        arch/BPF/BPFInstPrinter.h
-        arch/BPF/BPFMapping.h
-        arch/BPF/BPFModule.h
-    )
-endif()
-
-if(CAPSTONE_RISCV_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_RISCV)
-    set(SOURCES_RISCV
-        arch/RISCV/RISCVDisassembler.c
-        arch/RISCV/RISCVInstPrinter.c
-        arch/RISCV/RISCVMapping.c
-        arch/RISCV/RISCVModule.c
-    )
-    set(HEADERS_RISCV
-        arch/RISCV/RISCVBaseInfo.h
-        arch/RISCV/RISCVDisassembler.h
-        arch/RISCV/RISCVInstPrinter.h
-        arch/RISCV/RISCVMapping.h
-        arch/RISCV/RISCVModule.h
-        arch/RISCV/RISCVGenAsmWriter.inc
-        arch/RISCV/RISCVGenDisassemblerTables.inc
-        arch/RISCV/RISCVGenInsnNameMaps.inc
-        arch/RISCV/RISCVGenInstrInfo.inc
-        arch/RISCV/RISCVGenRegisterInfo.inc
-        arch/RISCV/RISCVGenSubtargetInfo.inc
-        arch/RISCV/RISCVMappingInsn.inc
-        arch/RISCV/RISCVMappingInsnOp.inc
-    )
-endif()
-
-if(CAPSTONE_SH_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_SH)
-    set(SOURCES_SH
-        arch/SH/SHDisassembler.c
-        arch/SH/SHInstPrinter.c
-        arch/SH/SHModule.c
-    )
-    set(HEADERS_SH
-        arch/SH/SHDisassembler.h
-        arch/SH/SHInstPrinter.h
-        arch/SH/SHModule.h
-        arch/SH/SHInsnTable.inc
-    )
-endif()
-
-if (CAPSTONE_TRICORE_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_TRICORE)
-    set(SOURCES_TRICORE
-            arch/TriCore/TriCoreDisassembler.c
-            arch/TriCore/TriCoreInstPrinter.c
-            arch/TriCore/TriCoreMapping.c
-            arch/TriCore/TriCoreModule.c
-            )
-    set(HEADERS_TRICORE
-            arch/TriCore/TriCoreDisassembler.h
-            arch/TriCore/TriCoreLinkage.h
-            arch/TriCore/TriCoreGenAsmWriter.inc
-            arch/TriCore/TriCoreGenDisassemblerTables.inc
-            arch/TriCore/TriCoreGenInstrInfo.inc
-            arch/TriCore/TriCoreGenRegisterInfo.inc
-            arch/TriCore/TriCoreMapping.h
-            arch/TriCore/TriCoreModule.h
-            )
-endif ()
-
-if (CAPSTONE_ALPHA_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_ALPHA)
-    set(SOURCES_ALPHA
-            arch/Alpha/AlphaDisassembler.c
-            arch/Alpha/AlphaInstPrinter.c
-            arch/Alpha/AlphaMapping.c
-            arch/Alpha/AlphaModule.c
-            )
-    set(HEADERS_ALPHA
-            arch/Alpha/AlphaDisassembler.h
-            arch/Alpha/AlphaGenAsmWriter.inc
-            arch/Alpha/AlphaGenDisassemblerTables.inc
-            arch/Alpha/AlphaGenInstrInfo.inc
-            arch/Alpha/AlphaGenRegisterInfo.inc
-            arch/Alpha/AlphaLinkage.h
-            arch/Alpha/AlphaMapping.h
-            arch/Alpha/AlphaModule.h
-            arch/Alpha/AlphaGenCSMappingInsnOp.inc
-            arch/Alpha/AlphaGenCSMappingInsn.inc
-            arch/Alpha/AlphaGenCSMappingInsnName.inc
-            )
-endif ()
-
-if(CAPSTONE_HPPA_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_HPPA)
-    set(SOURCES_HPPA
-        arch/HPPA/HPPADisassembler.c
-        arch/HPPA/HPPAInstPrinter.c
-        arch/HPPA/HPPAMapping.c
-        arch/HPPA/HPPAModule.c
-    )
-    set(HEADERS_HPPA
-        arch/HPPA/HPPAConstants.h
-        arch/HPPA/HPPADisassembler.h
-        arch/HPPA/HPPAInstPrinter.h
-        arch/HPPA/HPPAMapping.h
-        arch/HPPA/HPPAModule.h
-    )
-endif()
-
-if (CAPSTONE_LOONGARCH_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_LOONGARCH)
-    set(SOURCES_LOONGARCH
-            arch/LoongArch/LoongArchDisassembler.c
-            arch/LoongArch/LoongArchDisassemblerExtension.c
-            arch/LoongArch/LoongArchInstPrinter.c
-            arch/LoongArch/LoongArchMapping.c
-            arch/LoongArch/LoongArchModule.c
-            )
-    set(HEADERS_LOONGARCH
-            arch/LoongArch/LoongArchInstPrinter.h
-            arch/LoongArch/LoongArchMapping.h
-            arch/LoongArch/LoongArchModule.h
-            arch/LoongArch/LoongArchLinkage.h
-            )
-endif ()
-
-if (CAPSTONE_OSXKERNEL_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
-endif()
-
-set(ALL_SOURCES
-    ${SOURCES_ENGINE}
-    ${SOURCES_ARM}
-    ${SOURCES_AARCH64}
-    ${SOURCES_MIPS}
-    ${SOURCES_PPC}
-    ${SOURCES_X86}
-    ${SOURCES_SPARC}
-    ${SOURCES_SYSZ}
-    ${SOURCES_XCORE}
-    ${SOURCES_M68K}
-    ${SOURCES_TMS320C64X}
-    ${SOURCES_M680X}
-    ${SOURCES_EVM}
-    ${SOURCES_WASM}
-    ${SOURCES_MOS65XX}
-    ${SOURCES_BPF}
-    ${SOURCES_RISCV}
-    ${SOURCES_SH}
-    ${SOURCES_TRICORE}
-    ${SOURCES_ALPHA}
-    ${SOURCES_HPPA}
-    ${SOURCES_LOONGARCH}
-)
-
-set(ALL_HEADERS
-    ${HEADERS_COMMON}
-    ${HEADERS_ENGINE}
-    ${HEADERS_ARM}
-    ${HEADERS_AARCH64}
-    ${HEADERS_MIPS}
-    ${HEADERS_PPC}
-    ${HEADERS_X86}
-    ${HEADERS_SPARC}
-    ${HEADERS_SYSZ}
-    ${HEADERS_XCORE}
-    ${HEADERS_M68K}
-    ${HEADERS_TMS320C64X}
-    ${HEADERS_M680X}
-    ${HEADERS_EVM}
-    ${HEADERS_WASM}
-    ${HEADERS_MOS65XX}
-    ${HEADERS_BPF}
-    ${HEADERS_RISCV}
-    ${HEADERS_SH}
-    ${HEADERS_TRICORE}
-    ${HEADERS_ALPHA}
-    ${HEADERS_HPPA}
-    ${HEADERS_LOONGARCH}
-)
-
-## properties
-# version info
-set_property(GLOBAL PROPERTY VERSION ${PROJECT_VERSION})
-
-## targets
-add_library(capstone ${ALL_SOURCES} ${ALL_HEADERS})
-add_library(capstone::capstone ALIAS capstone)
-target_include_directories(capstone PUBLIC
-    $<BUILD_INTERFACE:${PROJECT_SOURCE_DIR}/include>
-)
-set_property(TARGET capstone PROPERTY C_STANDARD 99)
-
-if(BUILD_SHARED_LIBS)
-    target_compile_definitions(capstone PUBLIC CAPSTONE_SHARED)
-    set_target_properties(capstone PROPERTIES
-        VERSION ${PROJECT_VERSION}
-        SOVERSION ${PROJECT_VERSION_MAJOR}
-    )
-endif()
-
-# Fuzzer if this is moved to it's own CMakeLists.txt (as it should be)
-# the OSS fuzzer build fails. And must be fixed.
-# Simply because it builds the fuzzer there again with hard-coded paths.
-# See: https://github.com/google/oss-fuzz/blob/master/projects/capstone/build.sh
-# and: https://github.com/capstone-engine/capstone/issues/2454
-add_executable(fuzz_disasm ${PROJECT_SOURCE_DIR}/suite/fuzz/onefile.c ${PROJECT_SOURCE_DIR}/suite/fuzz/fuzz_disasm.c ${PROJECT_SOURCE_DIR}/suite/fuzz/platform.c)
-target_link_libraries(fuzz_disasm PRIVATE capstone)
-
-source_group("Source\\Engine" FILES ${SOURCES_ENGINE})
-source_group("Source\\ARM" FILES ${SOURCES_ARM})
-source_group("Source\\AARCH64" FILES ${SOURCES_AARCH64})
-source_group("Source\\Mips" FILES ${SOURCES_MIPS})
-source_group("Source\\PowerPC" FILES ${SOURCES_PPC})
-source_group("Source\\Sparc" FILES ${SOURCES_SPARC})
-source_group("Source\\SystemZ" FILES ${SOURCES_SYSZ})
-source_group("Source\\X86" FILES ${SOURCES_X86})
-source_group("Source\\XCore" FILES ${SOURCES_XCORE})
-source_group("Source\\M68K" FILES ${SOURCES_M68K})
-source_group("Source\\TMS320C64x" FILES ${SOURCES_TMS320C64X})
-source_group("Source\\M680X" FILES ${SOURCES_M680X})
-source_group("Source\\EVM" FILES ${SOURCES_EVM})
-source_group("Source\\WASM" FILES ${SOURCES_WASM})
-source_group("Source\\MOS65XX" FILES ${SOURCES_MOS65XX})
-source_group("Source\\BPF" FILES ${SOURCES_BPF})
-source_group("Source\\RISCV" FILES ${SOURCES_RISCV})
-source_group("Source\\SH" FILES ${SOURCES_SH})
-source_group("Source\\TriCore" FILES ${SOURCES_TRICORE})
-source_group("Source\\Alpha" FILES ${SOURCES_ALPHA})
-source_group("Source\\HPPA" FILES ${SOURCES_HPPA})
-source_group("Source\\LoongArch" FILES ${SOURCES_LOONGARCH})
-
-source_group("Include\\Common" FILES ${HEADERS_COMMON})
-source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
-source_group("Include\\ARM" FILES ${HEADERS_ARM})
-source_group("Include\\AARCH64" FILES ${HEADERS_AARCH64})
-source_group("Include\\Mips" FILES ${HEADERS_MIPS})
-source_group("Include\\PowerPC" FILES ${HEADERS_PPC})
-source_group("Include\\Sparc" FILES ${HEADERS_SPARC})
-source_group("Include\\SystemZ" FILES ${HEADERS_SYSZ})
-source_group("Include\\X86" FILES ${HEADERS_X86})
-source_group("Include\\XCore" FILES ${HEADERS_XCORE})
-source_group("Include\\M68K" FILES ${HEADERS_M68K})
-source_group("Include\\TMS320C64x" FILES ${HEADERS_TMS320C64X})
-source_group("Include\\M680X" FILES ${HEADERS_MC680X})
-source_group("Include\\EVM" FILES ${HEADERS_EVM})
-source_group("Include\\WASM" FILES ${HEADERS_WASM})
-source_group("Include\\MOS65XX" FILES ${HEADERS_MOS65XX})
-source_group("Include\\BPF" FILES ${HEADERS_BPF})
-source_group("Include\\RISCV" FILES ${HEADERS_RISCV})
-source_group("Include\\SH" FILES ${HEADERS_SH})
-source_group("Include\\TriCore" FILES ${HEADERS_TRICORE})
-source_group("Include\\Alpha" FILES ${HEADERS_ALPHA})
-source_group("Include\\HPPA" FILES ${HEADERS_HPPA})
-source_group("Include\\LoongArch" FILES ${HEADERS_LOONGARCH})
-
-## installation
-if(CAPSTONE_INSTALL)
-    include(GNUInstallDirs)
-
-    install(FILES ${HEADERS_COMMON} DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/capstone)
-    install(FILES ${HEADERS_INC} DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/capstone/inc)
-
-    # Support absolute installation paths (discussion: https://github.com/NixOS/nixpkgs/issues/144170)
-    if(IS_ABSOLUTE ${CMAKE_INSTALL_LIBDIR})
-        set(CAPSTONE_PKGCONFIG_INSTALL_LIBDIR ${CMAKE_INSTALL_LIBDIR})
-        set(CAPSTONE_CMAKE_INSTALL_LIBDIR ${CMAKE_INSTALL_LIBDIR})
-    else()
-        set(CAPSTONE_PKGCONFIG_INSTALL_LIBDIR "\${prefix}/${CMAKE_INSTALL_LIBDIR}")
-        set(CAPSTONE_CMAKE_INSTALL_LIBDIR "\${PACKAGE_PREFIX_DIR}/${CMAKE_INSTALL_LIBDIR}")
-    endif()
-    if(IS_ABSOLUTE ${CMAKE_INSTALL_INCLUDEDIR})
-        set(CAPSTONE_PKGCONFIG_INSTALL_INCLUDEDIR ${CMAKE_INSTALL_INCLUDEDIR})
-        set(CAPSTONE_CMAKE_INSTALL_INCLUDEDIR ${CMAKE_INSTALL_INCLUDEDIR})
-    else()
-        set(CAPSTONE_PKGCONFIG_INSTALL_INCLUDEDIR "\${prefix}/${CMAKE_INSTALL_INCLUDEDIR}")
-        set(CAPSTONE_CMAKE_INSTALL_INCLUDEDIR "\${PACKAGE_PREFIX_DIR}/${CMAKE_INSTALL_INCLUDEDIR}")
-    endif()
-
-    configure_file(capstone.pc.in ${CMAKE_BINARY_DIR}/capstone.pc @ONLY)
-    install(FILES ${CMAKE_BINARY_DIR}/capstone.pc DESTINATION ${CMAKE_INSTALL_LIBDIR}/pkgconfig)
-
-    include(CMakePackageConfigHelpers)
-    set(CAPSTONE_CMAKE_CONFIG_INSTALL_DIR "${CMAKE_INSTALL_LIBDIR}/cmake/capstone")
-    configure_package_config_file(
-        capstone-config.cmake.in
-        ${CMAKE_CURRENT_BINARY_DIR}/capstone-config.cmake
-        INSTALL_DESTINATION ${CAPSTONE_CMAKE_CONFIG_INSTALL_DIR}
-    )
-    write_basic_package_version_file(
-        ${CMAKE_CURRENT_BINARY_DIR}/capstone-config-version.cmake
-        VERSION ${PROJECT_VERSION}
-        COMPATIBILITY SameMajorVersion
-    )
-
-    install(FILES
-        "${CMAKE_CURRENT_BINARY_DIR}/capstone-config.cmake"
-        "${CMAKE_CURRENT_BINARY_DIR}/capstone-config-version.cmake"
-        DESTINATION ${CAPSTONE_CMAKE_CONFIG_INSTALL_DIR}
-    )
-
-    install(TARGETS capstone
-            EXPORT capstone-targets
-            RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}
-            LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}
-            ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}
-            INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}
-    )
-
-    install(EXPORT capstone-targets
-            NAMESPACE capstone::
-            DESTINATION ${CAPSTONE_CMAKE_CONFIG_INSTALL_DIR}
-    )
-
-    # uninstall target
-    if(NOT TARGET UNINSTALL)
-        configure_file(
-            "${CMAKE_CURRENT_SOURCE_DIR}/cmake_uninstall.cmake.in"
-            "${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake"
-            IMMEDIATE @ONLY
-        )
-        add_custom_target(UNINSTALL COMMAND ${CMAKE_COMMAND} -P ${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake)
-        set_target_properties(UNINSTALL PROPERTIES
-            FOLDER CMakePredefinedTargets
-        )
-    endif()
-endif()
-
-if(CAPSTONE_BUILD_CSTOOL)
-    file(GLOB CSTOOL_SRC cstool/*.c)
-    add_executable(cstool ${CSTOOL_SRC})
-    target_link_libraries(cstool PRIVATE capstone)
-
-    if(CAPSTONE_INSTALL)
-        install(TARGETS cstool EXPORT capstone-targets DESTINATION ${CMAKE_INSTALL_BINDIR})
-    endif()
-endif()
-
-if(CAPSTONE_BUILD_CSTEST)
-    enable_testing()
-    set(CSTEST_DIR ${PROJECT_SOURCE_DIR}/suite/cstest)
-    add_subdirectory(${CSTEST_DIR})
-
-    # Integration and unit tests
-    set(TESTS_INTEGRATION_DIR ${PROJECT_SOURCE_DIR}/tests/integration)
-    add_subdirectory(${TESTS_INTEGRATION_DIR})
-    set(TESTS_UNIT_DIR ${PROJECT_SOURCE_DIR}/tests/unit)
-    add_subdirectory(${TESTS_UNIT_DIR})
-
-    # Unit tests for auto-sync
-    set(AUTO_SYNC_C_TEST_DIR ${PROJECT_SOURCE_DIR}/suite/auto-sync/c_tests/)
-    add_subdirectory(${AUTO_SYNC_C_TEST_DIR})
-endif()

thirdparty/capstone/CMakePresets.json

@@ -1,133 +0,0 @@
-{
-  "version": 3,
-  "configurePresets": [
-    {
-      "name": "locations-base",
-      "hidden": true,
-      "binaryDir": "${sourceDir}/build/${presetName}",
-      "installDir": "${sourceDir}/out/install/${presetName}"
-    },
-    {
-      "name": "warnings-base",
-      "hidden": true,
-      "warnings": {
-        "dev": true,
-        "deprecated": true,
-        "systemVars": true
-      },
-      "errors": {
-        "dev": true,
-        "deprecated": false
-      }
-    },
-    {
-      "name": "ninja",
-      "hidden": true,
-      "displayName": "Ninja",
-      "generator": "Ninja Multi-Config",
-      "cacheVariables": {
-        "CMAKE_DEFAULT_BUILD_TYPE": "Debug"
-      }
-    },
-    {
-      "name": "x64",
-      "hidden": true,
-      "architecture": {
-        "value": "x64",
-        "strategy": "external"
-      }
-    },
-    {
-      "name": "linux-x64",
-      "inherits": [ "ninja", "x64", "locations-base", "warnings-base" ],
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Linux"}
-    },
-    {
-      "name": "macos-x64",
-      "inherits": [ "ninja", "x64", "locations-base", "warnings-base" ],
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Darwin"}
-    },
-    {
-      "name": "windows-x64",
-      "inherits": [ "ninja", "x64", "locations-base", "warnings-base" ],
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Windows"}
-    }
-  ],
-  "buildPresets": [
-    {
-      "name": "build-linux",
-      "configurePreset": "linux-x64",
-      "nativeToolOptions": [ "-v" ],
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Linux"}
-    },
-    {
-      "name": "build-macos",
-      "configurePreset": "macos-x64",
-      "nativeToolOptions": [ "-v" ],
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Darwin"}
-    },
-    {
-      "name": "build-windows",
-      "configurePreset": "windows-x64",
-      "nativeToolOptions": [ "-v" ],
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Windows"}
-    },
-    {
-      "name": "build-linux-release",
-      "inherits": "build-linux",
-      "configuration": "Release",
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Linux"}
-    },
-    {
-      "name": "build-macos-release",
-      "inherits": "build-macos",
-      "configuration": "Release",
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Darwin"}
-    },
-    {
-      "name": "build-windows-release",
-      "inherits": "build-windows",
-      "configuration": "Release",
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Windows"}
-    },
-    {
-      "name": "install-linux",
-      "configurePreset": "linux-x64",
-      "inherits": "build-linux",
-      "targets": [ "install" ],
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Linux"}
-    },
-    {
-      "name": "install-macos",
-      "configurePreset": "macos-x64",
-      "inherits": "build-macos",
-      "targets": [ "install" ],
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Darwin"}
-    },
-    {
-      "name": "install-windows",
-      "configurePreset": "windows-x64",
-      "inherits": "build-windows",
-      "targets": [ "install" ],
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Windows"}
-    },
-    {
-      "name": "install-linux-release",
-      "inherits": "install-linux",
-      "configuration": "Release",
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Linux"}
-    },
-    {
-      "name": "install-macos-release",
-      "inherits": "install-macos",
-      "configuration": "Release",
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Darwin"}
-    },
-    {
-      "name": "install-windows-release",
-      "inherits": "install-windows",
-      "configuration": "Release",
-      "condition": {"type": "equals", "lhs": "${hostSystemName}", "rhs": "Windows"}
-    }
-  ]
-}

thirdparty/capstone/COMPILE_CMAKE.TXT

@@ -1,131 +0,0 @@
-This documentation explains how to compile Capstone with CMake, focus on
-using Microsoft Visual C as the compiler.
-
-To compile Capstone on Windows using Visual Studio, see COMPILE_MSVC.TXT.
-
-                        *-*-*-*-*-*
-
-This documentation requires CMake & Windows SDK or MS Visual Studio installed on
-your machine.
-
-Get CMake for free from http://www.cmake.org.
-
-
-
-(0) Tailor Capstone to your need.
-
-  Out of architectures supported by Capstone, if you just need several selected archs,
-  run "cmake" with the unwanted archs disabled (set to 0) as followings.
-
-  - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM.
-  - CAPSTONE_AARCH64_SUPPORT: support AARCH64. Run cmake with -DCAPSTONE_AARCH64_SUPPORT=0 to remove AARCH64.
-  - CAPSTONE_ALPHA_SUPPORT: support Alpha. Run cmake with -DCAPSTONE_ALPHA_SUPPORT=0 to remove Alpha.
-  - CAPSTONE_HPPA_SUPPORT: support HPPA. Run cmake with -DCAPSTONE_HPPA_SUPPORT=0 to remove HPPA.
-  - CAPSTONE_LOONGARCH_SUPPORT: support LoongArch. Run cmake with -DCAPSTONE_LOONGARCH_SUPPORT=0 to remove LoongArch.
-  - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X.
-  - CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K.
-  - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips.
-  - CAPSTONE_MOS65XX_SUPPORT: support MOS65XX. Run cmake with -DCAPSTONE_MOS65XX_SUPPORT=0 to remove MOS65XX.
-  - CAPSTONE_PPC_SUPPORT: support PPC. Run cmake with -DCAPSTONE_PPC_SUPPORT=0 to remove PPC.
-  - CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc.
-  - CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ.
-  - CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore.
-  - CAPSTONE_TRICORE_SUPPORT: support TriCore. Run cmake with -DCAPSTONE_TRICORE_SUPPORT=0 to remove TriCore.
-  - CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86.
-  - CAPSTONE_TMS320C64X_SUPPORT: support TMS320C64X. Run cmake with -DCAPSTONE_TMS320C64X_SUPPORT=0 to remove TMS320C64X.
-  - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X.
-  - CAPSTONE_EVM_SUPPORT: support EVM. Run cmake with -DCAPSTONE_EVM_SUPPORT=0 to remove EVM.
-  - CAPSTONE_WASM_SUPPORT: support Web Assembly. Run cmake with -DCAPSTONE_WASM_SUPPORT=0 to remove WASM.
-  - CAPSTONE_BPF_SUPPORT: support BPF. Run cmake with -DCAPSTONE_BPF_SUPPORT=0 to remove BPF.
-  - CAPSTONE_RISCV_SUPPORT: support RISCV. Run cmake with -DCAPSTONE_RISCV_SUPPORT=0 to remove RISCV.
-  - CAPSTONE_ARCHITECTURE_DEFAULT: Whether architectures are enabled by default.
-      Set this of OFF with -DCAPSTONE_ARCHITECTURE_DEFAULT=OFF to disable all architectures by default.
-      You can then enable them again with one of the CAPSTONE_<ARCH>_SUPPORT options.
-
-  By default, all architectures are compiled in. If you're building a static library that you intend to link into
-  multiple consumers, and they have differing architecture requirements, you may want -DCAPSTONE_USE_ARCH_REGISTRATION=1
-  and call cs_arch_register_*() for the architectures you need in each particular consumer. In this way you only pay
-  footprint size for the architectures you're actually using in each consumer, without having to compile Capstone
-  multiple times.
-
-  Besides, Capstone also allows some more customization via following macros.
-
-  - CAPSTONE_USE_SYS_DYN_MEM: change this to OFF to use your own dynamic memory management.
-  - CAPSTONE_BUILD_DIET: change this to ON to make the binaries more compact.
-  - CAPSTONE_X86_REDUCE: change this to ON to make X86 binary smaller.
-  - CAPSTONE_X86_ATT_DISABLE: change this to ON to disable AT&T syntax on x86.
-  - CAPSTONE_DEBUG: change this to ON to enable extra debug assertions.
-  - CAPSTONE_BUILD_CSTEST: Build `cstest` in `suite/cstest/`. `cstest` requires `libyaml` on your system.
-  - ENABLE_ASAN: Compiles Capstone with the address sanitizer.
-
-  By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
-  modes are disabled. To use your own memory allocations, turn ON both DIET &
-  X86_REDUCE, run "cmake" with: -DCAPSTONE_USE_SYS_DYN_MEM=0 -DCAPSTONE_BUILD_DIET=1 -DCAPSTONE_X86_REDUCE=1
-
-
-  For each option, refer to docs/README for more details.
-
-
-
-(1) CMake allows you to generate different generators to build Capstone. Below is
-    some examples on how to build Capstone on Windows with CMake.
-
-  (*) You can let CMake select a generator for you. Do:
-  
-      mkdir build
-      cd build
-      cmake ..
-      
-    This last command is also where you can pass additional CMake configuration flags
-    using `-D<key>=<value>`.
-    For a debug build add `-DCMAKE_BUILD_TYPE=Debug`.
-    To export `compile_commands.json` add `-DCMAKE_EXPORT_COMPILE_COMMANDS=ON`.
-    
-    Then to build use:
-    
-      cmake --build . --config [Release/Debug]
-      
-
-  (*) To build Capstone using Nmake of Windows SDK, do:
-
-      mkdir build
-      cd build
-      ..\nmake.bat
-
-  After this, find the samples test*.exe, capstone.lib & capstone.dll
-  in the same directory.
-
-
-
-  (*) To build Capstone using Visual Studio, choose the generator accordingly to the
-  version of Visual Studio on your machine. For example, with Visual Studio 2013, do:
-
-      mkdir build
-      cd build
-      cmake -G "Visual Studio 12" ..
-
-  After this, find capstone.sln in the same directory. Open it with Visual Studio
-  and build the solution including libraries & all test as usual.
-
-
-
-(2) You can make sure the prior steps successfully worked by launching one of the
-  testing binary (test*.exe).
-
-(3) You can also enable just one specific architecture by passing the architecture name
-  to either the cmake.sh or nmake.bat scripts. e.g.:
-  
-    ../cmake.sh x86
-
-  Will just target the x86 architecture. The list of available architectures is: ARM,
-  AARCH64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX,
-  WASM, BPF, RISCV, Alpha, HPPA, LoongArch.
-  
-(4) You can also create an installation image with cmake, by using the 'install' target.
-  Use:
-
-    cmake --build . --config Release --target install
-
-  This will normally install an image in a default location (`C:\Program Files` on Windows),
-  so it's good to explicitly set this location when configuring CMake. Use: `-DCMAKE_INSTALL_PREFIX=image`
-  for instance, to put the installation in the 'image' subdirectory of the build directory.

thirdparty/capstone/COMPILE_MAKE.TXT

@@ -1,215 +0,0 @@
-
-# NOTICE
-
-> Please be aware that the Makefile build is deprecated.
-> Use cmake instead.
-
-<hr>
-
-This documentation explains how to compile, install & run Capstone on MacOSX,
-Linux, *BSD & Solaris. We also show steps to cross-compile for Microsoft Windows.
-
-To natively compile for Windows using Microsoft Visual Studio, see COMPILE_MSVC.TXT.
-
-To compile using CMake, see COMPILE_CMAKE.TXT.
-
-To compile using XCode on MacOSX, see xcode/README.md.
-
-To compile for Windows CE (a.k.a, Windows Embedded Compact), see windowsce/COMPILE.md.
-
-                        *-*-*-*-*-*
-
-Capstone requires no prerequisite packages, so it is easy to compile & install.
-
-
-
-(0) Tailor Capstone to your need.
-
-  Out of all architectures supported by Capstone, if you just need several
-  selected archs, choose the ones you want to compile in by editing "config.mk"
-  before going to next steps.
-
-  By default, all architectures are compiled.
-
-  The other way of customize Capstone without having to edit config.mk is to
-  pass the desired options on the commandline to ./make.sh. Currently,
-  Capstone supports 8 options, as followings.
-
-  - CAPSTONE_ARCHS: specify list of architectures to compiled in.
-  - CAPSTONE_USE_SYS_DYN_MEM: change this if you have your own dynamic memory management.
-  - CAPSTONE_DIET: use this to make the output binaries more compact.
-  - CAPSTONE_X86_REDUCE: another option to make X86 binary smaller.
-  - CAPSTONE_X86_ATT_DISABLE: disables AT&T syntax on x86.
-  - CAPSTONE_STATIC: build static library.
-  - CAPSTONE_SHARED: build dynamic (shared) library.
-  - CAPSTONE_DEBUG: enable debug build supporting assert().
-
-  By default, Capstone uses system dynamic memory management, both DIET and X86_REDUCE
-  modes are disable, and builds all the static & shared libraries.
-
-  To avoid editing config.mk for these customization, we can pass their values to
-  make.sh, as followings.
-
-  $ CAPSTONE_ARCHS="arm aarch64 x86" CAPSTONE_USE_SYS_DYN_MEM=no CAPSTONE_DIET=yes CAPSTONE_X86_REDUCE=yes ./make.sh
-
-  NOTE: on commandline, put these values in front of ./make.sh, not after it.
-
-  For each option, refer to docs/README for more details.
-
-
-
-(1) Compile from source
-
-  On *nix (such as MacOSX, Linux, *BSD, Solaris):
-
-  - To compile for current platform, run:
-
-		$ ./make.sh
-
-  - On 64-bit OS, run the command below to cross-compile Capstone for 32-bit binary:
-
-		$ ./make.sh nix32
-
-
-
-(2) Install Capstone on *nix
-
-  To install Capstone, run:
-
-	$ sudo ./make.sh install
-
-	For FreeBSD/OpenBSD, where sudo is unavailable, run:
-
-		$ su; ./make.sh install
-
-  Users are then required to enter root password to copy Capstone into machine
-  system directories.
-
-  Afterwards, run ./tests/test* to see the tests disassembling sample code.
-
-
-  NOTE: The core framework installed by "./make.sh install" consist of
-  following files:
-
-	/usr/include/capstone/arm.h
-	/usr/include/capstone/arm64.h
-	/usr/include/capstone/alpha.h
-	/usr/include/capstone/bpf.h
-	/usr/include/capstone/capstone.h
-	/usr/include/capstone/evm.h
-	/usr/include/capstone/hppa.h
-	/usr/include/capstone/loongarch.h
-	/usr/include/capstone/m680x.h
-	/usr/include/capstone/m68k.h
-	/usr/include/capstone/mips.h
-	/usr/include/capstone/mos65xx.h
-	/usr/include/capstone/platform.h
-	/usr/include/capstone/ppc.h
-	/usr/include/capstone/sparc.h
-	/usr/include/capstone/systemz.h
-	/usr/include/capstone/tms320c64x.h
-	/usr/include/capstone/wasm.h
-	/usr/include/capstone/x86.h
-	/usr/include/capstone/xcore.h
-	/usr/include/capstone/tricore.h
-	/usr/lib/libcapstone.a
-	/usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX)
-
-
-
-(3) Cross-compile for Windows from *nix
-
-  To cross-compile for Windows, Linux & gcc-mingw-w64-i686 (and also gcc-mingw-w64-x86-64
-  for 64-bit binaries) are required.
-
-	- To cross-compile Windows 32-bit binary, simply run:
-
-		$ ./make.sh cross-win32
-
-	- To cross-compile Windows 64-bit binary, run:
-
-		$ ./make.sh cross-win64
-
-  Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then
-  be used on Windows machine.
-
-
-
-(4) Cross-compile for iOS from Mac OSX.
-
-  To cross-compile for iOS (iPhone/iPad/iPod), Mac OSX with XCode installed is required.
-
-	- To cross-compile for ArmV7 (iPod 4, iPad 1/2/3, iPhone4, iPhone4S), run:
-		$ ./make.sh ios_armv7
-
-	- To cross-compile for ArmV7s (iPad 4, iPhone 5C, iPad mini), run:
-		$ ./make.sh ios_armv7s
-
-	- To cross-compile for Arm64 (iPhone 5S, iPad mini Retina, iPad Air), run:
-		$ ./make.sh ios_arm64
-
-	- To cross-compile for all iDevices (armv7 + armv7s + arm64), run:
-		$ ./make.sh ios
-
-  Resulted files libcapstone.dylib, libcapstone.a & tests/test* can then
-  be used on iOS devices.
-
-
-
-(5) Cross-compile for Android
-
-  To cross-compile for Android (smartphone/tablet), Android NDK is required.
-  NOTE: Only ARM and AARCH64 are currently supported.
-
-	$ NDK=/android/android-ndk-r10e ./make.sh cross-android arm
-  or
-	$ NDK=/android/android-ndk-r10e ./make.sh cross-android arm64
-
-  Resulted files libcapstone.so, libcapstone.a & tests/test* can then
-  be used on Android devices.
-
-
-
-(6) Compile on Windows with Cygwin
-
-  To compile under Cygwin gcc-mingw-w64-i686 or x86_64-w64-mingw32 run:
-
-        - To compile Windows 32-bit binary under Cygwin, run:
-
-                $ ./make.sh cygwin-mingw32
-
-        - To compile Windows 64-bit binary under Cygwin, run:
-
-                $ ./make.sh cygwin-mingw64
-
-  Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then
-  be used on Windows machine.
-
-
-
-(7) By default, "cc" (default C compiler on the system) is used as compiler.
-
-	- To use "clang" compiler instead, run the command below:
-
-		$ ./make.sh clang
-
-	- To use "gcc" compiler instead, run:
-
-		$ ./make.sh gcc
-
-
-
-(8) To uninstall Capstone, run the command below:
-
-		$ sudo ./make.sh uninstall
-
-
-
-(9) Language bindings
-
-  So far, Python, Ocaml & Java are supported by bindings in the main code.
-  Look for the bindings under directory bindings/, and refer to README file
-  of corresponding languages.
-
-  Community also provide bindings for C#, Go, Ruby, NodeJS, C++ & Vala. Links to
-  these can be found at address http://capstone-engine.org/download.html

thirdparty/capstone/COMPILE_MSVC.TXT

@@ -1,125 +0,0 @@
-This documentation explains how to compile Capstone on Windows using
-Microsoft Visual Studio version 2010 or newer.
-
-To compile Capstone on *nix, see COMPILE_CMAKE.TXT
-
-To compile Capstone with CMake, see COMPILE_CMAKE.TXT
-
-                        *-*-*-*-*-*
-
-Capstone requires no prerequisite packages with default configurations, so it is
-easy to compile & install. Open the Visual Studio solution "msvc/capstone.sln"
-and follow the instructions below.
-
-NOTE: This requires Visual Studio 2017 or newer versions.
-
-If you wish to embed Capstone in a kernel driver Windows Driver Kit 8.1 Update 1
-or newer versions are required.
-
-
-(0) Tailor Capstone to your need.
-
-  Out of 9 architectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC,
-  Sparc, SystemZ, X86 & XCore), if you just need several selected archs, choose
-  the ones you want to compile in by opening Visual Studio solution "msvc\capstone.sln",
-  then directly editing the projects "capstone_static" & "capstone_dll" for static
-  and dynamic libraries, respectively. This must be done before going to the next
-  steps.
-
-  In VisualStudio interface, modify the preprocessor definitions via
-  "Project Properties" -> "Configuration Properties" -> "C/C++" -> "Preprocessor"
-  to customize Capstone library, as followings.
-
-  - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support.
-  - CAPSTONE_HAS_AARCH64: support AARCH64. Delete this to remove AARCH64 support.
-  - CAPSTONE_HAS_ALPHA: support Alpha. Delete this to remove Alpha support.
-  - CAPSTONE_HAS_HPPA: support HPPA. Delete this to remove HPPA support.
-  - CAPSTONE_HAS_M68K: support M68K. Delete this to remove M68K support.
-  - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support.
-  - CAPSTONE_HAS_POWERPC: support PPC. Delete this to remove PPC support.
-  - CAPSTONE_HAS_SPARC: support Sparc. Delete this to remove Sparc support.
-  - CAPSTONE_HAS_SYSZ: support SystemZ. Delete this to remove SystemZ support.
-  - CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support.
-  - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support.
-  - CAPSTONE_HAS_TRICORE: support TriCore. Delete this to remove TriCore support.
-
-  By default, all 11 architectures are compiled in.
-
-
-  Besides, Capstone also allows some more customization via following macros.
-
-  - CAPSTONE_USE_SYS_DYN_MEM: delete this to use your own dynamic memory management.
-  - CAPSTONE_DIET_NO: rename this to "CAPSTONE_DIET" to make the binaries more compact.
-  - CAPSTONE_X86_REDUCE_NO: rename this to "CAPSTONE_X86_REDUCE" to make X86 binary smaller.
-  - CAPSTONE_X86_ATT_DISABLE_NO: rename this to "CAPSTONE_X86_ATT_DISABLE" to disable
-    AT&T syntax on x86.
-
-  By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
-  modes are disable.
-
-
-  For each option, refer to docs/README for more details.
-
-
-
-(1) Compile from source on Windows with Visual Studio
-
-  - Choose the configuration and the platform you want: Release/Debug & Win32/Win64.
-  - Build only the libraries, or the libraries along with all the tests.
-  - "capstone_static_winkernel" is for compiling Capstone for a driver and
-    "test_winkernel" is a test for a driver, and those are excluded from build by
-    default. To compile them, open the Configuration Manager through the [Build]
-    menu and check "Build" check boxes for those project.
-
-
-
-(2) You can make sure the prior steps successfully worked by launching one of the
-  testing binary (test*.exe).
-
-  The testing binary for a driver "test_winkernel.sys" is made up of all tests for
-  supported architectures configured with the step (0) along side its own tests.
-  Below explains a procedure to run the test driver and check test results.
-
-  On the x64 platform, the test signing mode has to be enabled to install the test
-  driver. To do it, open the command prompt with the administrator privileges and
-  type the following command, and then restart the system to activate the change:
-
-      >bcdedit /set testsigning on
-
-  Test results from the test driver is sent to kernel debug buffer. In order to
-  see those results, download DebugView and run it with the administrator
-  privileges, then check [Capture Kernel] through the [Capture] menu.
-
-  DebugView: https://technet.microsoft.com/en-us/sysinternals/debugview.aspx
-
-  To install and uninstall the driver, use the 'sc' command. For installing and
-  executing test_winkernel.sys, execute the following commands with the
-  administrator privileges:
-
-      >sc create test_winkernel type= kernel binPath= <full path to test_winkernel.sys>
-      [SC] CreateService SUCCESS
-
-      >sc start test_winkernel
-      [SC] StartService FAILED 995:
-
-      The I/O operation has been aborted because of either a thread exit or an application request.
-
-  To uninstall the driver, execute the following commands with the administrator
-  privileges:
-
-      >sc delete test_winkernel
-      >bcdedit /deletevalue testsigning
-      
-      
-      
-(3) Installing and building capstone via vcpkg
-  
-  You can download and install capstone using the vcpkg(https://github.com/Microsoft/vcpkg) dependency manager:
-
-    git clone https://github.com/Microsoft/vcpkg.git
-    cd vcpkg
-    ./bootstrap-vcpkg.sh
-    ./vcpkg integrate install
-    vcpkg install capstone
-
-  The capstone port in vcpkg is kept up to date by Microsoft team members and community contributors. If the version is out of date, please create an issue or pull request on the vcpkg repository(https://github.com/Microsoft/vcpkg). 

thirdparty/capstone/CREDITS.TXT

@@ -1,92 +0,0 @@
-This file credits all the contributors of the Capstone engine project.
-
-Key developers
-==============
-Nguyen Anh Quynh <aquynh -at- gmail.com>
-Chenxu Wu (kabeor) kabeor@qiling.io
-
-
-Past key developers
-===================
-Tan Sheng Di <shengdi -at- coseinc.com>
-	- Bindings: Ruby
-
-Ben Nagy <ben -at- coseinc.com>
-	- Bindings: Ruby, Go
-
-Dang Hoang Vu <dang.hvu -at- gmail.com>
-	- Bindings: Java
-
-
-Beta testers (in random order)
-==============================
-Pancake
-Van Hauser
-FX of Phenoelit
-The Grugq, The Grugq   <-- our hero for submitting the first ever patch!
-Isaac Dawson, Veracode Inc
-Patroklos Argyroudis, Census Inc. (http://census-labs.com)
-Attila Suszter
-Le Dinh Long
-Nicolas Ruff
-Gunther
-Alex Ionescu, Winsider Seminars & Solutions Inc.
-Snare
-Daniel Godas-Lopez
-Joshua J. Drake
-Edgar Barbosa
-Ralf-Philipp Weinmann
-Hugo Fortier
-Joxean Koret
-Bruce Dang
-Andrew Dunham
-
-
-Contributors (in no particular order)
-=====================================
-(Please let us know if you want to have your name here)
-
-Ole André Vadla Ravnås (author of the 100th Pull-Request in our Github repo, thanks!)
-Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC.
-Daniel Pistelli: Cmake support.
-Peter Hlavaty: integrate Capstone for Windows kernel drivers.
-Guillaume Jeanne: Ocaml binding.
-Martin Tofall, Obsidium Software: Optimize X86 performance & size + x86 encoding features.
-David Martínez Moreno & Hilko Bengen: Debian package.
-Félix Cloutier: Xcode project.
-Benoit Lecocq: OpenBSD package.
-Christophe Avoinne (Hlide): Improve memory management for better performance.
-Michael Cohen & Nguyen Tan Cong: Python module installer.
-Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
-Felix Gröbert (Google): fuzz testing harness.
-Xipiter LLC: Capstone logo redesigned.
-Satoshi Tanda: Support Windows kernel driver.
-Tang Yuhang: cstool.
-Andrew Dutcher: better Python setup.
-Ruben Boonen: PowerShell binding.
-David Zimmer: VB6 binding.
-Philippe Antoine: Integration with oss-fuzz and various fixes.
-Bui Dinh Cuong: Explicit registers accessed for Arm64.
-Vincent Bénony: Explicit registers accessed for X86.
-Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
-Felix Gröbert (Google): fuzz testing harness.
-Daniel Collin & Nicolas Planel: M68K architecture.
-Pranith Kumar: Explicit registers accessed for Arm64.
-Xipiter LLC: Capstone logo redesigned.
-Satoshi Tanda: Support Windows kernel driver.
-Koutheir Attouchi: Support for Windows CE.
-Fotis Loukos: TMS320C64x architecture.
-Wolfgang Schwotzer: M680X architecture.
-Philippe Antoine: Integration with oss-fuzz and various fixes.
-Stephen Eckels (stevemk14ebr): x86 encoding features
-Tong Yu(Spike) & Kai Jern, Lau (xwings): WASM architecture.
-Sebastian Macke: MOS65XX architecture
-Ilya Leoshkevich: SystemZ architecture improvements.
-Do Minh Tuan: Regression testing tool (cstest)
-david942j: BPF (both classic and extended) architecture.
-fanfuqiang & citypw & porto703 : RISCV architecture.
-Josh "blacktop" Maine: Arm64 architecture improvements.
-Finn Wilkinson: AArch64 update to Armv9.2-a (SME + SVE2 support)
-Billow & Sidneyp : TriCore architecture.
-Dmitry Sibirtsev: Alpha & HPPA architecture.
-Jiajie Chen & Yanglin Xun: LoongArch architecture.

thirdparty/capstone/HACK.TXT

@@ -1,135 +0,0 @@
-Code structure
---------------
-
-Capstone source is organized as followings.
-
-.                   <- core engine + README + COMPILE_CMAKE.TXT etc
-├── arch            <- code handling disasm engine for each arch
-│   ├── AArch64     <- AArch64 engine
-│   ├── Alpha       <- Alpha engine
-│   ├── ARM         <- ARM engine
-│   ├── BPF         <- Berkeley Packet Filter engine
-│   ├── EVM         <- Ethereum engine
-│   ├── HPPA        <- HPPA engine
-│   ├── M680X       <- M680X engine
-│   ├── M68K        <- M68K engine
-│   ├── Mips        <- Mips engine
-│   ├── MOS65XX     <- MOS65XX engine
-│   ├── PowerPC     <- PowerPC engine
-│   ├── RISCV       <- RISCV engine
-│   ├── SH          <- SH engine
-│   ├── Sparc       <- Sparc engine
-│   ├── SystemZ     <- SystemZ engine
-│   ├── TMS320C64x  <- TMS320C64x engine
-│   ├── TriCore     <- TriCore engine
-│   └── WASM        <- WASM engine
-├── bindings        <- all bindings are under this dir
-│   ├── java        <- Java bindings + test code
-│   ├── ocaml       <- Ocaml bindings + test code
-│   └── python      <- Python bindings + test code
-├── contrib         <- Code contributed by community to help Capstone integration
-├── cstool          <- Cstool
-├── docs            <- Documentation
-├── include         <- API headers in C language (*.h)
-├── msvc            <- Microsoft Visual Studio support (for Windows compile)
-├── packages        <- Packages for Linux/OSX/BSD.
-├── windows         <- Windows support (for Windows kernel driver compile)
-├── suite           <- Development test tools - for Capstone developers only
-├── tests           <- Test code (in C language)
-└── xcode           <- Xcode support (for MacOSX compile)
-
-
-Follow the instructions in COMPILE_CMAKE.TXT for how to compile and run test code.
-
-Note: if you find some strange bugs, it is recommended to firstly clean
-the code and try to recompile/reinstall again. This can be done with:
-
-	$ ./make.sh
-	$ sudo ./make.sh install
-
-Then test Capstone with cstool, for example:
-
-	$ cstool x32 "90 91"
-
-At the same time, for Java/Ocaml/Python bindings, be sure to always use
-the bindings coming with the core to avoid potential incompatibility issue
-with older versions.
-See bindings/<language>/README for detail instructions on how to compile &
-install the bindings.
-
-
-Coding style
-------------
-- C code follows Linux kernel coding style, using tabs for indentation.
-- Python code uses 4 spaces for indentation.
-
-Updating an Architecture
-------------------------
-
-The update tool for Capstone is called `auto-sync` and can be found in `suite/auto-sync`.
-
-Not all architectures are supported yet.
-Run `suite/auto-sync/Updater/ASUpdater.py -h` to get a list of currently supported architectures.
-
-The documentation how to update with `auto-sync` or refactor an architecture module
-can be found in [docs/AutoSync.md](docs/AutoSync.md).
-
-If a module does not support `auto-sync` yet, it is highly recommended to refactor it
-instead of attempting to update it manually.
-Refactoring will take less time and updates it during the procedure.
-
-The one exception is `x86`. In LLVM we use several emitter backends to generate C code.
-One of those LLVM backends (the `DecoderEmitter`) has two versions.
-One for `x86` and another for all the other architectures.
-Until now it was not worth it to refactoring this unique `x86` backend. So `x86` is not
-supported currently.
-
-Adding an architecture
-----------------------
-
-If your architecture is supported in LLVM or one of its forks, you can use `auto-sync` to
-add the new module.
-
-<!-- TODO: Move this info to the auto-sync docs -->
-
-Obviously, you first need to write all the logic and put it in a new directory arch/newarch
-Then, you have to modify other files.
-(You can look for one architecture such as EVM in these files to get what you need to do)
-
-Integrate:
-- cs.c
-- cstool/cstool.c
-- cstool/cstool_newarch.c: print the architecture specific details
-- include/capstone/capstone.h
-- include/capstone/newarch.h: create this file to export all specifics about the new architecture
-
-Compile:
-- CMakeLists.txt
-- Makefile
-- config.mk
-
-Tests:
-- tests/Makefile
-- tests/test_basic.c
-- tests/test_iter.c
-- tests/test_newarch.c
-- suite/fuzz/platform.c: add the architecture and its modes to the list of fuzzed platforms
-- suite/capstone_get_setup.c
-- suite/MC/newarch/mode.mc: samples
-- suite/test_corpus.py: correspondence between architecture and mode as text and architecture number for fuzzing
-- suite/cstest/
-
-Bindings:
-- bindings/Makefile
-- bindings/const_generator.py: add the header file and the architecture
-- bindings/python/Makefile
-- bindings/python/capstone/__init__.py
-- bindings/python/capstone/newarch.py: define the python structures
-- bindings/python/capstone/newarch_const.py: generate this file
-- bindings/python/test_newarch.py: create a basic decoding test
-- bindings/python/test_all.py
-
-Docs:
-- README.md
-- HACK.txt
-- CREDITS.txt: add your name

thirdparty/capstone/LEB128.h

@@ -1,38 +0,0 @@
-//===- llvm/Support/LEB128.h - [SU]LEB128 utility functions -----*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file declares some utility functions for encoding SLEB128 and
-// ULEB128 values.
-//
-//===----------------------------------------------------------------------===//
-
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#ifndef CS_LLVM_SUPPORT_LEB128_H
-#define CS_LLVM_SUPPORT_LEB128_H
-
-#include "include/capstone/capstone.h"
-
-/// Utility function to decode a ULEB128 value.
-static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n)
-{
-	const uint8_t *orig_p = p;
-	uint64_t Value = 0;
-	unsigned Shift = 0;
-	do {
-		Value += (uint64_t)(*p & 0x7f) << Shift;
-		Shift += 7;
-	} while (*p++ >= 128);
-	if (n)
-		*n = (unsigned)(p - orig_p);
-	return Value;
-}
-
-#endif  // LLVM_SYSTEM_LEB128_H

thirdparty/capstone/LICENSES/LICENSE.TXT

@@ -1,31 +0,0 @@
-This is the software license for Capstone disassembly framework.
-Capstone has been designed & implemented by Nguyen Anh Quynh <aquynh@gmail.com>
-
-See http://www.capstone-engine.org for further information.
-
-Copyright (c) 2013, COSEINC.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice,
-  this list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice,
-  this list of conditions and the following disclaimer in the documentation
-  and/or other materials provided with the distribution.
-* Neither the name of the developer(s) nor the names of its
-  contributors may be used to endorse or promote products derived from this
-  software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.

thirdparty/capstone/LICENSES/LICENSE_BSD_3_CLAUSE.txt

@@ -1,11 +0,0 @@
-Copyright (c) <year> <owner>. 
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
-
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
-
-2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
-
-3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

thirdparty/capstone/LICENSES/LICENSE_LLVM.TXT

@@ -1,71 +0,0 @@
-==============================================================================
-LLVM Release License
-==============================================================================
-University of Illinois/NCSA
-Open Source License
-
-Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign.
-All rights reserved.
-
-Developed by:
-
-    LLVM Team
-
-    University of Illinois at Urbana-Champaign
-
-    http://llvm.org
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal with
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-    * Redistributions of source code must retain the above copyright notice,
-      this list of conditions and the following disclaimers.
-
-    * Redistributions in binary form must reproduce the above copyright notice,
-      this list of conditions and the following disclaimers in the
-      documentation and/or other materials provided with the distribution.
-
-    * Neither the names of the LLVM Team, University of Illinois at
-      Urbana-Champaign, nor the names of its contributors may be used to
-      endorse or promote products derived from this Software without specific
-      prior written permission.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
-CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
-SOFTWARE.
-
-==============================================================================
-Copyrights and Licenses for Third Party Software Distributed with LLVM:
-==============================================================================
-The LLVM software contains code written by third parties.  Such software will
-have its own individual LICENSE.TXT file in the directory in which it appears.
-This file will describe the copyrights, license, and restrictions which apply
-to that code.
-
-The disclaimer of warranty in the University of Illinois Open Source License
-applies to all code in the LLVM Distribution, and nothing in any of the
-other licenses gives permission to use the names of the LLVM Team or the
-University of Illinois to endorse or promote products derived from this
-Software.
-
-The following pieces of software have additional or alternate copyrights,
-licenses, and/or restrictions:
-
-Program             Directory
--------             ---------
-Autoconf            llvm/autoconf
-                    llvm/projects/ModuleMaker/autoconf
-                    llvm/projects/sample/autoconf
-Google Test         llvm/utils/unittest/googletest
-OpenBSD regex       llvm/lib/Support/{reg*, COPYRIGHT.regex}
-pyyaml tests        llvm/test/YAMLParser/{*.data, LICENSE.TXT}
-ARM contributions   llvm/lib/Target/ARM/LICENSE.TXT
-md5 contributions   llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h

thirdparty/capstone/MCDisassembler.h

@@ -1,14 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#ifndef CS_MCDISASSEMBLER_H
-#define CS_MCDISASSEMBLER_H
-
-typedef enum DecodeStatus {
-	MCDisassembler_Fail = 0,
-	MCDisassembler_SoftFail = 1,
-	MCDisassembler_Success = 3,
-} DecodeStatus;
-
-#endif
-

thirdparty/capstone/MCFixedLenDisassembler.h

@@ -1,32 +0,0 @@
-//===-- llvm/MC/MCFixedLenDisassembler.h - Decoder driver -------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-// Fixed length disassembler decoder state machine driver.
-//===----------------------------------------------------------------------===//
-
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
-#define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
-
-// Disassembler state machine opcodes.
-enum DecoderOps {
-	MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len)
-	MCD_OPC_FilterValue,      // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip)
-	MCD_OPC_CheckField,       // OPC_CheckField(uint8_t Start, uint8_t Len,
-							  //                uleb128 Val, uint16_t NumToSkip)
-	MCD_OPC_CheckPredicate,   // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip)
-	MCD_OPC_Decode,           // OPC_Decode(uleb128 Opcode, uleb128 DIdx)
-        MCD_OPC_TryDecode,        // OPC_TryDecode(uleb128 Opcode, uleb128 DIdx,
-                                  //               uint16_t NumToSkip)	
-	MCD_OPC_SoftFail,         // OPC_SoftFail(uleb128 PMask, uleb128 NMask)
-	MCD_OPC_Fail              // OPC_Fail()
-};
-
-#endif

thirdparty/capstone/MCInst.c

@@ -1,313 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-#if defined(CAPSTONE_HAS_OSXKERNEL)
-#include <Availability.h>
-#include <libkern/libkern.h>
-#else
-#include <stdio.h>
-#include <stdlib.h>
-#endif
-#include <string.h>
-#include <assert.h>
-
-#include "MCInstrDesc.h"
-#include "MCInst.h"
-#include "utils.h"
-
-#define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1)
-
-void MCInst_Init(MCInst *inst)
-{
-	// unnecessary to initialize in loop . its expensive and inst->size should be honored
-	inst->Operands[0].Kind = kInvalid;
-	inst->Operands[0].ImmVal = 0;
-
-	inst->Opcode = 0;
-	inst->OpcodePub = 0;
-	inst->size = 0;
-	inst->has_imm = false;
-	inst->op1_size = 0;
-	inst->ac_idx = 0;
-	inst->popcode_adjust = 0;
-	inst->assembly[0] = '\0';
-	inst->wasm_data.type = WASM_OP_INVALID;
-	inst->xAcquireRelease = 0;
-	for (int i = 0; i < MAX_MC_OPS; ++i)
-		inst->tied_op_idx[i] = -1;
-	inst->isAliasInstr = false;
-	inst->fillDetailOps = false;
-	memset(&inst->hppa_ext, 0, sizeof(inst->hppa_ext));
-}
-
-void MCInst_clear(MCInst *inst)
-{
-	inst->size = 0;
-}
-
-// does not free @Op
-void MCInst_insert0(MCInst *inst, int index, MCOperand *Op)
-{
-	assert(index < MAX_MC_OPS);
-	int i;
-
-	for(i = inst->size; i > index; i--)
-		//memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand));
-		inst->Operands[i] = inst->Operands[i-1];
-
-	inst->Operands[index] = *Op;
-	inst->size++;
-}
-
-void MCInst_setOpcode(MCInst *inst, unsigned Op)
-{
-	inst->Opcode = Op;
-}
-
-void MCInst_setOpcodePub(MCInst *inst, unsigned Op)
-{
-	inst->OpcodePub = Op;
-}
-
-unsigned MCInst_getOpcode(const MCInst *inst)
-{
-	return inst->Opcode;
-}
-
-unsigned MCInst_getOpcodePub(const MCInst *inst)
-{
-	return inst->OpcodePub;
-}
-
-MCOperand *MCInst_getOperand(MCInst *inst, unsigned i)
-{
-	assert(i < MAX_MC_OPS);
-	return &inst->Operands[i];
-}
-
-unsigned MCInst_getNumOperands(const MCInst *inst)
-{
-	return inst->size;
-}
-
-// This addOperand2 function doesn't free Op
-void MCInst_addOperand2(MCInst *inst, MCOperand *Op)
-{
-	assert(inst->size < MAX_MC_OPS);
-	inst->Operands[inst->size] = *Op;
-
-	inst->size++;
-}
-
-bool MCOperand_isValid(const MCOperand *op)
-{
-	return op->Kind != kInvalid;
-}
-
-bool MCOperand_isReg(const MCOperand *op)
-{
-	return op->Kind == kRegister || op->MachineOperandType == kRegister;
-}
-
-bool MCOperand_isImm(const MCOperand *op)
-{
-	return op->Kind == kImmediate || op->MachineOperandType == kImmediate;
-}
-
-bool MCOperand_isFPImm(const MCOperand *op)
-{
-	return op->Kind == kFPImmediate;
-}
-
-bool MCOperand_isDFPImm(const MCOperand *op)
-{
-	return op->Kind == kDFPImmediate;
-}
-
-bool MCOperand_isExpr(const MCOperand *op)
-{
-	return op->Kind == kExpr;
-}
-
-bool MCOperand_isInst(const MCOperand *op)
-{
-	return op->Kind == kInst;
-}
-
-/// getReg - Returns the register number.
-unsigned MCOperand_getReg(const MCOperand *op)
-{
-	return op->RegVal;
-}
-
-/// setReg - Set the register number.
-void MCOperand_setReg(MCOperand *op, unsigned Reg)
-{
-	op->RegVal = Reg;
-}
-
-int64_t MCOperand_getImm(const MCOperand *op)
-{
-	return op->ImmVal;
-}
-
-void MCOperand_setImm(MCOperand *op, int64_t Val)
-{
-	op->ImmVal = Val;
-}
-
-double MCOperand_getFPImm(const MCOperand *op)
-{
-	return op->FPImmVal;
-}
-
-void MCOperand_setFPImm(MCOperand *op, double Val)
-{
-	op->FPImmVal = Val;
-}
-
-MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg)
-{
-	MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
-
-	op->MachineOperandType = kRegister;
-	op->Kind = kRegister;
-	op->RegVal = Reg;
-
-	return op;
-}
-
-void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg)
-{
-	MCOperand *op = &(mcInst->Operands[mcInst->size]);
-	mcInst->size++;
-
-	op->MachineOperandType = kRegister;
-	op->Kind = kRegister;
-	op->RegVal = Reg;
-}
-
-MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val)
-{
-	MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
-
-	op->MachineOperandType = kImmediate;
-	op->Kind = kImmediate;
-	op->ImmVal = Val;
-
-	return op;
-}
-
-void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val)
-{
-	assert(mcInst->size < MAX_MC_OPS);
-	MCOperand *op = &(mcInst->Operands[mcInst->size]);
-	mcInst->size++;
-
-	op->MachineOperandType = kImmediate;
-	op->Kind = kImmediate;
-	op->ImmVal = Val;
-}
-
-/// Check if any operand of the MCInstrDesc is predicable
-bool MCInst_isPredicable(const MCInstrDesc *MIDesc)
-{
-	const MCOperandInfo *OpInfo = MIDesc->OpInfo;
-	unsigned NumOps = MIDesc->NumOperands;
-	for (unsigned i = 0; i < NumOps; ++i) {
-		if (MCOperandInfo_isPredicate(&OpInfo[i])) {
-			return true;
-		}
-	}
-	return false;
-}
-
-/// Checks if tied operands exist in the instruction and sets
-/// - The writeback flag in detail
-/// - Saves the indices of the tied destination operands.
-void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDescTable, unsigned tbl_size)
-{
-	const MCInstrDesc *InstDesc = NULL;
-	const MCOperandInfo *OpInfo = NULL;
-	unsigned short NumOps = 0;
-	if (MI->csh->arch == CS_ARCH_ARM) {
-		// Uses old (pre LLVM 18) indexing method.
-		InstDesc = &InstDescTable[MCInst_getOpcode(MI)];
-		OpInfo = InstDescTable[MCInst_getOpcode(MI)].OpInfo;
-		NumOps = InstDescTable[MCInst_getOpcode(MI)].NumOperands;
-	} else {
-		InstDesc = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size);
-		OpInfo = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size)->OpInfo;
-		NumOps = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size)->NumOperands;
-	}
-
-	for (unsigned i = 0; i < NumOps; ++i) {
-		if (MCOperandInfo_isTiedToOp(&OpInfo[i])) {
-			int idx = MCOperandInfo_getOperandConstraint(
-				InstDesc, i,
-				MCOI_TIED_TO);
-
-			if (idx == -1)
-				continue;
-
-			if (i >= MAX_MC_OPS) {
-				assert(0 &&
-				       "Maximum number of MC operands reached.");
-			}
-			MI->tied_op_idx[i] = idx;
-
-			if (MI->flat_insn->detail)
-				MI->flat_insn->detail->writeback = true;
-		}
-	}
-}
-
-/// Check if operand with OpNum is tied by another operand
-/// (operand is tying destination).
-bool MCInst_opIsTied(const MCInst *MI, unsigned OpNum)
-{
-	assert(OpNum < MAX_MC_OPS && "Maximum number of MC operands exceeded.");
-	for (int i = 0; i < MAX_MC_OPS; ++i) {
-		if (MI->tied_op_idx[i] == OpNum)
-			return true;
-	}
-	return false;
-}
-
-/// Check if operand with OpNum is tying another operand
-/// (operand is tying src).
-bool MCInst_opIsTying(const MCInst *MI, unsigned OpNum)
-{
-	assert(OpNum < MAX_MC_OPS && "Maximum number of MC operands exceeded.");
-	return MI->tied_op_idx[OpNum] != -1;
-}
-
-/// Returns the value of the @MCInst operand at index @OpNum.
-uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum)
-{
-	assert(OpNum < MAX_MC_OPS);
-	MCOperand *op = MCInst_getOperand(MI, OpNum);
-	if (MCOperand_isReg(op))
-		return MCOperand_getReg(op);
-	else if (MCOperand_isImm(op))
-		return MCOperand_getImm(op);
-	else
-		assert(0 && "Operand type not handled in this getter.");
-	return MCOperand_getImm(op);
-}
-
-void MCInst_setIsAlias(MCInst *MI, bool Flag) {
-	assert(MI);
-	MI->isAliasInstr = Flag;
-	MI->flat_insn->is_alias = Flag;
-}
-
-/// @brief Copies the relevant members of a temporary MCInst to
-/// the main MCInst. This is used if TryDecode was run on a temporary MCInst.
-/// @param MI The main MCInst
-/// @param TmpMI The temporary MCInst.
-void MCInst_updateWithTmpMI(MCInst *MI, MCInst *TmpMI) {
-	MI->size = TmpMI->size;
-	MI->Opcode = TmpMI->Opcode;
-	assert(MI->size < MAX_MC_OPS);
-	memcpy(MI->Operands, TmpMI->Operands, sizeof(MI->Operands[0]) * MI->size);
-}

thirdparty/capstone/MCInst.h

@@ -1,178 +0,0 @@
-//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the declaration of the MCInst and MCOperand classes, which
-// is the basic representation used to represent low-level machine code
-// instructions.
-//
-//===----------------------------------------------------------------------===//
-
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#ifndef CS_MCINST_H
-#define CS_MCINST_H
-
-#include "include/capstone/capstone.h"
-#include "MCInstrDesc.h"
-#include "MCRegisterInfo.h"
-
-typedef struct MCInst MCInst;
-typedef struct cs_struct cs_struct;
-typedef struct MCOperand MCOperand;
-typedef unsigned MCRegister;
-
-/// MCOperand - Instances of this class represent operands of the MCInst class.
-/// This is a simple discriminated union.
-struct MCOperand {
-	enum {
-		kInvalid = 0,  ///< Uninitialized.
-		kRegister,     ///< Register operand.
-		kImmediate,    ///< Immediate operand.
-		kFPImmediate,  ///< Floating-point immediate operand.
-		kDFPImmediate, ///< Double-Floating-point immediate operand.
-		kExpr,	       ///< Relocatable immediate operand.
-		kInst	       ///< Sub-instruction operand.
-	} MachineOperandType;
-	unsigned char Kind;
-
-	union {
-		uint64_t RegVal;
-		int64_t ImmVal;
-		double FPImmVal;
-	};
-};
-
-bool MCOperand_isValid(const MCOperand *op);
-
-bool MCOperand_isReg(const MCOperand *op);
-
-bool MCOperand_isImm(const MCOperand *op);
-
-bool MCOperand_isFPImm(const MCOperand *op);
-
-bool MCOperand_isDFPImm(const MCOperand *op);
-
-bool MCOperand_isExpr(const MCOperand *op);
-
-bool MCOperand_isInst(const MCOperand *op);
-
-/// getReg - Returns the register number.
-unsigned MCOperand_getReg(const MCOperand *op);
-
-/// setReg - Set the register number.
-void MCOperand_setReg(MCOperand *op, unsigned Reg);
-
-int64_t MCOperand_getImm(const MCOperand *op);
-
-void MCOperand_setImm(MCOperand *op, int64_t Val);
-
-double MCOperand_getFPImm(const MCOperand *op);
-
-void MCOperand_setFPImm(MCOperand *op, double Val);
-
-const MCInst *MCOperand_getInst(const MCOperand *op);
-
-void MCOperand_setInst(MCOperand *op, const MCInst *Val);
-
-// create Reg operand in the next slot
-void MCOperand_CreateReg0(MCInst *inst, unsigned Reg);
-
-// create Reg operand use the last-unused slot
-MCOperand *MCOperand_CreateReg1(MCInst *inst, unsigned Reg);
-
-// create Imm operand in the next slot
-void MCOperand_CreateImm0(MCInst *inst, int64_t Val);
-
-// create Imm operand in the last-unused slot
-MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val);
-
-#define MAX_MC_OPS 48
-
-/// MCInst - Instances of this class represent a single low-level machine
-/// instruction.
-struct MCInst {
-	unsigned OpcodePub;  // public opcode (<arch>_INS_yyy in header files <arch>.h)
-	uint8_t size;	// number of operands
-	bool has_imm;	// indicate this instruction has an X86_OP_IMM operand - used for ATT syntax
-	uint8_t op1_size; // size of 1st operand - for X86 Intel syntax
-	unsigned Opcode;  // private opcode
-	MCOperand Operands[MAX_MC_OPS];
-	cs_insn *flat_insn;	// insn to be exposed to public
-	uint64_t address;	// address of this insn
-	cs_struct *csh;	// save the main csh
-	uint8_t x86opsize;	// opsize for [mem] operand
-
-	// These flags could be used to pass some info from one target subcomponent
-	// to another, for example, from disassembler to asm printer. The values of
-	// the flags have any sense on target level only (e.g. prefixes on x86).
-	unsigned flags;
-
-	// (Optional) instruction prefix, which can be up to 4 bytes.
-	// A prefix byte gets value 0 when irrelevant.
-	// This is copied from cs_x86 struct
-	uint8_t x86_prefix[4];
-	uint8_t imm_size;	// immediate size for X86_OP_IMM operand
-	bool writeback;		// writeback for ARM
-	int8_t tied_op_idx
-		[MAX_MC_OPS]; ///< Tied operand indices. Index = Src op; Value: Dest op
-	// operand access index for list of registers sharing the same access right (for ARM)
-	uint8_t ac_idx;
-	uint8_t popcode_adjust;   // Pseudo X86 instruction adjust
-	char assembly[8];	// for special instruction, so that we don't need printer
-	unsigned char evm_data[32];	// for EVM PUSH operand
-	cs_wasm_op wasm_data;    // for WASM operand
-	MCRegisterInfo *MRI;
-	uint8_t xAcquireRelease;   // X86 xacquire/xrelease
-	bool isAliasInstr; // Flag if this MCInst is an alias.
-	bool fillDetailOps; // If set, detail->operands gets filled.
-	hppa_ext hppa_ext;	///< for HPPA operand. Contains info about modifiers and their effect on the instruction
-};
-
-void MCInst_Init(MCInst *inst);
-
-void MCInst_clear(MCInst *inst);
-
-// do not free operand after inserting
-void MCInst_insert0(MCInst *inst, int index, MCOperand *Op);
-
-void MCInst_setOpcode(MCInst *inst, unsigned Op);
-
-unsigned MCInst_getOpcode(const MCInst*);
-
-void MCInst_setOpcodePub(MCInst *inst, unsigned Op);
-
-unsigned MCInst_getOpcodePub(const MCInst*);
-
-MCOperand *MCInst_getOperand(MCInst *inst, unsigned i);
-
-unsigned MCInst_getNumOperands(const MCInst *inst);
-
-// This addOperand2 function doesn't free Op
-void MCInst_addOperand2(MCInst *inst, MCOperand *Op);
-
-bool MCInst_isPredicable(const MCInstrDesc *MIDesc);
-
-void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDescTable, unsigned tbl_size);
-
-bool MCInst_opIsTied(const MCInst *MI, unsigned OpNum);
-
-bool MCInst_opIsTying(const MCInst *MI, unsigned OpNum);
-
-uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum);
-
-void MCInst_setIsAlias(MCInst *MI, bool Flag);
-
-static inline bool MCInst_isAlias(const MCInst *MI) {
-	return MI->isAliasInstr;
-}
-
-void MCInst_updateWithTmpMI(MCInst *MI, MCInst *TmpMI);
-
-#endif

thirdparty/capstone/MCInstPrinter.c

@@ -1,257 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Rot127 <unisono@quyllur.org>, 2023 */
-
-#include "MCInstPrinter.h"
-#include "cs_priv.h"
-#include <capstone/platform.h>
-
-extern bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
-extern bool PPC_getFeatureBits(unsigned int mode, unsigned int feature);
-extern bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
-extern bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature);
-
-static bool testFeatureBits(const MCInst *MI, uint32_t Value)
-{
-	assert(MI && MI->csh);
-	switch (MI->csh->arch) {
-	default:
-		assert(0 && "Not implemented for current arch.");
-		return false;
-#ifdef CAPSTONE_HAS_ARM
-	case CS_ARCH_ARM:
-		return ARM_getFeatureBits(MI->csh->mode, Value);
-#endif
-#ifdef CAPSTONE_HAS_POWERPC
-	case CS_ARCH_PPC:
-		return PPC_getFeatureBits(MI->csh->mode, Value);
-#endif
-#ifdef CAPSTONE_HAS_AARCH64
-	case CS_ARCH_AARCH64:
-		return AArch64_getFeatureBits(MI->csh->mode, Value);
-#endif
-#ifdef CAPSTONE_HAS_TRICORE
-	case CS_ARCH_TRICORE:
-		return TriCore_getFeatureBits(MI->csh->mode, Value);
-#endif
-	}
-}
-
-static bool matchAliasCondition(MCInst *MI, const MCRegisterInfo *MRI,
-								unsigned *OpIdx, const AliasMatchingData *M,
-								const AliasPatternCond *C,
-								bool *OrPredicateResult)
-{
-	// Feature tests are special, they don't consume operands.
-	if (C->Kind == AliasPatternCond_K_Feature)
-		return testFeatureBits(MI, C->Value);
-	if (C->Kind == AliasPatternCond_K_NegFeature)
-		return !testFeatureBits(MI, C->Value);
-	// For feature tests where just one feature is required in a list, set the
-	// predicate result bit to whether the expression will return true, and only
-	// return the real result at the end of list marker.
-	if (C->Kind == AliasPatternCond_K_OrFeature) {
-		*OrPredicateResult |= testFeatureBits(MI, C->Value);
-		return true;
-	}
-	if (C->Kind == AliasPatternCond_K_OrNegFeature) {
-		*OrPredicateResult |= !(testFeatureBits(MI, C->Value));
-		return true;
-	}
-	if (C->Kind == AliasPatternCond_K_EndOrFeatures) {
-		bool Res = *OrPredicateResult;
-		*OrPredicateResult = false;
-		return Res;
-	}
-
-	// Get and consume an operand.
-	MCOperand *Opnd = MCInst_getOperand(MI, *OpIdx);
-	++(*OpIdx);
-
-	// Check the specific condition for the operand.
-	switch (C->Kind) {
-	default:
-		assert(0 && "invalid kind");
-	case AliasPatternCond_K_Imm:
-		// Operand must be a specific immediate.
-		return MCOperand_isImm(Opnd) &&
-			   MCOperand_getImm(Opnd) == (int32_t)C->Value;
-	case AliasPatternCond_K_Reg:
-		// Operand must be a specific register.
-		return MCOperand_isReg(Opnd) && MCOperand_getReg(Opnd) == C->Value;
-	case AliasPatternCond_K_TiedReg:
-		// Operand must match the register of another operand.
-		return MCOperand_isReg(Opnd) &&
-			   MCOperand_getReg(Opnd) ==
-				   MCOperand_getReg(MCInst_getOperand(MI, C->Value));
-	case AliasPatternCond_K_RegClass:
-		// Operand must be a register in this class. Value is a register class
-		// id.
-		return MCOperand_isReg(Opnd) &&
-			   MCRegisterClass_contains(
-				   MCRegisterInfo_getRegClass(MRI, C->Value),
-				   MCOperand_getReg(Opnd));
-	case AliasPatternCond_K_Custom:
-		// Operand must match some custom criteria.
-		assert(M->ValidateMCOperand && "A custom validator should be set but isn't.");
-		return M->ValidateMCOperand(Opnd, C->Value);
-	case AliasPatternCond_K_Ignore:
-		// Operand can be anything.
-		return true;
-	case AliasPatternCond_K_Feature:
-	case AliasPatternCond_K_NegFeature:
-	case AliasPatternCond_K_OrFeature:
-	case AliasPatternCond_K_OrNegFeature:
-	case AliasPatternCond_K_EndOrFeatures:
-		assert(0 && "handled earlier");
-	}
-	return false;
-}
-
-/// Check if PatternsForOpcode is all zero.
-static inline bool validOpToPatter(const PatternsForOpcode *P)
-{
-	return !(P->Opcode == 0 && P->PatternStart == 0 && P->NumPatterns == 0);
-}
-
-const char *matchAliasPatterns(MCInst *MI, const AliasMatchingData *M)
-{
-	// TODO Rewrite to C
-
-	// auto It = lower_bound(M.OpToPatterns, MI->getOpcode(),
-	//                       [](const PatternsForOpcode &L, unsigned Opcode) {
-	//                         return L.Opcode < Opcode;
-	//                       });
-	// if (It == M.OpToPatterns.end() || It->Opcode != MI->getOpcode())
-	//   return nullptr;
-
-	// Binary search by opcode. Return false if there are no aliases for this
-	// opcode.
-	unsigned MIOpcode = MI->Opcode;
-	size_t i = 0;
-	uint32_t PatternOpcode = M->OpToPatterns[i].Opcode;
-	while (PatternOpcode < MIOpcode && validOpToPatter(&M->OpToPatterns[i]))
-		PatternOpcode = M->OpToPatterns[++i].Opcode;
-	if (PatternOpcode != MI->Opcode || !validOpToPatter(&M->OpToPatterns[i]))
-		return NULL;
-
-	// // Try all patterns for this opcode.
-	uint32_t AsmStrOffset = ~0U;
-	const AliasPattern *Patterns = M->Patterns + M->OpToPatterns[i].PatternStart;
-	for (const AliasPattern *P = Patterns;
-		P != Patterns + M->OpToPatterns[i].NumPatterns; ++P) {
-		// Check operand count first.
-		if (MCInst_getNumOperands(MI) != P->NumOperands)
-			return NULL;
-
-		// Test all conditions for this pattern.
-		const AliasPatternCond *Conds = M->PatternConds + P->AliasCondStart;
-		unsigned OpIdx = 0;
-		bool OrPredicateResult = false;
-		bool allMatch = true;
-		for (const AliasPatternCond *C = Conds; C != Conds + P->NumConds; ++C) {
-			if (!matchAliasCondition(MI, MI->MRI, &OpIdx, M, C, &OrPredicateResult)) {
-				allMatch = false;
-				break;
-			}
-		}
-		if (allMatch) {
-			AsmStrOffset = P->AsmStrOffset;
-			break;
-		}
-	}
-	// If no alias matched, don't print an alias.
-	if (AsmStrOffset == ~0U)
-		return NULL;
-
-	// Go to offset AsmStrOffset and use the null terminated string there. The
-	// offset should point to the beginning of an alias string, so it should
-	// either be zero or be preceded by a null byte.
-	return M->AsmStrings + AsmStrOffset;
-}
-
-// TODO Add functionality to toggle the flag.
-bool getUseMarkup(void) { return false; }
-
-/// Utility functions to make adding mark ups simpler.
-const char *markup(const char *s)
-{
-	static const char *no_markup = "";
-	if (getUseMarkup())
-		return s;
-	else
-		return no_markup;
-}
-
-// binary search for encoding in IndexType array
-// return -1 if not found, or index if found
-unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding)
-{
-	// binary searching since the index is sorted in encoding order
-	size_t left, right, m;
-
-	right = size - 1;
-
-	if (encoding < index[0].encoding || encoding > index[right].encoding)
-		// not found
-		return -1;
-
-	left = 0;
-
-	while(left <= right) {
-		m = (left + right) / 2;
-		if (encoding == index[m].encoding) {
-			// LLVM actually uses lower_bound for the index table search
-			// Here we need to check if a previous entry is of the same encoding
-			// and return the first one.
-			while (m > 0 && encoding == index[m - 1].encoding)
-				--m;
-			return m;
-		}
-
-		if (encoding < index[m].encoding)
-			right = m - 1;
-		else
-			left = m + 1;
-	}
-
-	// not found
-	return -1;
-}
-
-// binary search for encoding in IndexTypeStr array
-// return -1 if not found, or index if found
-unsigned int binsearch_IndexTypeStrEncoding(const struct IndexTypeStr *index, size_t size, const char *name)
-{
-	// binary searching since the index is sorted in encoding order
-	size_t left, right, m;
-
-	right = size - 1;
-
-	size_t str_left_cmp = strcmp(name, index[0].name);
-	size_t str_right_cmp = strcmp(name, index[right].name);
-	if (str_left_cmp < 0 || str_right_cmp > 0)
-		// not found
-		return -1;
-
-	left = 0;
-
-	while(left <= right) {
-		m = (left + right) / 2;
-		if (strcmp(name, index[m].name) == 0) {
-			// LLVM actually uses lower_bound for the index table search
-			// Here we need to check if a previous entry is of the same encoding
-			// and return the first one.
-			while (m > 0 && (strcmp(name, index[m - 1].name) == 0))
-				--m;
-			return m;
-		}
-
-		if (strcmp(name, index[m].name) < 0)
-			right = m - 1;
-		else
-			left = m + 1;
-	}
-
-	// not found
-	return -1;
-}

thirdparty/capstone/MCInstPrinter.h

@@ -1,84 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Rot127 <unisono@quyllur.org>, 2023 */
-
-#ifndef CS_MCINSTPRINTER_H
-#define CS_MCINSTPRINTER_H
-
-#include "MCInst.h"
-#include <assert.h>
-#include <capstone/platform.h>
-
-/// Returned by getMnemonic() of the AsmPrinters.
-typedef struct {
-	const char *first; // Mnemonic
-	uint64_t second;   // Bits
-} MnemonicBitsInfo;
-
-/// Map from opcode to pattern list by binary search.
-typedef struct {
-	uint32_t Opcode;
-	uint16_t PatternStart;
-	uint16_t NumPatterns;
-} PatternsForOpcode;
-
-/// Data for each alias pattern. Includes feature bits, string, number of
-/// operands, and a variadic list of conditions to check.
-typedef struct {
-	uint32_t AsmStrOffset;
-	uint32_t AliasCondStart;
-	uint8_t NumOperands;
-	uint8_t NumConds;
-} AliasPattern;
-
-typedef enum {
-	AliasPatternCond_K_Feature,	   // Match only if a feature is enabled.
-	AliasPatternCond_K_NegFeature, // Match only if a feature is disabled.
-	AliasPatternCond_K_OrFeature,  // Match only if one of a set of features is
-								   // enabled.
-	AliasPatternCond_K_OrNegFeature,  // Match only if one of a set of features
-									 // is disabled.
-	AliasPatternCond_K_EndOrFeatures, // Note end of list of K_Or(Neg)?Features.
-	AliasPatternCond_K_Ignore,		  // Match any operand.
-	AliasPatternCond_K_Reg,			  // Match a specific register.
-	AliasPatternCond_K_TiedReg,		  // Match another already matched register.
-	AliasPatternCond_K_Imm,			  // Match a specific immediate.
-	AliasPatternCond_K_RegClass,	  // Match registers in a class.
-	AliasPatternCond_K_Custom,		  // Call custom matcher by index.
-} AliasPatternCond_CondKind;
-
-typedef struct {
-	AliasPatternCond_CondKind Kind;
-	uint32_t Value;
-} AliasPatternCond;
-
-typedef bool (*ValidateMCOperandFunc)(const MCOperand *MCOp, unsigned PredicateIndex);
-
-/// Tablegenerated data structures needed to match alias patterns.
-typedef struct {
-	const PatternsForOpcode *OpToPatterns;
-	const AliasPattern *Patterns;
-	const AliasPatternCond *PatternConds;
-	const char *AsmStrings;
-	const ValidateMCOperandFunc ValidateMCOperand;
-} AliasMatchingData;
-
-const char *matchAliasPatterns(MCInst *MI, const AliasMatchingData *M);
-bool getUseMarkup(void);
-const char *markup(const char *s);
-
-struct IndexType {
-	uint16_t encoding;
-	unsigned index;
-};
-
-struct IndexTypeStr {
-	const char *name;
-	unsigned index;
-};
-
-// binary search for encoding in IndexType array
-// return -1 if not found, or index if found
-unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding);
-unsigned int binsearch_IndexTypeStrEncoding(const struct IndexTypeStr *index, size_t size, const char *name);
-
-#endif // CS_MCINSTPRINTER_H

thirdparty/capstone/MCInstrDesc.c

@@ -1,48 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#include "MCInstrDesc.h"
-
-/// isPredicate - Set if this is one of the operands that made up of
-/// the predicate operand that controls an isPredicable() instruction.
-bool MCOperandInfo_isPredicate(const MCOperandInfo *m)
-{
-	return m->Flags & (1 << MCOI_Predicate);
-}
-
-/// isOptionalDef - Set if this operand is a optional def.
-///
-bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m)
-{
-	return m->Flags & (1 << MCOI_OptionalDef);
-}
-
-/// Checks if operand is tied to another one.
-bool MCOperandInfo_isTiedToOp(const MCOperandInfo *m)
-{
-	if (m->Constraints & (1 << MCOI_TIED_TO))
-		return true;
-	return false;
-}
-
-/// Returns the value of the specified operand constraint if
-/// it is present. Returns -1 if it is not present.
-int MCOperandInfo_getOperandConstraint(const MCInstrDesc *InstrDesc,
-				       unsigned OpNum,
-				       MCOI_OperandConstraint Constraint)
-{
-	const MCOperandInfo OpInfo = InstrDesc->OpInfo[OpNum];
-	if (OpNum < InstrDesc->NumOperands &&
-	    (OpInfo.Constraints & (1 << Constraint))) {
-		unsigned ValuePos = 4 + Constraint * 4;
-		return (OpInfo.Constraints >> ValuePos) & 0xf;
-	}
-	return -1;
-}
-
-/// Returns the instruction description for the given MCInst opcode.
-/// Function should be called like:
-/// MCInstrDesc_get(MCInst_getOpcode(MI), ARCHInstDesc, ARR_SIZE(ARCHInstDesc));
-const MCInstrDesc *MCInstrDesc_get(unsigned opcode, const MCInstrDesc *table, unsigned tbl_size) {
-	return &table[tbl_size - 1 - opcode];
-}

thirdparty/capstone/MCInstrDesc.h

@@ -1,171 +0,0 @@
-//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the MCOperandInfo and MCInstrDesc classes, which
-// are used to describe target instructions and their operands.
-//
-//===----------------------------------------------------------------------===//
-
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#ifndef CS_LLVM_MC_MCINSTRDESC_H
-#define CS_LLVM_MC_MCINSTRDESC_H
-
-#include "MCRegisterInfo.h"
-#include "capstone/platform.h"
-
-//===----------------------------------------------------------------------===//
-// Machine Operand Flags and Description
-//===----------------------------------------------------------------------===//
-
-/// Operand constraints. These are encoded in 16 bits with one of the
-/// low-order 3 bits specifying that a constraint is present and the
-/// corresponding high-order hex digit specifying the constraint value.
-/// This allows for a maximum of 3 constraints.
-typedef enum {
-	MCOI_TIED_TO = 0,    // Operand tied to another operand.
-	MCOI_EARLY_CLOBBER   // Operand is an early clobber register operand
-} MCOI_OperandConstraint;
-
-// Define a macro to produce each constraint value.
-#define CONSTRAINT_MCOI_TIED_TO(op) \
-  ((1 << MCOI_TIED_TO) | ((op) << (4 + MCOI_TIED_TO * 4)))
-
-#define CONSTRAINT_MCOI_EARLY_CLOBBER \
-  (1 << MCOI_EARLY_CLOBBER)
-
-/// OperandFlags - These are flags set on operands, but should be considered
-/// private, all access should go through the MCOperandInfo accessors.
-/// See the accessors for a description of what these are.
-enum MCOI_OperandFlags {
-	MCOI_LookupPtrRegClass = 0,
-	MCOI_Predicate,
-	MCOI_OptionalDef
-};
-
-/// Operand Type - Operands are tagged with one of the values of this enum.
-enum MCOI_OperandType {
-	MCOI_OPERAND_UNKNOWN = 0,
-	MCOI_OPERAND_IMMEDIATE = 1,
-	MCOI_OPERAND_REGISTER = 2,
-	MCOI_OPERAND_MEMORY = 3,
-	MCOI_OPERAND_PCREL = 4,
-
-	MCOI_OPERAND_FIRST_GENERIC = 6,
-	MCOI_OPERAND_GENERIC_0 = 6,
-	MCOI_OPERAND_GENERIC_1 = 7,
-	MCOI_OPERAND_GENERIC_2 = 8,
-	MCOI_OPERAND_GENERIC_3 = 9,
-	MCOI_OPERAND_GENERIC_4 = 10,
-	MCOI_OPERAND_GENERIC_5 = 11,
-	MCOI_OPERAND_LAST_GENERIC = 11,
-
-	MCOI_OPERAND_FIRST_GENERIC_IMM = 12,
-	MCOI_OPERAND_GENERIC_IMM_0 = 12,
-	MCOI_OPERAND_LAST_GENERIC_IMM = 12,
-
-	MCOI_OPERAND_FIRST_TARGET = 13,
-};
-
-
-/// MCOperandInfo - This holds information about one operand of a machine
-/// instruction, indicating the register class for register operands, etc.
-///
-typedef struct MCOperandInfo {
-	/// This specifies the register class enumeration of the operand
-	/// if the operand is a register.  If isLookupPtrRegClass is set, then this is
-	/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
-	/// get a dynamic register class.
-	int16_t RegClass;
-
-	/// These are flags from the MCOI::OperandFlags enum.
-	uint8_t Flags;
-
-	/// Information about the type of the operand.
-	uint8_t OperandType;
-
-	/// The lower 3 bits are used to specify which constraints are set.
-	/// The higher 13 bits are used to specify the value of constraints (4 bits each).
-	uint16_t Constraints;
-	/// Currently no other information.
-} MCOperandInfo;
-
-
-//===----------------------------------------------------------------------===//
-// Machine Instruction Flags and Description
-//===----------------------------------------------------------------------===//
-
-/// MCInstrDesc flags - These should be considered private to the
-/// implementation of the MCInstrDesc class. Clients should use the predicate
-/// methods on MCInstrDesc, not use these directly. These all correspond to
-/// bitfields in the MCInstrDesc::Flags field.
-enum {
-	MCID_Variadic = 0,
-	MCID_HasOptionalDef,
-	MCID_Pseudo,
-	MCID_Return,
-	MCID_Call,
-	MCID_Barrier,
-	MCID_Terminator,
-	MCID_Branch,
-	MCID_IndirectBranch,
-	MCID_Compare,
-	MCID_MoveImm,
-	MCID_MoveReg,
-	MCID_Bitcast,
-	MCID_Select,
-	MCID_DelaySlot,
-	MCID_FoldableAsLoad,
-	MCID_MayLoad,
-	MCID_MayStore,
-	MCID_Predicable,
-	MCID_NotDuplicable,
-	MCID_UnmodeledSideEffects,
-	MCID_Commutable,
-	MCID_ConvertibleTo3Addr,
-	MCID_UsesCustomInserter,
-	MCID_HasPostISelHook,
-	MCID_Rematerializable,
-	MCID_CheapAsAMove,
-	MCID_ExtraSrcRegAllocReq,
-	MCID_ExtraDefRegAllocReq,
-	MCID_RegSequence,
-	MCID_ExtractSubreg,
-	MCID_InsertSubreg,
-	MCID_Convergent,
-	MCID_Add,
-	MCID_Trap,
-};
-
-/// MCInstrDesc - Describe properties that are true of each instruction in the
-/// target description file. This captures information about side effects,
-/// register use and many other things. There is one instance of this struct
-/// for each target instruction class, and the MachineInstr class points to
-/// this struct directly to describe itself.
-typedef struct MCInstrDesc {
-	unsigned char  NumOperands;   // Num of args (may be more if variable_ops)
-	const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
-} MCInstrDesc;
-
-bool MCOperandInfo_isPredicate(const MCOperandInfo *m);
-
-bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m);
-
-bool MCOperandInfo_isTiedToOp(const MCOperandInfo *m);
-
-int MCOperandInfo_getOperandConstraint(const MCInstrDesc *OpInfo,
-				       unsigned OpNum,
-				       MCOI_OperandConstraint Constraint);
-const MCInstrDesc *MCInstrDesc_get(unsigned opcode,
-                                   const MCInstrDesc *table,
-                                   unsigned tbl_size);
-
-
-#endif

thirdparty/capstone/MCRegisterInfo.c

@@ -1,151 +0,0 @@
-//=== MC/MCRegisterInfo.cpp - Target Register Description -------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements MCRegisterInfo functions.
-//
-//===----------------------------------------------------------------------===//
-
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#include "MCRegisterInfo.h"
-
-/// DiffListIterator - Base iterator class that can traverse the
-/// differentially encoded register and regunit lists in DiffLists.
-/// Don't use this class directly, use one of the specialized sub-classes
-/// defined below.
-typedef struct DiffListIterator {
-	uint16_t Val;
-	const MCPhysReg *List;
-} DiffListIterator;
-
-void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
-		const MCRegisterDesc *D, unsigned NR,
-		unsigned RA, unsigned PC,
-		const MCRegisterClass *C, unsigned NC,
-		uint16_t (*RURoots)[2], unsigned NRU,
-		const MCPhysReg *DL,
-		const char *Strings,
-		const uint16_t *SubIndices, unsigned NumIndices,
-		const uint16_t *RET)
-{
-	RI->Desc = D;
-	RI->NumRegs = NR;
-	RI->RAReg = RA;
-	RI->PCReg = PC;
-	RI->Classes = C;
-	RI->DiffLists = DL;
-	RI->RegStrings = Strings;
-	RI->NumClasses = NC;
-	RI->RegUnitRoots = RURoots;
-	RI->NumRegUnits = NRU;
-	RI->SubRegIndices = SubIndices;
-	RI->NumSubRegIndices = NumIndices;
-	RI->RegEncodingTable = RET;
-}
-
-static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, const MCPhysReg *DiffList)
-{
-	d->Val = InitVal;
-	d->List = DiffList;
-}
-
-static uint16_t DiffListIterator_getVal(DiffListIterator *d)
-{
-	return d->Val;
-}
-
-static bool DiffListIterator_next(DiffListIterator *d)
-{
-	MCPhysReg D;
-
-	if (d->List == 0)
-		return false;
-
-	D = *d->List;
-	d->List++;
-	d->Val += D;
-
-	if (!D)
-		d->List = 0;
-
-	return (D != 0);
-}
-
-static bool DiffListIterator_isValid(DiffListIterator *d)
-{
-	return (d->List != 0);
-}
-
-unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC)
-{
-	DiffListIterator iter;
-
-	if (Reg >= RI->NumRegs) {
-		return 0;
-	}
-
-	DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs);
-	DiffListIterator_next(&iter);
-
-	while(DiffListIterator_isValid(&iter)) {
-		uint16_t val = DiffListIterator_getVal(&iter);
-		if (MCRegisterClass_contains(RC, val) && Reg ==  MCRegisterInfo_getSubReg(RI, val, SubIdx))
-			return val;
-
-		DiffListIterator_next(&iter);
-	}
-
-	return 0;
-}
-
-unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx)
-{
-	DiffListIterator iter;
-	const uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
-
-	DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs);
-	DiffListIterator_next(&iter);
-
-	while(DiffListIterator_isValid(&iter)) {
-		if (*SRI == Idx)
-			return DiffListIterator_getVal(&iter);
-		DiffListIterator_next(&iter);
-		++SRI;
-	}
-
-	return 0;
-}
-
-const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i)
-{
-	//assert(i < getNumRegClasses() && "Register Class ID out of range");
-	if (i >= RI->NumClasses)
-		return 0;
-	return &(RI->Classes[i]);
-}
-
-bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg)
-{
-	unsigned InByte = 0;
-	unsigned Byte = 0;
-
-	// Make sure that MCRegisterInfo_getRegClass didn't return 0
-	// (for calls to GETREGCLASS_CONTAIN0)
-	if(!c)
-		return false;
-
-	InByte = Reg % 8;
-	Byte = Reg / 8;
-
-	if (Byte >= c->RegSetSize)
-		return false;
-
-	return (c->RegSet[Byte] & (1 << InByte)) != 0;
-}

thirdparty/capstone/MCRegisterInfo.h

@@ -1,116 +0,0 @@
-//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes an abstract interface used to get information about a
-// target machines register file.  This information is used for a variety of
-// purposed, especially register allocation.
-//
-//===----------------------------------------------------------------------===//
-
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#ifndef CS_LLVM_MC_MCREGISTERINFO_H
-#define CS_LLVM_MC_MCREGISTERINFO_H
-
-#include "capstone/platform.h"
-
-/// An unsigned integer type large enough to represent all physical registers,
-/// but not necessarily virtual registers.
-typedef int16_t MCPhysReg;
-typedef const MCPhysReg* iterator;
-
-typedef struct MCRegisterClass2 {
-	iterator RegsBegin;
-	const uint8_t *RegSet;
-	uint8_t RegsSize;
-	uint8_t RegSetSize;
-} MCRegisterClass2;
-
-typedef struct MCRegisterClass {
-	iterator RegsBegin;
-	const uint8_t *RegSet;
-	uint16_t RegSetSize;
-} MCRegisterClass;
-
-/// MCRegisterDesc - This record contains information about a particular
-/// register.  The SubRegs field is a zero terminated array of registers that
-/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
-/// of AX. The SuperRegs field is a zero terminated array of registers that are
-/// super-registers of AX.
-typedef struct MCRegisterDesc {
-	uint32_t Name;      // Printable name for the reg (for debugging)
-	uint32_t SubRegs;   // Sub-register set, described above
-	uint32_t SuperRegs; // Super-register set, described above
-
-	// Offset into MCRI::SubRegIndices of a list of sub-register indices for each
-	// sub-register in SubRegs.
-	uint32_t SubRegIndices;
-
-	// RegUnits - Points to the list of register units. The low 4 bits holds the
-	// Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
-	uint32_t RegUnits;
-
-	/// Index into list with lane mask sequences. The sequence contains a lanemask
-	/// for every register unit.
-	uint16_t RegUnitLaneMasks;	// ???
-} MCRegisterDesc;
-
-/// MCRegisterInfo base class - We assume that the target defines a static
-/// array of MCRegisterDesc objects that represent all of the machine
-/// registers that the target has.  As such, we simply have to track a pointer
-/// to this array so that we can turn register number into a register
-/// descriptor.
-///
-/// Note this class is designed to be a base class of TargetRegisterInfo, which
-/// is the interface used by codegen. However, specific targets *should never*
-/// specialize this class. MCRegisterInfo should only contain getters to access
-/// TableGen generated physical register data. It must not be extended with
-/// virtual methods.
-typedef struct MCRegisterInfo {
-	const MCRegisterDesc *Desc;                 // Pointer to the descriptor array
-	unsigned NumRegs;                           // Number of entries in the array
-	unsigned RAReg;                             // Return address register
-	unsigned PCReg;                             // Program counter register
-	const MCRegisterClass *Classes;             // Pointer to the regclass array
-	unsigned NumClasses;                        // Number of entries in the array
-	unsigned NumRegUnits;                       // Number of regunits.
-	uint16_t (*RegUnitRoots)[2];          // Pointer to regunit root table.
-	const MCPhysReg *DiffLists;                 // Pointer to the difflists array
-	// const LaneBitmask *RegUnitMaskSequences;    // Pointer to lane mask sequences
-	const char *RegStrings;                     // Pointer to the string table.
-	// const char *RegClassStrings;                // Pointer to the class strings.
-	const uint16_t *SubRegIndices;              // Pointer to the subreg lookup
-	// array.
-	unsigned NumSubRegIndices;                  // Number of subreg indices.
-	const uint16_t *RegEncodingTable;           // Pointer to array of register
-	// encodings.
-} MCRegisterInfo;
-
-void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
-		const MCRegisterDesc *D, unsigned NR, unsigned RA,
-		unsigned PC,
-		const MCRegisterClass *C, unsigned NC,
-		uint16_t (*RURoots)[2],
-		unsigned NRU,
-		const MCPhysReg *DL,
-		const char *Strings,
-		const uint16_t *SubIndices,
-		unsigned NumIndices,
-		const uint16_t *RET);
-
-unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC);
-
-unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
-
-const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i);
-
-bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg);
-
-#endif

thirdparty/capstone/Makefile

@@ -1,649 +0,0 @@
-# Capstone Disassembly Engine
-# By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014
-
-include config.mk
-include pkgconfig.mk	# package version
-include functions.mk
-
-# Verbose output?
-V ?= 0
-
-OS := $(shell uname)
-ifeq ($(OS),Darwin)
-LIBARCHS ?= x86_64 arm64
-PREFIX ?= /usr/local
-endif
-
-ifeq ($(PKG_EXTRA),)
-PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR)
-else
-PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA)
-endif
-
-ifeq ($(CROSS),)
-RANLIB ?= ranlib
-else ifeq ($(ANDROID), 1)
-CC = $(CROSS)/../../bin/clang
-AR = $(CROSS)/ar
-RANLIB = $(CROSS)/ranlib
-STRIP = $(CROSS)/strip
-else
-CC = $(CROSS)gcc
-AR = $(CROSS)ar
-RANLIB = $(CROSS)ranlib
-STRIP = $(CROSS)strip
-endif
-
-ifeq ($(OS),OS/390)
-RANLIB = touch
-endif
-
-ifneq (,$(findstring yes,$(CAPSTONE_DIET)))
-CFLAGS ?= -Os
-CFLAGS += -DCAPSTONE_DIET
-else
-CFLAGS ?= -O3
-endif
-
-# C99 has been enforced elsewhere like xcode
-CFLAGS += -std=gnu99
-
-ifneq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
-CFLAGS += -DCAPSTONE_X86_ATT_DISABLE
-endif
-
-ifeq ($(CC),xlc)
-CFLAGS += -qcpluscmt -qkeyword=inline -qlanglvl=extc1x -Iinclude
-ifneq ($(OS),OS/390)
-CFLAGS += -fPIC
-endif
-else
-CFLAGS += -fPIC -Wall -Wwrite-strings -Wmissing-prototypes -Iinclude
-endif
-
-ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
-CFLAGS += -DCAPSTONE_USE_SYS_DYN_MEM
-endif
-
-ifeq ($(CAPSTONE_HAS_OSXKERNEL), yes)
-CFLAGS += -DCAPSTONE_HAS_OSXKERNEL
-SDKROOT ?= $(shell xcodebuild -version -sdk macosx Path)
-CFLAGS += -mmacosx-version-min=10.5 \
-		  -isysroot$(SDKROOT) \
-		  -I$(SDKROOT)/System/Library/Frameworks/Kernel.framework/Headers \
-		  -mkernel \
-		  -fno-builtin
-endif
-
-PREFIX ?= /usr
-DESTDIR ?=
-ifndef BUILDDIR
-BLDIR = .
-OBJDIR = .
-else
-BLDIR = $(abspath $(BUILDDIR))
-OBJDIR = $(BLDIR)/obj
-endif
-INCDIR ?= $(PREFIX)/include
-
-UNAME_S := $(shell uname -s)
-
-LIBDIRARCH ?= lib
-# Uncomment the below line to installs x86_64 libs to lib64/ directory.
-# Or better, pass 'LIBDIRARCH=lib64' to 'make install/uninstall' via 'make.sh'.
-#LIBDIRARCH ?= lib64
-LIBDIR = $(DESTDIR)$(PREFIX)/$(LIBDIRARCH)
-BINDIR = $(DESTDIR)$(PREFIX)/bin
-
-LIBDATADIR = $(LIBDIR)
-
-# Don't redefine $LIBDATADIR when global environment variable
-# USE_GENERIC_LIBDATADIR is set. This is used by the pkgsrc framework.
-
-ifndef USE_GENERIC_LIBDATADIR
-ifeq ($(UNAME_S), FreeBSD)
-LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata
-endif
-ifeq ($(UNAME_S), DragonFly)
-LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata
-endif
-endif
-
-INSTALL_BIN ?= install
-INSTALL_DATA ?= $(INSTALL_BIN) -m0644
-INSTALL_LIB ?= $(INSTALL_BIN) -m0755
-
-LIBNAME = capstone
-
-
-DEP_ARM =
-DEP_ARM += $(wildcard arch/ARM/ARM*.inc)
-
-LIBOBJ_ARM =
-ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_ARM
-	LIBSRC_ARM += $(wildcard arch/ARM/ARM*.c)
-	LIBOBJ_ARM += $(LIBSRC_ARM:%.c=$(OBJDIR)/%.o)
-endif
-
-DEP_AARCH64 =
-DEP_AARCH64 += $(wildcard arch/AArch64/AArch64*.inc)
-
-LIBOBJ_AARCH64 =
-ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_ARM64
-	CFLAGS += -DCAPSTONE_HAS_AARCH64
-	LIBSRC_AARCH64 += $(wildcard arch/AArch64/AArch64*.c)
-	LIBOBJ_AARCH64 += $(LIBSRC_AARCH64:%.c=$(OBJDIR)/%.o)
-endif
-
-
-DEP_M68K =
-DEP_M68K += $(wildcard arch/M68K/M68K*.inc)
-DEP_M68K += $(wildcard arch/M68K/M68K*.h)
-
-LIBOBJ_M68K =
-ifneq (,$(findstring m68k,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_M68K
-	LIBSRC_M68K += $(wildcard arch/M68K/M68K*.c)
-	LIBOBJ_M68K += $(LIBSRC_M68K:%.c=$(OBJDIR)/%.o)
-endif
-
-DEP_MIPS =
-DEP_MIPS += $(wildcard arch/Mips/Mips*.inc)
-
-LIBOBJ_MIPS =
-ifneq (,$(findstring mips,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_MIPS
-	LIBSRC_MIPS += $(wildcard arch/Mips/Mips*.c)
-	LIBOBJ_MIPS += $(LIBSRC_MIPS:%.c=$(OBJDIR)/%.o)
-endif
-
-DEP_SH = $(wildcard arch/SH/SH*.inc)
-
-LIBOBJ_SH =
-ifneq (,$(findstring sh,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_SH
-	LIBSRC_SH += $(wildcard arch/SH/SH*.c)
-	LIBOBJ_SH += $(LIBSRC_SH:%.c=$(OBJDIR)/%.o)
-endif
-
-DEP_PPC =
-DEP_PPC += $(wildcard arch/PowerPC/PPC*.inc)
-
-LIBOBJ_PPC =
-ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_POWERPC
-	LIBSRC_PPC += $(wildcard arch/PowerPC/PPC*.c)
-	LIBOBJ_PPC += $(LIBSRC_PPC:%.c=$(OBJDIR)/%.o)
-endif
-
-
-DEP_SPARC =
-DEP_SPARC += $(wildcard arch/Sparc/Sparc*.inc)
-
-LIBOBJ_SPARC =
-ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_SPARC
-	LIBSRC_SPARC += $(wildcard arch/Sparc/Sparc*.c)
-	LIBOBJ_SPARC += $(LIBSRC_SPARC:%.c=$(OBJDIR)/%.o)
-endif
-
-
-DEP_SYSZ =
-DEP_SYSZ += $(wildcard arch/SystemZ/SystemZ*.inc)
-
-LIBOBJ_SYSZ =
-ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_SYSZ
-	LIBSRC_SYSZ += $(wildcard arch/SystemZ/SystemZ*.c)
-	LIBOBJ_SYSZ += $(LIBSRC_SYSZ:%.c=$(OBJDIR)/%.o)
-endif
-
-
-# by default, we compile full X86 instruction sets
-X86_REDUCE =
-ifneq (,$(findstring yes,$(CAPSTONE_X86_REDUCE)))
-X86_REDUCE = _reduce
-CFLAGS += -DCAPSTONE_X86_REDUCE -Os
-endif
-
-
-DEP_X86 =
-DEP_X86 += $(wildcard arch/X86/X86*.inc)
-
-LIBOBJ_X86 =
-ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_X86
-	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86DisassemblerDecoder.o
-	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Disassembler.o
-	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86InstPrinterCommon.o
-	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o
-# assembly syntax is irrelevant in Diet mode, when this info is suppressed
-ifeq (,$(findstring yes,$(CAPSTONE_DIET)))
-ifeq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
-	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86ATTInstPrinter.o
-endif
-endif
-	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Mapping.o
-	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o
-endif
-
-
-DEP_XCORE =
-DEP_XCORE += $(wildcard arch/XCore/XCore*.inc)
-
-LIBOBJ_XCORE =
-ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_XCORE
-	LIBSRC_XCORE += $(wildcard arch/XCore/XCore*.c)
-	LIBOBJ_XCORE += $(LIBSRC_XCORE:%.c=$(OBJDIR)/%.o)
-endif
-
-
-DEP_TMS320C64X =
-DEP_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.inc)
-
-LIBOBJ_TMS320C64X =
-ifneq (,$(findstring tms320c64x,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_TMS320C64X
-	LIBSRC_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.c)
-	LIBOBJ_TMS320C64X += $(LIBSRC_TMS320C64X:%.c=$(OBJDIR)/%.o)
-endif
-
-DEP_M680X =
-DEP_M680X += $(wildcard arch/M680X/*.inc)
-DEP_M680X += $(wildcard arch/M680X/M680X*.h)
-
-LIBOBJ_M680X =
-ifneq (,$(findstring m680x,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_M680X
-	LIBSRC_M680X += $(wildcard arch/M680X/*.c)
-	LIBOBJ_M680X += $(LIBSRC_M680X:%.c=$(OBJDIR)/%.o)
-endif
-
-
-DEP_EVM =
-DEP_EVM += $(wildcard arch/EVM/EVM*.inc)
-
-LIBOBJ_EVM =
-ifneq (,$(findstring evm,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_EVM
-	LIBSRC_EVM += $(wildcard arch/EVM/EVM*.c)
-	LIBOBJ_EVM += $(LIBSRC_EVM:%.c=$(OBJDIR)/%.o)
-endif
-
-DEP_RISCV =
-DEP_RISCV += $(wildcard arch/RISCV/RISCV*.inc)
-
-LIBOBJ_RISCV =
-ifneq (,$(findstring riscv,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_RISCV
-	LIBSRC_RISCV += $(wildcard arch/RISCV/RISCV*.c)
-	LIBOBJ_RISCV += $(LIBSRC_RISCV:%.c=$(OBJDIR)/%.o)
-endif
-
-DEP_WASM =
-DEP_WASM += $(wildcard arch/WASM/WASM*.inc)
-
-LIBOBJ_WASM =
-ifneq (,$(findstring wasm,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_WASM
-	LIBSRC_WASM += $(wildcard arch/WASM/WASM*.c)
-	LIBOBJ_WASM += $(LIBSRC_WASM:%.c=$(OBJDIR)/%.o)
-endif
-
-
-DEP_MOS65XX =
-DEP_MOS65XX += $(wildcard arch/MOS65XX/MOS65XX*.inc)
-
-LIBOBJ_MOS65XX =
-ifneq (,$(findstring mos65xx,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_MOS65XX
-	LIBSRC_MOS65XX += $(wildcard arch/MOS65XX/MOS65XX*.c)
-	LIBOBJ_MOS65XX += $(LIBSRC_MOS65XX:%.c=$(OBJDIR)/%.o)
-endif
-
-
-DEP_BPF =
-DEP_BPF += $(wildcard arch/BPF/BPF*.inc)
-
-LIBOBJ_BPF =
-ifneq (,$(findstring bpf,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_BPF
-	LIBSRC_BPF += $(wildcard arch/BPF/BPF*.c)
-	LIBOBJ_BPF += $(LIBSRC_BPF:%.c=$(OBJDIR)/%.o)
-endif
-
-DEP_TRICORE =
-DEP_TRICORE +=$(wildcard arch/TriCore/TriCore*.inc)
-
-LIBOBJ_TRICORE =
-ifneq (,$(findstring tricore,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_TRICORE
-	LIBSRC_TRICORE += $(wildcard arch/TriCore/TriCore*.c)
-	LIBOBJ_TRICORE += $(LIBSRC_TRICORE:%.c=$(OBJDIR)/%.o)
-endif
-
-DEP_ALPHA =
-DEP_ALPHA +=$(wildcard arch/Alpha/Alpha*.inc)
-
-LIBOBJ_ALPHA =
-ifneq (,$(findstring alpha,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_ALPHA
-	LIBSRC_ALPHA += $(wildcard arch/Alpha/Alpha*.c)
-	LIBOBJ_ALPHA += $(LIBSRC_ALPHA:%.c=$(OBJDIR)/%.o)
-endif
-
-DEP_HPPA =
-DEP_HPPA += $(wildcard arch/HPPA/HPPA*.inc)
-
-LIBOBJ_HPPA =
-ifneq (,$(findstring hppa,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_HPPA
-	LIBSRC_HPPA += $(wildcard arch/HPPA/HPPA*.c)
-	LIBOBJ_HPPA += $(LIBSRC_HPPA:%.c=$(OBJDIR)/%.o)
-endif
-
-DEP_LOONGARCH =
-DEP_LOONGARCH += $(wildcard arch/LoongArch/LoongArch*.inc)
-
-LIBOBJ_LOONGARCH =
-ifneq (,$(findstring loongarch,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_LOONGARCH
-	LIBSRC_LOONGARCH += $(wildcard arch/LoongArch/LoongArch*.c)
-	LIBOBJ_LOONGARCH += $(LIBSRC_LOONGARCH:%.c=$(OBJDIR)/%.o)
-endif
-
-LIBOBJ =
-LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/Mapping.o
-LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_AARCH64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
-LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF)
-LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) $(LIBOBJ_HPPA) $(LIBOBJ_LOONGARCH)
-
-
-ifeq ($(PKG_EXTRA),)
-PKGCFGDIR = $(LIBDATADIR)/pkgconfig
-else
-PKGCFGDIR ?= $(LIBDATADIR)/pkgconfig
-ifeq ($(PKGCFGDIR),)
-PKGCFGDIR = $(LIBDATADIR)/pkgconfig
-endif
-endif
-
-API_MAJOR=$(shell echo `grep -e CS_API_MAJOR include/capstone/capstone.h | grep -v = | awk '{print $$3}'` | awk '{print $$1}')
-VERSION_EXT =
-
-IS_APPLE := $(shell $(CC) -dM -E - < /dev/null 2> /dev/null | grep __APPLE__ | wc -l | tr -d " ")
-ifeq ($(IS_APPLE),1)
-# on MacOS, do not build in Universal format by default
-MACOS_UNIVERSAL ?= no
-ifeq ($(MACOS_UNIVERSAL),yes)
-CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
-LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
-endif
-EXT = dylib
-VERSION_EXT = $(API_MAJOR).$(EXT)
-$(LIBNAME)_LDFLAGS += -dynamiclib -install_name lib$(LIBNAME).$(VERSION_EXT) -current_version $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) -compatibility_version $(PKG_MAJOR).$(PKG_MINOR)
-AR_EXT = a
-# Homebrew wants to make sure its formula does not disable FORTIFY_SOURCE
-# However, this is not really necessary because 'CAPSTONE_USE_SYS_DYN_MEM=yes' by default
-ifneq ($(HOMEBREW_CAPSTONE),1)
-ifneq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
-# remove string check because OSX kernel complains about missing symbols
-CFLAGS += -D_FORTIFY_SOURCE=0
-endif
-endif
-else
-CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
-LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
-ifeq ($(OS), AIX)
-$(LIBNAME)_LDFLAGS += -qmkshrobj
-else
-$(LIBNAME)_LDFLAGS += -shared
-endif
-# Cygwin?
-IS_CYGWIN := $(shell $(CC) -dumpmachine 2>/dev/null | grep -i cygwin | wc -l)
-ifeq ($(IS_CYGWIN),1)
-EXT = dll
-AR_EXT = lib
-# Cygwin doesn't like -fPIC
-CFLAGS := $(CFLAGS:-fPIC=)
-# On Windows we need the shared library to be executable
-else
-# mingw?
-IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i "\(mingw\|MSYS\)" | wc -l)
-ifeq ($(IS_MINGW),1)
-EXT = dll
-AR_EXT = lib
-# mingw doesn't like -fPIC either
-CFLAGS := $(CFLAGS:-fPIC=)
-# On Windows we need the shared library to be executable
-else
-# Linux, *BSD
-EXT = so
-VERSION_EXT = $(EXT).$(API_MAJOR)
-AR_EXT = a
-$(LIBNAME)_LDFLAGS += -Wl,-soname,lib$(LIBNAME).$(VERSION_EXT)
-endif
-endif
-endif
-
-ifeq ($(CAPSTONE_SHARED),yes)
-ifeq ($(IS_MINGW),1)
-LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT)
-else ifeq ($(IS_CYGWIN),1)
-LIBRARY = $(BLDIR)/$(LIBNAME).$(EXT)
-else	# *nix
-LIBRARY = $(BLDIR)/lib$(LIBNAME).$(VERSION_EXT)
-CFLAGS += -fvisibility=hidden
-endif
-endif
-
-ifeq ($(CAPSTONE_STATIC),yes)
-ifeq ($(IS_MINGW),1)
-ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT)
-else ifeq ($(IS_CYGWIN),1)
-ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT)
-else
-ARCHIVE = $(BLDIR)/lib$(LIBNAME).$(AR_EXT)
-endif
-endif
-
-PKGCFGF = $(BLDIR)/$(LIBNAME).pc
-
-.PHONY: all clean install uninstall dist
-
-all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF)
-ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
-	@V=$(V) CC=$(CC) $(MAKE) -C cstool
-endif
-
-ifeq ($(CAPSTONE_SHARED),yes)
-$(LIBRARY): $(LIBOBJ)
-ifeq ($(V),0)
-	$(call log,LINK,$(@:$(BLDIR)/%=%))
-	@$(create-library)
-else
-	$(create-library)
-endif
-endif
-
-$(LIBOBJ): config.mk
-
-$(LIBOBJ_ARM): $(DEP_ARM)
-$(LIBOBJ_AARCH64): $(DEP_AARCH64)
-$(LIBOBJ_M68K): $(DEP_M68K)
-$(LIBOBJ_MIPS): $(DEP_MIPS)
-$(LIBOBJ_PPC): $(DEP_PPC)
-$(LIBOBJ_SH): $(DEP_SH)
-$(LIBOBJ_SPARC): $(DEP_SPARC)
-$(LIBOBJ_SYSZ): $(DEP_SYSZ)
-$(LIBOBJ_X86): $(DEP_X86)
-$(LIBOBJ_XCORE): $(DEP_XCORE)
-$(LIBOBJ_TMS320C64X): $(DEP_TMS320C64X)
-$(LIBOBJ_M680X): $(DEP_M680X)
-$(LIBOBJ_EVM): $(DEP_EVM)
-$(LIBOBJ_RISCV): $(DEP_RISCV)
-$(LIBOBJ_WASM): $(DEP_WASM)
-$(LIBOBJ_MOS65XX): $(DEP_MOS65XX)
-$(LIBOBJ_BPF): $(DEP_BPF)
-$(LIBOBJ_TRICORE): $(DEP_TRICORE)
-$(LIBOBJ_ALPHA): $(DEP_ALPHA)
-$(LIBOBJ_HPPA): $(DEP_HPPA)
-$(LIBOBJ_LOONGARCH): $(DEP_LOONGARCH)
-
-ifeq ($(CAPSTONE_STATIC),yes)
-$(ARCHIVE): $(LIBOBJ)
-	@rm -f $(ARCHIVE)
-ifeq ($(V),0)
-	$(call log,AR,$(@:$(BLDIR)/%=%))
-	@$(create-archive)
-else
-	$(create-archive)
-endif
-endif
-
-$(PKGCFGF):
-ifeq ($(V),0)
-	$(call log,GEN,$(@:$(BLDIR)/%=%))
-	@$(generate-pkgcfg)
-else
-	$(generate-pkgcfg)
-endif
-
-# create a list of auto dependencies
-AUTODEPS:= $(patsubst %.o,%.d, $(LIBOBJ))
-
-# include by auto dependencies
--include $(AUTODEPS)
-
-install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY)
-	mkdir -p $(LIBDIR)
-	$(call install-library,$(LIBDIR))
-ifeq ($(CAPSTONE_STATIC),yes)
-	$(INSTALL_DATA) $(ARCHIVE) $(LIBDIR)
-endif
-	mkdir -p $(DESTDIR)$(INCDIR)/$(LIBNAME)
-	$(INSTALL_DATA) include/capstone/*.h $(DESTDIR)$(INCDIR)/$(LIBNAME)
-	mkdir -p $(PKGCFGDIR)
-	$(INSTALL_DATA) $(PKGCFGF) $(PKGCFGDIR)
-ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
-	mkdir -p $(BINDIR)
-	$(INSTALL_LIB) cstool/cstool $(BINDIR)
-endif
-
-uninstall:
-	rm -rf $(DESTDIR)$(INCDIR)/$(LIBNAME)
-	rm -f $(LIBDIR)/lib$(LIBNAME).*
-	rm -f $(PKGCFGDIR)/$(LIBNAME).pc
-ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
-	rm -f $(BINDIR)/cstool
-endif
-
-clean:
-	rm -f $(LIBOBJ)
-	rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).pc
-	rm -f $(PKGCFGF)
-	rm -f $(AUTODEPS)
-	[ "${ANDROID}" = "1" ] && rm -rf android-ndk-* || true
-
-ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
-	$(MAKE) -C cstool clean
-	$(MAKE) -C suite/fuzz clean
-endif
-
-ifdef BUILDDIR
-	rm -rf $(BUILDDIR)
-endif
-
-ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
-	$(MAKE) -C bindings/python clean
-	$(MAKE) -C bindings/java clean
-	$(MAKE) -C bindings/ocaml clean
-endif
-
-
-TAG ?= HEAD
-ifeq ($(TAG), HEAD)
-DIST_VERSION = latest
-else
-DIST_VERSION = $(TAG)
-endif
-
-dist:
-	git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz
-	git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
-
-checkfuzz: fuzztest fuzzallcorp
-
-FUZZ_INPUTS = $(shell find suite/MC -type f -name '*.cs')
-
-buildfuzz:
-ifndef BUILDDIR
-	$(MAKE) -C suite/fuzz
-else
-	$(MAKE) -C suite/fuzz BUILDDIR=$(BLDIR)
-endif
-
-fuzztest:
-	./suite/fuzz/fuzz_disasm $(FUZZ_INPUTS)
-
-fuzzallcorp:
-ifneq ($(wildcard suite/fuzz/corpus-libFuzzer-capstone_fuzz_disasmnext-latest),)
-	./suite/fuzz/fuzz_bindisasm suite/fuzz/corpus-libFuzzer-capstone_fuzz_disasmnext-latest/ > fuzz_bindisasm.log || (tail -1 fuzz_bindisasm.log; false)
-else
-	@echo "Skipping tests on whole corpus"
-endif
-
-$(OBJDIR)/%.o: %.c
-	@mkdir -p $(@D)
-ifeq ($(V),0)
-	$(call log,CC,$(@:$(OBJDIR)/%=%))
-	@$(compile)
-else
-	$(compile)
-endif
-
-
-ifeq ($(CAPSTONE_SHARED),yes)
-define install-library
-	$(INSTALL_LIB) $(LIBRARY) $1
-	$(if $(VERSION_EXT),
-		cd $1 && \
-		rm -f lib$(LIBNAME).$(EXT) && \
-		ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT))
-endef
-else
-define install-library
-endef
-endif
-
-ifeq ($(AR_FLAGS),)
-AR_FLAGS := q
-endif
-
-define create-archive
-	$(AR) $(AR_FLAGS) $(ARCHIVE) $(LIBOBJ)
-	$(RANLIB) $(ARCHIVE)
-endef
-
-
-define create-library
-	$(CC) $(LDFLAGS) $($(LIBNAME)_LDFLAGS) $(LIBOBJ) -o $(LIBRARY)
-endef
-
-
-define generate-pkgcfg
-	mkdir -p $(BLDIR)
-	echo 'Name: capstone' > $(PKGCFGF)
-	echo 'Description: Capstone disassembly engine' >> $(PKGCFGF)
-	echo 'Version: $(PKG_VERSION)' >> $(PKGCFGF)
-	echo 'libdir=$(LIBDIR)' >> $(PKGCFGF)
-	echo 'includedir=$(INCDIR)/capstone' >> $(PKGCFGF)
-	echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF)
-	echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF)
-	echo 'Libs.private: -L$${libdir} -l:libcapstone.a' >> $(PKGCFGF)
-	echo 'Cflags: -I$${includedir}' >> $(PKGCFGF)
-	echo 'archs=${CAPSTONE_ARCHS}' >> $(PKGCFGF)
-endef

thirdparty/capstone/Mapping.c

@@ -1,443 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
-
-#include "Mapping.h"
-#include "capstone/capstone.h"
-#include "utils.h"
-
-// create a cache for fast id lookup
-static unsigned short *make_id2insn(const insn_map *insns, unsigned int size)
-{
-	// NOTE: assume that the max id is always put at the end of insns array
-	unsigned short max_id = insns[size - 1].id;
-	unsigned int i;
-
-	unsigned short *cache =
-		(unsigned short *)cs_mem_calloc(max_id + 1, sizeof(*cache));
-
-	for (i = 1; i < size; i++)
-		cache[insns[i].id] = i;
-
-	return cache;
-}
-
-// look for @id in @insns, given its size in @max. first time call will update
-// @cache. return 0 if not found
-unsigned short insn_find(const insn_map *insns, unsigned int max,
-			 unsigned int id, unsigned short **cache)
-{
-	if (id > insns[max - 1].id)
-		return 0;
-
-	if (*cache == NULL)
-		*cache = make_id2insn(insns, max);
-
-	return (*cache)[id];
-}
-
-// Gives the id for the given @name if it is saved in @map.
-// Returns the id or -1 if not found.
-int name2id(const name_map *map, int max, const char *name)
-{
-	int i;
-
-	for (i = 0; i < max; i++) {
-		if (!strcmp(map[i].name, name)) {
-			return map[i].id;
-		}
-	}
-
-	// nothing match
-	return -1;
-}
-
-// Gives the name for the given @id if it is saved in @map.
-// Returns the name or NULL if not found.
-const char *id2name(const name_map *map, int max, const unsigned int id)
-{
-	int i;
-
-	for (i = 0; i < max; i++) {
-		if (map[i].id == id) {
-			return map[i].name;
-		}
-	}
-
-	// nothing match
-	return NULL;
-}
-
-/// Adds a register to the implicit write register list.
-/// It will not add the same register twice.
-void map_add_implicit_write(MCInst *MI, uint32_t Reg)
-{
-	if (!MI->flat_insn->detail)
-		return;
-
-	uint16_t *regs_write = MI->flat_insn->detail->regs_write;
-	for (int i = 0; i < MAX_IMPL_W_REGS; ++i) {
-		if (i == MI->flat_insn->detail->regs_write_count) {
-			regs_write[i] = Reg;
-			MI->flat_insn->detail->regs_write_count++;
-			return;
-		}
-		if (regs_write[i] == Reg)
-			return;
-	}
-}
-
-/// Adds a register to the implicit read register list.
-/// It will not add the same register twice.
-void map_add_implicit_read(MCInst *MI, uint32_t Reg)
-{
-	if (!MI->flat_insn->detail)
-		return;
-
-	uint16_t *regs_read = MI->flat_insn->detail->regs_read;
-	for (int i = 0; i < MAX_IMPL_R_REGS; ++i) {
-		if (i == MI->flat_insn->detail->regs_read_count) {
-			regs_read[i] = Reg;
-			MI->flat_insn->detail->regs_read_count++;
-			return;
-		}
-		if (regs_read[i] == Reg)
-			return;
-	}
-}
-
-/// Removes a register from the implicit write register list.
-void map_remove_implicit_write(MCInst *MI, uint32_t Reg)
-{
-	if (!MI->flat_insn->detail)
-		return;
-
-	uint16_t *regs_write = MI->flat_insn->detail->regs_write;
-	bool shorten_list = false;
-	for (int i = 0; i < MAX_IMPL_W_REGS; ++i) {
-		if (shorten_list) {
-			regs_write[i - 1] = regs_write[i];
-		}
-		if (i >= MI->flat_insn->detail->regs_write_count)
-			return;
-
-		if (regs_write[i] == Reg) {
-			MI->flat_insn->detail->regs_write_count--;
-			// The register should exist only once in the list.
-			assert(!shorten_list);
-			shorten_list = true;
-		}
-	}
-}
-
-/// Copies the implicit read registers of @imap to @MI->flat_insn.
-/// Already present registers will be preserved.
-void map_implicit_reads(MCInst *MI, const insn_map *imap)
-{
-#ifndef CAPSTONE_DIET
-	if (!MI->flat_insn->detail)
-		return;
-
-	cs_detail *detail = MI->flat_insn->detail;
-	unsigned Opcode = MCInst_getOpcode(MI);
-	unsigned i = 0;
-	uint16_t reg = imap[Opcode].regs_use[i];
-	while (reg != 0) {
-		if (i >= MAX_IMPL_R_REGS ||
-		    detail->regs_read_count >= MAX_IMPL_R_REGS) {
-			printf("ERROR: Too many implicit read register defined in "
-			       "instruction mapping.\n");
-			return;
-		}
-		detail->regs_read[detail->regs_read_count++] = reg;
-		reg = imap[Opcode].regs_use[++i];
-	}
-#endif // CAPSTONE_DIET
-}
-
-/// Copies the implicit write registers of @imap to @MI->flat_insn.
-/// Already present registers will be preserved.
-void map_implicit_writes(MCInst *MI, const insn_map *imap)
-{
-#ifndef CAPSTONE_DIET
-	if (!MI->flat_insn->detail)
-		return;
-
-	cs_detail *detail = MI->flat_insn->detail;
-	unsigned Opcode = MCInst_getOpcode(MI);
-	unsigned i = 0;
-	uint16_t reg = imap[Opcode].regs_mod[i];
-	while (reg != 0) {
-		if (i >= MAX_IMPL_W_REGS ||
-		    detail->regs_write_count >= MAX_IMPL_W_REGS) {
-			printf("ERROR: Too many implicit write register defined in "
-			       "instruction mapping.\n");
-			return;
-		}
-		detail->regs_write[detail->regs_write_count++] = reg;
-		reg = imap[Opcode].regs_mod[++i];
-	}
-#endif // CAPSTONE_DIET
-}
-
-/// Adds a given group to @MI->flat_insn.
-/// A group is never added twice.
-void add_group(MCInst *MI, unsigned /* arch_group */ group)
-{
-#ifndef CAPSTONE_DIET
-	if (!MI->flat_insn->detail)
-		return;
-
-	cs_detail *detail = MI->flat_insn->detail;
-	if (detail->groups_count >= MAX_NUM_GROUPS) {
-		printf("ERROR: Too many groups defined.\n");
-		return;
-	}
-	for (int i = 0; i < detail->groups_count; ++i) {
-		if (detail->groups[i] == group) {
-			return;
-		}
-	}
-	detail->groups[detail->groups_count++] = group;
-#endif // CAPSTONE_DIET
-}
-
-/// Copies the groups from @imap to @MI->flat_insn.
-/// Already present groups will be preserved.
-void map_groups(MCInst *MI, const insn_map *imap)
-{
-#ifndef CAPSTONE_DIET
-	if (!MI->flat_insn->detail)
-		return;
-
-	cs_detail *detail = MI->flat_insn->detail;
-	unsigned Opcode = MCInst_getOpcode(MI);
-	unsigned i = 0;
-	uint16_t group = imap[Opcode].groups[i];
-	while (group != 0) {
-		if (detail->groups_count >= MAX_NUM_GROUPS) {
-			printf("ERROR: Too many groups defined in instruction mapping.\n");
-			return;
-		}
-		detail->groups[detail->groups_count++] = group;
-		group = imap[Opcode].groups[++i];
-	}
-#endif // CAPSTONE_DIET
-}
-
-/// Returns the pointer to the supllementary information in
-/// the instruction mapping table @imap or NULL in case of failure.
-const void *map_get_suppl_info(MCInst *MI, const insn_map *imap)
-{
-#ifndef CAPSTONE_DIET
-	if (!MI->flat_insn->detail)
-		return NULL;
-
-	unsigned Opcode = MCInst_getOpcode(MI);
-	return &imap[Opcode].suppl_info;
-#else
-	return NULL;
-#endif // CAPSTONE_DIET
-}
-
-// Search for the CS instruction id for the given @MC_Opcode in @imap.
-// return -1 if none is found.
-unsigned int find_cs_id(unsigned MC_Opcode, const insn_map *imap,
-			unsigned imap_size)
-{
-	// binary searching since the IDs are sorted in order
-	unsigned int left, right, m;
-	unsigned int max = imap_size;
-
-	right = max - 1;
-
-	if (MC_Opcode < imap[0].id || MC_Opcode > imap[right].id)
-		// not found
-		return -1;
-
-	left = 0;
-
-	while (left <= right) {
-		m = (left + right) / 2;
-		if (MC_Opcode == imap[m].id) {
-			return m;
-		}
-
-		if (MC_Opcode < imap[m].id)
-			right = m - 1;
-		else
-			left = m + 1;
-	}
-
-	return -1;
-}
-
-/// Sets the Capstone instruction id which maps to the @MI opcode.
-/// If no mapping is found the function returns and prints an error.
-void map_cs_id(MCInst *MI, const insn_map *imap, unsigned int imap_size)
-{
-	unsigned int i = find_cs_id(MCInst_getOpcode(MI), imap, imap_size);
-	if (i != -1) {
-		MI->flat_insn->id = imap[i].mapid;
-		return;
-	}
-	printf("ERROR: Could not find CS id for MCInst opcode: %d\n",
-	       MCInst_getOpcode(MI));
-	return;
-}
-
-/// Returns the operand type information from the
-/// mapping table for instruction operands.
-/// Only usable by `auto-sync` archs!
-const cs_op_type mapping_get_op_type(MCInst *MI, unsigned OpNum,
-				     const map_insn_ops *insn_ops_map,
-				     size_t map_size)
-{
-	assert(MI);
-	assert(MI->Opcode < map_size);
-	assert(OpNum < sizeof(insn_ops_map[MI->Opcode].ops) /
-			       sizeof(insn_ops_map[MI->Opcode].ops[0]));
-
-	return insn_ops_map[MI->Opcode].ops[OpNum].type;
-}
-
-/// Returns the operand access flags from the
-/// mapping table for instruction operands.
-/// Only usable by `auto-sync` archs!
-const cs_ac_type mapping_get_op_access(MCInst *MI, unsigned OpNum,
-				       const map_insn_ops *insn_ops_map,
-				       size_t map_size)
-{
-	assert(MI);
-	assert(MI->Opcode < map_size);
-	assert(OpNum < sizeof(insn_ops_map[MI->Opcode].ops) /
-			       sizeof(insn_ops_map[MI->Opcode].ops[0]));
-
-	cs_ac_type access = insn_ops_map[MI->Opcode].ops[OpNum].access;
-	if (MCInst_opIsTied(MI, OpNum) || MCInst_opIsTying(MI, OpNum))
-		access |= (access == CS_AC_READ) ? CS_AC_WRITE : CS_AC_READ;
-	return access;
-}
-
-/// Returns the operand at detail->arch.operands[op_count + offset]
-/// Or NULL if detail is not set.
-#define DEFINE_get_detail_op(arch, ARCH) \
-	cs_##arch##_op *ARCH##_get_detail_op(MCInst *MI, int offset) \
-	{ \
-		if (!MI->flat_insn->detail) \
-			return NULL; \
-		int OpIdx = MI->flat_insn->detail->arch.op_count + offset; \
-		assert(OpIdx >= 0 && OpIdx < MAX_MC_OPS); \
-		return &MI->flat_insn->detail->arch.operands[OpIdx]; \
-	}
-
-DEFINE_get_detail_op(arm, ARM);
-DEFINE_get_detail_op(ppc, PPC);
-DEFINE_get_detail_op(tricore, TriCore);
-DEFINE_get_detail_op(aarch64, AArch64);
-DEFINE_get_detail_op(alpha, Alpha);
-DEFINE_get_detail_op(hppa, HPPA);
-DEFINE_get_detail_op(loongarch, LoongArch);
-DEFINE_get_detail_op(riscv, RISCV);
-
-/// Returns true if for this architecture the
-/// alias operands should be filled.
-/// TODO: Replace this with a proper option.
-/// 			So it can be toggled between disas() calls.
-bool map_use_alias_details(const MCInst *MI) {
-	assert(MI);
-	return !(MI->csh->detail_opt & CS_OPT_DETAIL_REAL);
-}
-
-/// Sets the setDetailOps flag to @p Val.
-/// If detail == NULLit refuses to set the flag to true.
-void map_set_fill_detail_ops(MCInst *MI, bool Val) {
-	assert(MI);
-	if (!detail_is_set(MI)) {
-		MI->fillDetailOps = false;
-		return;
-	}
-
-	MI->fillDetailOps = Val;
-}
-
-/// Sets the instruction alias flags and the given alias id.
-void map_set_is_alias_insn(MCInst *MI, bool Val, uint64_t Alias) {
-	assert(MI);
-	MI->isAliasInstr = Val;
-	MI->flat_insn->is_alias = Val;
-	MI->flat_insn->alias_id = Alias;
-}
-
-static inline bool char_ends_mnem(const char c) {
-	return (!c || c == ' ' || c == '\t');
-}
-
-/// Sets an alternative id for some instruction.
-/// Or -1 if it fails.
-/// You must add (<ARCH>_INS_ALIAS_BEGIN + 1) to the id to get the real id.
-void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_id_map, int map_size) {
-	if (!MCInst_isAlias(MI))
-		return;
-
-	char alias_mnem[16] = { 0 };
-	int i = 0, j = 0;
-	const char *asm_str_buf = O->buffer;
-	// Skip spaces and tabs
-	while (is_blank_char(asm_str_buf[i])) {
-		if (!asm_str_buf[i]) {
-			MI->flat_insn->alias_id = -1;
-			return;
-		}
-		++i;
-	}
-	for (; j < sizeof(alias_mnem) - 1; ++j, ++i) {
-		if (char_ends_mnem(asm_str_buf[i]))
-			break;
-		alias_mnem[j] = asm_str_buf[i];
-	}
-
-	MI->flat_insn->alias_id = name2id(alias_mnem_id_map, map_size, alias_mnem);
-}
-
-/// Does a binary search over the given map and searches for @id.
-/// If @id exists in @map, it sets @found to true and returns
-/// the value for the @id.
-/// Otherwise, @found is set to false and it returns UINT64_MAX.
-///
-/// Of course it assumes the map is sorted.
-uint64_t enum_map_bin_search(const cs_enum_id_map *map, size_t map_len,
-			     const char *id, bool *found)
-{
-	size_t l = 0;
-	size_t r = map_len;
-	size_t id_len = strlen(id);
-
-	while (l <= r) {
-		size_t m = (l + r) / 2;
-		size_t j = 0;
-		size_t i = 0;
-		size_t entry_len = strlen(map[m].str);
-
-		while (j < entry_len && i < id_len && id[i] == map[m].str[j]) {
-			++j, ++i;
-		}
-		if (i == id_len && j == entry_len) {
-			*found = true;
-			return map[m].val;
-		}
-
-		if (id[i] < map[m].str[j]) {
-			r = m - 1;
-		} else if (id[i] > map[m].str[j]) {
-			l = m + 1;
-		}
-		if (m == 0 || (l + r) / 2 >= map_len) {
-			// Break before we go out of bounds.
-			break;
-		}
-	}
-	*found = false;
-	return UINT64_MAX;
-}
-

thirdparty/capstone/Mapping.h

@@ -1,258 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
-
-#ifndef CS_MAPPING_H
-#define CS_MAPPING_H
-
-#if defined(CAPSTONE_HAS_OSXKERNEL)
-#include <libkern/libkern.h>
-#else
-#include "include/capstone/capstone.h"
-#include <stddef.h>
-#endif
-#include "cs_priv.h"
-#include <assert.h>
-#include <string.h>
-
-// map instruction to its characteristics
-typedef struct insn_map {
-	unsigned short id;		    // The LLVM instruction id
-	unsigned short mapid;		    // The Capstone instruction id
-#ifndef CAPSTONE_DIET
-	uint16_t regs_use[MAX_IMPL_R_REGS]; ///< list of implicit registers used by
-					    ///< this instruction
-	uint16_t regs_mod[MAX_IMPL_W_REGS]; ///< list of implicit registers modified
-					    ///< by this instruction
-	unsigned char groups
-		[MAX_NUM_GROUPS]; ///< list of group this instruction belong to
-	bool branch;		  // branch instruction?
-	bool indirect_branch;	  // indirect branch instruction?
-	union {
-		ppc_suppl_info ppc;
-		loongarch_suppl_info loongarch;
-		aarch64_suppl_info aarch64;
-	} suppl_info; // Supplementary information for each instruction.
-#endif
-} insn_map;
-
-// look for @id in @m, given its size in @max. first time call will update
-// @cache. return 0 if not found
-unsigned short insn_find(const insn_map *m, unsigned int max, unsigned int id,
-			 unsigned short **cache);
-
-unsigned int find_cs_id(unsigned MC_Opcode, const insn_map *imap,
-			unsigned imap_size);
-
-#define MAX_NO_DATA_TYPES 16
-
-///< A LLVM<->CS Mapping entry of an MCOperand.
-typedef struct {
-	uint8_t /* cs_op_type */ type;	 ///< Operand type (e.g.: reg, imm, mem)
-	uint8_t /* cs_ac_type */ access; ///< The access type (read, write)
-	uint8_t				 /* cs_data_type */
-		dtypes[MAX_NO_DATA_TYPES]; ///< List of op types. Terminated by
-					   ///< CS_DATA_TYPE_LAST
-} mapping_op;
-
-#define MAX_NO_INSN_MAP_OPS 16
-
-///< MCOperands of an instruction.
-typedef struct {
-	mapping_op
-		ops[MAX_NO_INSN_MAP_OPS]; ///< NULL terminated array of insn_op.
-} map_insn_ops;
-
-/// Only usable by `auto-sync` archs!
-const cs_op_type mapping_get_op_type(MCInst *MI, unsigned OpNum,
-				     const map_insn_ops *insn_ops_map,
-				     size_t map_size);
-
-/// Only usable by `auto-sync` archs!
-const cs_ac_type mapping_get_op_access(MCInst *MI, unsigned OpNum,
-				       const map_insn_ops *insn_ops_map,
-				       size_t map_size);
-
-/// Macro for easier access of operand types from the map.
-/// Assumes the istruction operands map is called "insn_operands"
-/// Only usable by `auto-sync` archs!
-#ifndef CAPSTONE_DIET
-#define map_get_op_type(MI, OpNum) \
-	mapping_get_op_type(MI, OpNum, (const map_insn_ops *)insn_operands, \
-			    sizeof(insn_operands) / sizeof(insn_operands[0]))
-#else
-#define map_get_op_type(MI, OpNum) \
-	CS_OP_INVALID
-#endif
-
-/// Macro for easier access of operand access flags from the map.
-/// Assumes the istruction operands map is called "insn_operands"
-/// Only usable by `auto-sync` archs!
-#ifndef CAPSTONE_DIET
-#define map_get_op_access(MI, OpNum) \
-	mapping_get_op_access(MI, OpNum, (const map_insn_ops *)insn_operands, \
-			      sizeof(insn_operands) / \
-				      sizeof(insn_operands[0]))
-#else
-#define map_get_op_access(MI, OpNum) \
-	CS_AC_INVALID
-#endif
-
-///< Map for ids to their string
-typedef struct name_map {
-	unsigned int id;
-	const char *name;
-} name_map;
-
-// map a name to its ID
-// return 0 if not found
-int name2id(const name_map *map, int max, const char *name);
-
-// map ID to a name
-// return NULL if not found
-const char *id2name(const name_map *map, int max, const unsigned int id);
-
-void map_add_implicit_write(MCInst *MI, uint32_t Reg);
-void map_add_implicit_read(MCInst *MI, uint32_t Reg);
-void map_remove_implicit_write(MCInst *MI, uint32_t Reg);
-
-void map_implicit_reads(MCInst *MI, const insn_map *imap);
-
-void map_implicit_writes(MCInst *MI, const insn_map *imap);
-
-void add_group(MCInst *MI, unsigned /* arch_group */ group);
-
-void map_groups(MCInst *MI, const insn_map *imap);
-
-void map_cs_id(MCInst *MI, const insn_map *imap, unsigned int imap_size);
-
-const void *map_get_suppl_info(MCInst *MI, const insn_map *imap);
-
-#define DECL_get_detail_op(arch, ARCH) \
-	cs_##arch##_op *ARCH##_get_detail_op(MCInst *MI, int offset);
-
-DECL_get_detail_op(arm, ARM);
-DECL_get_detail_op(ppc, PPC);
-DECL_get_detail_op(tricore, TriCore);
-DECL_get_detail_op(aarch64, AArch64);
-DECL_get_detail_op(alpha, Alpha);
-DECL_get_detail_op(hppa, HPPA);
-DECL_get_detail_op(loongarch, LoongArch);
-DECL_get_detail_op(riscv, RISCV);
-
-/// Increments the detail->arch.op_count by one.
-#define DEFINE_inc_detail_op_count(arch, ARCH) \
-	static inline void ARCH##_inc_op_count(MCInst *MI) \
-	{ \
-		MI->flat_insn->detail->arch.op_count++; \
-	}
-
-/// Decrements the detail->arch.op_count by one.
-#define DEFINE_dec_detail_op_count(arch, ARCH) \
-	static inline void ARCH##_dec_op_count(MCInst *MI) \
-	{ \
-		MI->flat_insn->detail->arch.op_count--; \
-	}
-
-DEFINE_inc_detail_op_count(arm, ARM);
-DEFINE_dec_detail_op_count(arm, ARM);
-DEFINE_inc_detail_op_count(ppc, PPC);
-DEFINE_dec_detail_op_count(ppc, PPC);
-DEFINE_inc_detail_op_count(tricore, TriCore);
-DEFINE_dec_detail_op_count(tricore, TriCore);
-DEFINE_inc_detail_op_count(aarch64, AArch64);
-DEFINE_dec_detail_op_count(aarch64, AArch64);
-DEFINE_inc_detail_op_count(alpha, Alpha);
-DEFINE_dec_detail_op_count(alpha, Alpha);
-DEFINE_inc_detail_op_count(hppa, HPPA);
-DEFINE_dec_detail_op_count(hppa, HPPA);
-DEFINE_inc_detail_op_count(loongarch, LoongArch);
-DEFINE_dec_detail_op_count(loongarch, LoongArch);
-DEFINE_inc_detail_op_count(riscv, RISCV);
-DEFINE_dec_detail_op_count(riscv, RISCV);
-
-/// Returns true if a memory operand is currently edited.
-static inline bool doing_mem(const MCInst *MI)
-{
-	return MI->csh->doing_mem;
-}
-
-/// Sets the doing_mem flag to @status.
-static inline void set_doing_mem(const MCInst *MI, bool status)
-{
-	MI->csh->doing_mem = status;
-}
-
-/// Returns detail->arch
-#define DEFINE_get_arch_detail(arch, ARCH) \
-	static inline cs_##arch *ARCH##_get_detail(const MCInst *MI) \
-	{ \
-		assert(MI && MI->flat_insn && MI->flat_insn->detail); \
-		return &MI->flat_insn->detail->arch; \
-	}
-
-DEFINE_get_arch_detail(arm, ARM);
-DEFINE_get_arch_detail(ppc, PPC);
-DEFINE_get_arch_detail(tricore, TriCore);
-DEFINE_get_arch_detail(aarch64, AArch64);
-DEFINE_get_arch_detail(alpha, Alpha);
-DEFINE_get_arch_detail(hppa, HPPA);
-DEFINE_get_arch_detail(loongarch, LoongArch);
-DEFINE_get_arch_detail(riscv, RISCV);
-
-static inline bool detail_is_set(const MCInst *MI)
-{
-	assert(MI && MI->flat_insn);
-	return MI->flat_insn->detail != NULL && MI->csh->detail_opt & CS_OPT_ON;
-}
-
-static inline cs_detail *get_detail(const MCInst *MI)
-{
-	assert(MI && MI->flat_insn);
-	return MI->flat_insn->detail;
-}
-
-/// Returns if the given instruction is an alias instruction.
-#define RETURN_IF_INSN_IS_ALIAS(MI) \
-do { \
-	if (MI->isAliasInstr) \
-		return; \
-} while(0)
-
-void map_set_fill_detail_ops(MCInst *MI, bool Val);
-
-static inline bool map_fill_detail_ops(MCInst *MI) {
-	assert(MI);
-	return MI->fillDetailOps;
-}
-
-void map_set_is_alias_insn(MCInst *MI, bool Val, uint64_t Alias);
-
-bool map_use_alias_details(const MCInst *MI);
-
-void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_id_map, int map_size);
-
-/// Mapping from Capstone enumeration identifiers and their values.
-///
-/// This map MUST BE sorted to allow binary searches.
-/// Please always ensure the map is sorted after you added a value.
-///
-/// You can sort the map with Python.
-/// Copy the map into a file and run:
-///
-/// ```python
-/// with open("/tmp/file_with_map_entries") as f:
-///     text = f.readlines()
-///
-/// text.sort()
-/// print(''.join(text))
-/// ```
-typedef struct {
-	const char *str; ///< The name of the enumeration identifier
-	uint64_t val;	 ///< The value of the identifier
-} cs_enum_id_map;
-
-uint64_t enum_map_bin_search(const cs_enum_id_map *map, size_t map_len,
-			     const char *id, bool *found);
-
-#endif // CS_MAPPING_H

thirdparty/capstone/MathExtras.h

@@ -1,488 +0,0 @@
-//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains some functions that are useful for math stuff.
-//
-//===----------------------------------------------------------------------===//
-
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#ifndef CS_LLVM_SUPPORT_MATHEXTRAS_H
-#define CS_LLVM_SUPPORT_MATHEXTRAS_H
-
-#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
-#include "windowsce/intrin.h"
-#elif defined(_MSC_VER)
-#include <intrin.h>
-#endif
-
-#ifndef __cplusplus
-#ifdef _MSC_VER
-#define inline /* inline */
-#endif
-#endif
-
-// NOTE: The following support functions use the _32/_64 extensions instead of
-// type overloading so that signed and unsigned integers can be used without
-// ambiguity.
-
-/// Hi_32 - This function returns the high 32 bits of a 64 bit value.
-static inline uint32_t Hi_32(uint64_t Value) {
-	return (uint32_t)(Value >> 32);
-}
-
-/// Lo_32 - This function returns the low 32 bits of a 64 bit value.
-static inline uint32_t Lo_32(uint64_t Value) {
-	return (uint32_t)(Value);
-}
-
-/// isUIntN - Checks if an unsigned integer fits into the given (dynamic)
-/// bit width.
-static inline bool isUIntN(unsigned N, uint64_t x) {
-	return x == (x & (~0ULL >> (64 - N)));
-}
-
-/// isIntN - Checks if an signed integer fits into the given (dynamic)
-/// bit width.
-//static inline bool isIntN(unsigned N, int64_t x) {
-//  return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));
-//}
-
-/// isMask_32 - This function returns true if the argument is a sequence of ones
-/// starting at the least significant bit with the remainder zero (32 bit
-/// version).   Ex. isMask_32(0x0000FFFFU) == true.
-static inline bool isMask_32(uint32_t Value) {
-	return Value && ((Value + 1) & Value) == 0;
-}
-
-/// isMask_64 - This function returns true if the argument is a sequence of ones
-/// starting at the least significant bit with the remainder zero (64 bit
-/// version).
-static inline bool isMask_64(uint64_t Value) {
-	return Value && ((Value + 1) & Value) == 0;
-}
-
-/// isShiftedMask_32 - This function returns true if the argument contains a
-/// sequence of ones with the remainder zero (32 bit version.)
-/// Ex. isShiftedMask_32(0x0000FF00U) == true.
-static inline bool isShiftedMask_32(uint32_t Value) {
-	return isMask_32((Value - 1) | Value);
-}
-
-/// isShiftedMask_64 - This function returns true if the argument contains a
-/// sequence of ones with the remainder zero (64 bit version.)
-static inline bool isShiftedMask_64(uint64_t Value) {
-	return isMask_64((Value - 1) | Value);
-}
-
-/// isPowerOf2_32 - This function returns true if the argument is a power of
-/// two > 0. Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.)
-static inline bool isPowerOf2_32(uint32_t Value) {
-	return Value && !(Value & (Value - 1));
-}
-
-/// CountLeadingZeros_32 - this function performs the platform optimal form of
-/// counting the number of zeros from the most significant bit to the first one
-/// bit.  Ex. CountLeadingZeros_32(0x00F000FF) == 8.
-/// Returns 32 if the word is zero.
-static inline unsigned CountLeadingZeros_32(uint32_t Value) {
-	unsigned Count; // result
-#if __GNUC__ >= 4
-	// PowerPC is defined for __builtin_clz(0)
-#if !defined(__ppc__) && !defined(__ppc64__)
-	if (!Value) return 32;
-#endif
-	Count = __builtin_clz(Value);
-#else
-	unsigned Shift;
-	if (!Value) return 32;
-	Count = 0;
-	// bisection method for count leading zeros
-	for (Shift = 32 >> 1; Shift; Shift >>= 1) {
-		uint32_t Tmp = Value >> Shift;
-		if (Tmp) {
-			Value = Tmp;
-		} else {
-			Count |= Shift;
-		}
-	}
-#endif
-	return Count;
-}
-
-/// CountLeadingOnes_32 - this function performs the operation of
-/// counting the number of ones from the most significant bit to the first zero
-/// bit.  Ex. CountLeadingOnes_32(0xFF0FFF00) == 8.
-/// Returns 32 if the word is all ones.
-static inline unsigned CountLeadingOnes_32(uint32_t Value) {
-	return CountLeadingZeros_32(~Value);
-}
-
-/// CountLeadingZeros_64 - This function performs the platform optimal form
-/// of counting the number of zeros from the most significant bit to the first
-/// one bit (64 bit edition.)
-/// Returns 64 if the word is zero.
-static inline unsigned CountLeadingZeros_64(uint64_t Value) {
-	unsigned Count; // result
-#if __GNUC__ >= 4
-	// PowerPC is defined for __builtin_clzll(0)
-#if !defined(__ppc__) && !defined(__ppc64__)
-	if (!Value) return 64;
-#endif
-	Count = __builtin_clzll(Value);
-#else
-#ifndef _MSC_VER
-	unsigned Shift;
-	if (sizeof(long) == sizeof(int64_t))
-	{
-		if (!Value) return 64;
-		Count = 0;
-		// bisection method for count leading zeros
-		for (Shift = 64 >> 1; Shift; Shift >>= 1) {
-			uint64_t Tmp = Value >> Shift;
-			if (Tmp) {
-				Value = Tmp;
-			} else {
-				Count |= Shift;
-			}
-		}
-	}
-	else
-#endif
-	{
-		// get hi portion
-		uint32_t Hi = Hi_32(Value);
-
-		// if some bits in hi portion
-		if (Hi) {
-			// leading zeros in hi portion plus all bits in lo portion
-			Count = CountLeadingZeros_32(Hi);
-		} else {
-			// get lo portion
-			uint32_t Lo = Lo_32(Value);
-			// same as 32 bit value
-			Count = CountLeadingZeros_32(Lo)+32;
-		}
-	}
-#endif
-	return Count;
-}
-
-/// CountLeadingOnes_64 - This function performs the operation
-/// of counting the number of ones from the most significant bit to the first
-/// zero bit (64 bit edition.)
-/// Returns 64 if the word is all ones.
-static inline unsigned CountLeadingOnes_64(uint64_t Value) {
-	return CountLeadingZeros_64(~Value);
-}
-
-/// CountTrailingZeros_32 - this function performs the platform optimal form of
-/// counting the number of zeros from the least significant bit to the first one
-/// bit.  Ex. CountTrailingZeros_32(0xFF00FF00) == 8.
-/// Returns 32 if the word is zero.
-static inline unsigned CountTrailingZeros_32(uint32_t Value) {
-#if __GNUC__ >= 4
-	return Value ? __builtin_ctz(Value) : 32;
-#else
-	static const unsigned Mod37BitPosition[] = {
-		32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13,
-		4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9,
-		5, 20, 8, 19, 18
-	};
-	// Replace "-Value" by "1+~Value" in the following commented code to avoid 
-	// MSVC warning C4146
-	//    return Mod37BitPosition[(-Value & Value) % 37];
-	return Mod37BitPosition[((1 + ~Value) & Value) % 37];
-#endif
-}
-
-// Count trailing zeros as in:
-// https://graphics.stanford.edu/~seander/bithacks.html#ZerosOnRightParallel
-static inline unsigned CountTrailingZeros_8(uint8_t Value) {
-	uint8_t c = 8;
-	Value &= -((int8_t)Value);
-	if (Value) c--;
-	if (Value & 0x0F) c -= 4;
-	if (Value & 0x33) c -= 2;
-	if (Value & 0x55) c -= 1;
-	return c;
-}
-
-/// CountTrailingOnes_32 - this function performs the operation of
-/// counting the number of ones from the least significant bit to the first zero
-/// bit.  Ex. CountTrailingOnes_32(0x00FF00FF) == 8.
-/// Returns 32 if the word is all ones.
-static inline unsigned CountTrailingOnes_32(uint32_t Value) {
-	return CountTrailingZeros_32(~Value);
-}
-
-/// CountTrailingZeros_64 - This function performs the platform optimal form
-/// of counting the number of zeros from the least significant bit to the first
-/// one bit (64 bit edition.)
-/// Returns 64 if the word is zero.
-static inline unsigned CountTrailingZeros_64(uint64_t Value) {
-#if __GNUC__ >= 4
-	return Value ? __builtin_ctzll(Value) : 64;
-#else
-	static const unsigned Mod67Position[] = {
-		64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54,
-		4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55,
-		47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27,
-		29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56,
-		7, 48, 35, 6, 34, 33, 0
-	};
-	// Replace "-Value" by "1+~Value" in the following commented code to avoid 
-	// MSVC warning C4146
-	//    return Mod67Position[(-Value & Value) % 67];
-	return Mod67Position[((1 + ~Value) & Value) % 67];
-#endif
-}
-
-/// CountTrailingOnes_64 - This function performs the operation
-/// of counting the number of ones from the least significant bit to the first
-/// zero bit (64 bit edition.)
-/// Returns 64 if the word is all ones.
-static inline unsigned CountTrailingOnes_64(uint64_t Value) {
-	return CountTrailingZeros_64(~Value);
-}
-
-/// CountPopulation_32 - this function counts the number of set bits in a value.
-/// Ex. CountPopulation(0xF000F000) = 8
-/// Returns 0 if the word is zero.
-static inline unsigned CountPopulation_32(uint32_t Value) {
-#if __GNUC__ >= 4
-	return __builtin_popcount(Value);
-#else
-	uint32_t v = Value - ((Value >> 1) & 0x55555555);
-	v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
-	return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
-#endif
-}
-
-/// CountPopulation_64 - this function counts the number of set bits in a value,
-/// (64 bit edition.)
-static inline unsigned CountPopulation_64(uint64_t Value) {
-#if __GNUC__ >= 4
-	return __builtin_popcountll(Value);
-#else
-	uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL);
-	v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL);
-	v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
-	return (uint64_t)((v * 0x0101010101010101ULL) >> 56);
-#endif
-}
-
-/// Log2_32 - This function returns the floor log base 2 of the specified value,
-/// -1 if the value is zero. (32 bit edition.)
-/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2
-static inline unsigned Log2_32(uint32_t Value) {
-	return 31 - CountLeadingZeros_32(Value);
-}
-
-/// Log2_64 - This function returns the floor log base 2 of the specified value,
-/// -1 if the value is zero. (64 bit edition.)
-static inline unsigned Log2_64(uint64_t Value) {
-	return 63 - CountLeadingZeros_64(Value);
-}
-
-/// Log2_32_Ceil - This function returns the ceil log base 2 of the specified
-/// value, 32 if the value is zero. (32 bit edition).
-/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3
-static inline unsigned Log2_32_Ceil(uint32_t Value) {
-	return 32-CountLeadingZeros_32(Value-1);
-}
-
-/// Log2_64_Ceil - This function returns the ceil log base 2 of the specified
-/// value, 64 if the value is zero. (64 bit edition.)
-static inline unsigned Log2_64_Ceil(uint64_t Value) {
-	return 64-CountLeadingZeros_64(Value-1);
-}
-
-/// GreatestCommonDivisor64 - Return the greatest common divisor of the two
-/// values using Euclid's algorithm.
-static inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) {
-	while (B) {
-		uint64_t T = B;
-		B = A % B;
-		A = T;
-	}
-	return A;
-}
-
-/// BitsToDouble - This function takes a 64-bit integer and returns the bit
-/// equivalent double.
-static inline double BitsToDouble(uint64_t Bits) {
-	union {
-		uint64_t L;
-		double D;
-	} T;
-	T.L = Bits;
-	return T.D;
-}
-
-/// BitsToFloat - This function takes a 32-bit integer and returns the bit
-/// equivalent float.
-static inline float BitsToFloat(uint32_t Bits) {
-	union {
-		uint32_t I;
-		float F;
-	} T;
-	T.I = Bits;
-	return T.F;
-}
-
-/// DoubleToBits - This function takes a double and returns the bit
-/// equivalent 64-bit integer.  Note that copying doubles around
-/// changes the bits of NaNs on some hosts, notably x86, so this
-/// routine cannot be used if these bits are needed.
-static inline uint64_t DoubleToBits(double Double) {
-	union {
-		uint64_t L;
-		double D;
-	} T;
-	T.D = Double;
-	return T.L;
-}
-
-/// FloatToBits - This function takes a float and returns the bit
-/// equivalent 32-bit integer.  Note that copying floats around
-/// changes the bits of NaNs on some hosts, notably x86, so this
-/// routine cannot be used if these bits are needed.
-static inline uint32_t FloatToBits(float Float) {
-	union {
-		uint32_t I;
-		float F;
-	} T;
-	T.F = Float;
-	return T.I;
-}
-
-/// MinAlign - A and B are either alignments or offsets.  Return the minimum
-/// alignment that may be assumed after adding the two together.
-static inline uint64_t MinAlign(uint64_t A, uint64_t B) {
-	// The largest power of 2 that divides both A and B.
-	//
-	// Replace "-Value" by "1+~Value" in the following commented code to avoid 
-	// MSVC warning C4146
-	//    return (A | B) & -(A | B);
-	return (A | B) & (1 + ~(A | B));
-}
-
-/// NextPowerOf2 - Returns the next power of two (in 64-bits)
-/// that is strictly greater than A.  Returns zero on overflow.
-static inline uint64_t NextPowerOf2(uint64_t A) {
-	A |= (A >> 1);
-	A |= (A >> 2);
-	A |= (A >> 4);
-	A |= (A >> 8);
-	A |= (A >> 16);
-	A |= (A >> 32);
-	return A + 1;
-}
-
-/// Returns the next integer (mod 2**64) that is greater than or equal to
-/// \p Value and is a multiple of \p Align. \p Align must be non-zero.
-///
-/// Examples:
-/// \code
-///   RoundUpToAlignment(5, 8) = 8
-///   RoundUpToAlignment(17, 8) = 24
-///   RoundUpToAlignment(~0LL, 8) = 0
-/// \endcode
-static inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) {
-	return ((Value + Align - 1) / Align) * Align;
-}
-
-/// Returns the offset to the next integer (mod 2**64) that is greater than
-/// or equal to \p Value and is a multiple of \p Align. \p Align must be
-/// non-zero.
-static inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) {
-	return RoundUpToAlignment(Value, Align) - Value;
-}
-
-/// abs64 - absolute value of a 64-bit int.  Not all environments support
-/// "abs" on whatever their name for the 64-bit int type is.  The absolute
-/// value of the largest negative number is undefined, as with "abs".
-static inline int64_t abs64(int64_t x) {
-	return (x < 0) ? -x : x;
-}
-
-/// \brief Sign extend number in the bottom B bits of X to a 32-bit int.
-/// Requires 0 < B <= 32.
-/// Note that this implementation relies on right shift of signed
-/// integers being an arithmetic shift.
-static inline int32_t SignExtend32(uint32_t X, unsigned B) {
-	return (int32_t)(X << (32 - B)) >> (32 - B);
-}
-
-/// \brief Sign extend number in the bottom B bits of X to a 64-bit int.
-/// Requires 0 < B <= 64.
-/// Note that this implementation relies on right shift of signed
-/// integers being an arithmetic shift.
-static inline int64_t SignExtend64(uint64_t X, unsigned B) {
-	return (int64_t)(X << (64 - B)) >> (64 - B);
-}
-
-/// \brief Removes the rightmost bit of x and extends the field to the left with that
-/// bit to form a 64-bit quantity. The field is of size len
-static inline int64_t LowSignExtend64(uint64_t x, unsigned len) {
-    return (x >> 1) - ((x & 1) << (len - 1));
-}
-
-/// \brief One extend number X starting at bit B and returns it as int32_t.
-/// Requires 0 < B <= 32.
-static inline int32_t OneExtend32(uint32_t X, unsigned B) {
-	return (~0U << B) | X;
-}
-
-/// \brief One extend number X starting at bit B and returns it as int64_t.
-/// Requires 0 < B <= 64.
-static inline int64_t OneExtend64(uint64_t X, unsigned B) {
-	return (~0ULL << B) | X;
-}
-
-/// \brief Count number of 0's from the most significant bit to the least
-///   stopping at the first 1.
-///
-/// Only unsigned integral types are allowed.
-///
-/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are
-///   valid arguments.
-static inline unsigned int countLeadingZeros(int x)
-{
-	int i;
-	const unsigned bits = sizeof(x) * 8;
-	unsigned count = bits;
-
-	if (x < 0) {
-		return 0;
-	}
-	for (i = bits; --i; ) {
-		if (x == 0) break;
-		count--;
-		x >>= 1;
-	}
-
-	return count;
-}
-
-/// \brief Get specified field from 32-bit instruction. Returns bits from the segment [from, to]
-static inline uint32_t get_insn_field(uint32_t insn, uint8_t from, uint8_t to) 
-{
-	return insn >> (31 - to) & ((1 << (to - from + 1)) - 1);
-}
-
-/// \brief Get specified bit from 32-bit instruction
-static inline uint32_t get_insn_bit(uint32_t insn, uint8_t bit) 
-{
-	return get_insn_field(insn, bit, bit);
-}
-
-#endif

thirdparty/capstone/README.md

@@ -1,77 +0,0 @@
-Capstone Engine
-===============
-
-[![Build status](https://ci.appveyor.com/api/projects/status/a4wvbn89wu3pinas/branch/next?svg=true)](https://ci.appveyor.com/project/aquynh/capstone/branch/next)
-[![pypi package](https://badge.fury.io/py/capstone.svg)](https://pypi.python.org/pypi/capstone)
-[![pypi downloads](https://pepy.tech/badge/capstone)](https://pepy.tech/project/capstone)
-[![oss-fuzz Status](https://oss-fuzz-build-logs.storage.googleapis.com/badges/capstone.svg)](https://bugs.chromium.org/p/oss-fuzz/issues/list?sort=-opened&can=1&q=proj:capstone)
-
-> [!TIP]
-> Welcome to join our community group! &ensp; [<img src="https://img.shields.io/badge/Telegram-2CA5E0?style=flat-squeare&logo=telegram&logoColor=white" height="22" />](https://t.me/CapstoneEngine)
-
-Capstone is a disassembly framework with the target of becoming the ultimate
-disasm engine for binary analysis and reversing in the security community.
-
-Created by Nguyen Anh Quynh, then developed and maintained by a small community,
-Capstone offers some unparalleled features:
-
-- Support multiple hardware architectures: ARM, AArch64, Alpha, BPF, Ethereum VM,
-  LoongArch, HP PA-RISC (HPPA), M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH,
-  Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86 (16, 32, 64).
-
-- Having clean/simple/lightweight/intuitive architecture-neutral API.
-
-- Provide details on disassembled instruction (called “decomposer” by others).
-
-- Provide semantics of the disassembled instruction, such as list of implicit
-  registers read & written.
-
-- Implemented in pure C language, with lightweight bindings for Swift, D, Clojure, F#,
-  Common Lisp, Visual Basic, PHP, PowerShell, Emacs, Haskell, Perl, Python,
-  Ruby, C#, NodeJS, Java, GO, C++, OCaml, Lua, Rust, Delphi, Free Pascal & Vala
-  ready either in main code, or provided externally by the community).
-
-- Native support for all popular platforms: Windows, Mac OSX, iOS, Android,
-  Linux, \*BSD, Solaris, etc.
-
-- Thread-safe by design.
-
-- Special support for embedding into firmware or OS kernel.
-
-- High performance & suitable for malware analysis (capable of handling various
-  X86 malware tricks).
-
-- Distributed under the open source BSD license.
-
-Further information is available at https://www.capstone-engine.org
-
-
-Compile
--------
-
-See [COMPILE_CMAKE.TXT](COMPILE_CMAKE.TXT) file for how to compile and install Capstone.
-
-
-Documentation
--------------
-
-See docs/README for how to customize & program your own tools with Capstone.
-
-
-Hack
-----
-
-See HACK.TXT file for the structure of the source code.
-
-
-Fuzz
-----
-
-See suite/fuzz/README.md for more information.
-
-
-License
--------
-
-This project is released under the BSD license. If you redistribute the binary
-or source code of Capstone, please attach file LICENSE.TXT with your products.

thirdparty/capstone/SPONSORS.TXT

@@ -1,20 +0,0 @@
-* Version 4.0.1 - January 10th, 2019
-
-Release 4.0.1 was sponsored by the following companies (in no particular order).
-
-- NowSecure: https://www.nowsecure.com
-- Verichains: https://verichains.io
-- Vsec: https://vsec.com.vn
-
------------------------------------
-* Version 4.0 - December 18th, 2018
-
-Capstone 4.0 version marks 5 years of the project!
-This release was sponsored by the following companies (in no particular order).
-
-- Thinkst Canary: https://canary.tools
-- NowSecure: https://www.nowsecure.com
-- ECQ: https://e-cq.net
-- Senrio: https://senr.io
-- GracefulBits: https://gracefulbits.com
-- Catena Cyber: https://catenacyber.fr

thirdparty/capstone/SStream.c

@@ -1,236 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#include <stdarg.h>
-#if defined(CAPSTONE_HAS_OSXKERNEL)
-#include <Availability.h>
-#include <libkern/libkern.h>
-#include <i386/limits.h>
-#else
-#include <stdio.h>
-#include <limits.h>
-#endif
-#include <string.h>
-
-#include <capstone/platform.h>
-
-#include "SStream.h"
-#include "cs_priv.h"
-#include "utils.h"
-
-#ifdef _MSC_VER
-#pragma warning(disable: 4996) // disable MSVC's warning on strcpy()
-#endif
-
-void SStream_Init(SStream *ss)
-{
-	assert(ss);
-	ss->index = 0;
-	ss->buffer[0] = '\0';
-	ss->is_closed = false;
-}
-
-/**
- * Open the output stream. Every write attempt is accepted again.
- */
-void SStream_Open(SStream *ss) {
-	assert(ss);
-	ss->is_closed = false;
-}
-
-/**
- * Closes the output stream. Every write attempt is ignored.
- */
-void SStream_Close(SStream *ss) {
-	assert(ss);
-	ss->is_closed = true;
-}
-
-/**
- * Copy the string \p s to the buffer of \p ss and terminate it with a '\\0' byte.
- */
-void SStream_concat0(SStream *ss, const char *s)
-{
-#ifndef CAPSTONE_DIET
-	SSTREAM_RETURN_IF_CLOSED(ss);
-	if (s[0] == '\0')
-		return;
-	unsigned int len = (unsigned int) strlen(s);
-
-	memcpy(ss->buffer + ss->index, s, len);
-	ss->index += len;
-	ss->buffer[ss->index] = '\0';
-#endif
-}
-
-/**
- * Copy the single char \p c to the buffer of \p ss.
- */
-void SStream_concat1(SStream *ss, const char c)
-{
-#ifndef CAPSTONE_DIET
-	SSTREAM_RETURN_IF_CLOSED(ss);
-	if (c == '\0')
-		return;
-	ss->buffer[ss->index] = c;
-	ss->index++;
-	ss->buffer[ss->index] = '\0';
-#endif
-}
-
-/**
- * Copy all strings given to the buffer of \p ss according to formatting \p fmt.
- */
-void SStream_concat(SStream *ss, const char *fmt, ...)
-{
-#ifndef CAPSTONE_DIET
-	SSTREAM_RETURN_IF_CLOSED(ss);
-	va_list ap;
-	int ret;
-
-	va_start(ap, fmt);
-	ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
-	va_end(ap);
-	ss->index += ret;
-#endif
-}
-
-// print number with prefix #
-void printInt64Bang(SStream *O, int64_t val)
-{
-	SSTREAM_RETURN_IF_CLOSED(O);
-	if (val >= 0) {
-		if (val > HEX_THRESHOLD)
-			SStream_concat(O, "#0x%"PRIx64, val);
-		else
-			SStream_concat(O, "#%"PRIu64, val);
-	} else {
-		if (val <- HEX_THRESHOLD) {
-			if (val == LONG_MIN)
-				SStream_concat(O, "#-0x%"PRIx64, (uint64_t)val);
-			else
-				SStream_concat(O, "#-0x%"PRIx64, (uint64_t)-val);
-		} else
-			SStream_concat(O, "#-%"PRIu64, -val);
-	}
-}
-
-void printUInt64Bang(SStream *O, uint64_t val)
-{
-	SSTREAM_RETURN_IF_CLOSED(O);
-	if (val > HEX_THRESHOLD)
-		SStream_concat(O, "#0x%"PRIx64, val);
-	else
-		SStream_concat(O, "#%"PRIu64, val);
-}
-
-// print number
-void printInt64(SStream *O, int64_t val)
-{
-	SSTREAM_RETURN_IF_CLOSED(O);
-	if (val >= 0) {
-		if (val > HEX_THRESHOLD)
-			SStream_concat(O, "0x%"PRIx64, val);
-		else
-			SStream_concat(O, "%"PRIu64, val);
-	} else {
-		if (val <- HEX_THRESHOLD) {
-			if (val == LONG_MIN)
-				SStream_concat(O, "-0x%"PRIx64, (uint64_t)val);
-			else
-				SStream_concat(O, "-0x%"PRIx64, (uint64_t)-val);
-		} else
-			SStream_concat(O, "-%"PRIu64, -val);
-	}
-}
-
-void printUInt64(SStream *O, uint64_t val)
-{
-	SSTREAM_RETURN_IF_CLOSED(O);
-	if (val > HEX_THRESHOLD)
-		SStream_concat(O, "0x%"PRIx64, val);
-	else
-		SStream_concat(O, "%"PRIu64, val);
-}
-
-// print number in decimal mode
-void printInt32BangDec(SStream *O, int32_t val)
-{
-	SSTREAM_RETURN_IF_CLOSED(O);
-	if (val >= 0)
-		SStream_concat(O, "#%u", val);
-	else {
-		if (val == INT_MIN)
-			SStream_concat(O, "#-%u", val);
-		else
-			SStream_concat(O, "#-%u", (uint32_t)-val);
-	}
-}
-
-void printInt32Bang(SStream *O, int32_t val)
-{
-	SSTREAM_RETURN_IF_CLOSED(O);
-	if (val >= 0) {
-		if (val > HEX_THRESHOLD)
-			SStream_concat(O, "#0x%x", val);
-		else
-			SStream_concat(O, "#%u", val);
-	} else {
-		if (val <- HEX_THRESHOLD) {
-			if (val == INT_MIN)
-				SStream_concat(O, "#-0x%x", (uint32_t)val);
-			else
-				SStream_concat(O, "#-0x%x", (uint32_t)-val);
-		} else
-			SStream_concat(O, "#-%u", -val);
-	}
-}
-
-void printInt32(SStream *O, int32_t val)
-{
-	SSTREAM_RETURN_IF_CLOSED(O);
-	if (val >= 0) {
-		if (val > HEX_THRESHOLD)
-			SStream_concat(O, "0x%x", val);
-		else
-			SStream_concat(O, "%u", val);
-	} else {
-		if (val <- HEX_THRESHOLD) {
-			if (val == INT_MIN)
-				SStream_concat(O, "-0x%x", (uint32_t)val);
-			else
-				SStream_concat(O, "-0x%x", (uint32_t)-val);
-		} else
-			SStream_concat(O, "-%u", -val);
-	}
-}
-
-void printUInt32Bang(SStream *O, uint32_t val)
-{
-	SSTREAM_RETURN_IF_CLOSED(O);
-	if (val > HEX_THRESHOLD)
-		SStream_concat(O, "#0x%x", val);
-	else
-		SStream_concat(O, "#%u", val);
-}
-
-void printUInt32(SStream *O, uint32_t val)
-{
-	SSTREAM_RETURN_IF_CLOSED(O);
-	if (val > HEX_THRESHOLD)
-		SStream_concat(O, "0x%x", val);
-	else
-		SStream_concat(O, "%u", val);
-}
-
-void printFloat(SStream *O, float val)
-{
-	SSTREAM_RETURN_IF_CLOSED(O);
-	SStream_concat(O, "%e", val);
-}
-
-void printFloatBang(SStream *O, float val)
-{
-	SSTREAM_RETURN_IF_CLOSED(O);
-	SStream_concat(O, "#%e", val);
-}

thirdparty/capstone/SStream.h

@@ -1,55 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#ifndef CS_SSTREAM_H_
-#define CS_SSTREAM_H_
-
-#include "include/capstone/platform.h"
-
-typedef struct SStream {
-	char buffer[512];
-	int index;
-	bool is_closed;
-} SStream;
-
-#define SSTREAM_RETURN_IF_CLOSED(OS) \
-do { \
-	if (OS->is_closed) \
-		return; \
-} while(0)
-
-void SStream_Init(SStream *ss);
-
-void SStream_Open(SStream *ss);
-
-void SStream_Close(SStream *ss);
-
-void SStream_concat(SStream *ss, const char *fmt, ...);
-
-void SStream_concat0(SStream *ss, const char *s);
-
-void SStream_concat1(SStream *ss, const char c);
-
-void printInt64Bang(SStream *O, int64_t val);
-
-void printUInt64Bang(SStream *O, uint64_t val);
-
-void printInt64(SStream *O, int64_t val);
-void printUInt64(SStream *O, uint64_t val);
-
-void printInt32Bang(SStream *O, int32_t val);
-
-void printInt32(SStream *O, int32_t val);
-
-void printUInt32Bang(SStream *O, uint32_t val);
-
-void printUInt32(SStream *O, uint32_t val);
-
-// print number in decimal mode
-void printInt32BangDec(SStream *O, int32_t val);
-
-void printFloat(SStream *O, float val);
-
-void printFloatBang(SStream *O, float val);
-
-#endif

thirdparty/capstone/arch/AArch64/AArch64AddressingModes.h

@@ -1,999 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
-/* Automatically translated source file from LLVM. */
-
-/* LLVM-commit: <commit> */
-/* LLVM-tag: <tag> */
-
-/* Only small edits allowed. */
-/* For multiple similar edits, please create a Patch for the translator. */
-
-/* Capstone's C++ file translator: */
-/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
-
-//===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the AArch64 addressing mode implementation stuff.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H
-#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H
-
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-#include <capstone/platform.h>
-
-#include "../../MathExtras.h"
-#include <assert.h>
-#include "../../MathExtras.h"
-
-#define CONCAT(a, b) CONCAT_(a, b)
-#define CONCAT_(a, b) a##_##b
-
-/// AArch64_AM - AArch64 Addressing Mode Stuff
-// CS namespace begin: AArch64_AM
-
-//===----------------------------------------------------------------------===//
-// Shifts
-//
-typedef enum ShiftExtendType {
-	AArch64_AM_InvalidShiftExtend = -1,
-	AArch64_AM_LSL = 0,
-	AArch64_AM_LSR,
-	AArch64_AM_ASR,
-	AArch64_AM_ROR,
-	AArch64_AM_MSL,
-
-	AArch64_AM_UXTB,
-	AArch64_AM_UXTH,
-	AArch64_AM_UXTW,
-	AArch64_AM_UXTX,
-
-	AArch64_AM_SXTB,
-	AArch64_AM_SXTH,
-	AArch64_AM_SXTW,
-	AArch64_AM_SXTX,
-} AArch64_AM_ShiftExtendType;
-
-/// getShiftName - Get the string encoding for the shift type.
-static inline const char *
-AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST)
-{
-	switch (ST) {
-	default:
-		assert(0 && "unhandled shift type!");
-	case AArch64_AM_LSL:
-		return "lsl";
-	case AArch64_AM_LSR:
-		return "lsr";
-	case AArch64_AM_ASR:
-		return "asr";
-	case AArch64_AM_ROR:
-		return "ror";
-	case AArch64_AM_MSL:
-		return "msl";
-	case AArch64_AM_UXTB:
-		return "uxtb";
-	case AArch64_AM_UXTH:
-		return "uxth";
-	case AArch64_AM_UXTW:
-		return "uxtw";
-	case AArch64_AM_UXTX:
-		return "uxtx";
-	case AArch64_AM_SXTB:
-		return "sxtb";
-	case AArch64_AM_SXTH:
-		return "sxth";
-	case AArch64_AM_SXTW:
-		return "sxtw";
-	case AArch64_AM_SXTX:
-		return "sxtx";
-	}
-	return NULL;
-}
-
-/// getShiftType - Extract the shift type.
-static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm)
-{
-	switch ((Imm >> 6) & 0x7) {
-	default:
-		return AArch64_AM_InvalidShiftExtend;
-	case 0:
-		return AArch64_AM_LSL;
-	case 1:
-		return AArch64_AM_LSR;
-	case 2:
-		return AArch64_AM_ASR;
-	case 3:
-		return AArch64_AM_ROR;
-	case 4:
-		return AArch64_AM_MSL;
-	}
-}
-
-/// getShiftValue - Extract the shift value.
-static inline unsigned AArch64_AM_getShiftValue(unsigned Imm)
-{
-	return Imm & 0x3f;
-}
-
-/// getShifterImm - Encode the shift type and amount:
-///   imm:     6-bit shift amount
-///   shifter: 000 ==> lsl
-///            001 ==> lsr
-///            010 ==> asr
-///            011 ==> ror
-///            100 ==> msl
-///   {8-6}  = shifter
-///   {5-0}  = imm
-static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST,
-						unsigned Imm)
-{
-	unsigned STEnc = 0;
-	switch (ST) {
-	default:
-		assert(0 && "Invalid shift requested");
-	case AArch64_AM_LSL:
-		STEnc = 0;
-		break;
-	case AArch64_AM_LSR:
-		STEnc = 1;
-		break;
-	case AArch64_AM_ASR:
-		STEnc = 2;
-		break;
-	case AArch64_AM_ROR:
-		STEnc = 3;
-		break;
-	case AArch64_AM_MSL:
-		STEnc = 4;
-		break;
-	}
-	return (STEnc << 6) | (Imm & 0x3f);
-}
-
-//===----------------------------------------------------------------------===//
-// Extends
-//
-/// getArithShiftValue - get the arithmetic shift value.
-static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm)
-{
-	return Imm & 0x7;
-}
-
-/// getExtendType - Extract the extend type for operands of arithmetic ops.
-static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm)
-{
-	switch (Imm) {
-	default:
-		assert(0 && "Compiler bug!");
-	case 0:
-		return AArch64_AM_UXTB;
-	case 1:
-		return AArch64_AM_UXTH;
-	case 2:
-		return AArch64_AM_UXTW;
-	case 3:
-		return AArch64_AM_UXTX;
-	case 4:
-		return AArch64_AM_SXTB;
-	case 5:
-		return AArch64_AM_SXTH;
-	case 6:
-		return AArch64_AM_SXTW;
-	case 7:
-		return AArch64_AM_SXTX;
-	}
-}
-
-static inline AArch64_AM_ShiftExtendType
-AArch64_AM_getArithExtendType(unsigned Imm)
-{
-	return AArch64_AM_getExtendType((Imm >> 3) & 0x7);
-}
-
-/// Mapping from extend bits to required operation:
-///   shifter: 000 ==> uxtb
-///            001 ==> uxth
-///            010 ==> uxtw
-///            011 ==> uxtx
-///            100 ==> sxtb
-///            101 ==> sxth
-///            110 ==> sxtw
-///            111 ==> sxtx
-static inline unsigned
-AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET)
-{
-	switch (ET) {
-	default:
-		assert(0 && "Invalid extend type requested");
-	case AArch64_AM_UXTB:
-		return 0;
-		break;
-	case AArch64_AM_UXTH:
-		return 1;
-		break;
-	case AArch64_AM_UXTW:
-		return 2;
-		break;
-	case AArch64_AM_UXTX:
-		return 3;
-		break;
-	case AArch64_AM_SXTB:
-		return 4;
-		break;
-	case AArch64_AM_SXTH:
-		return 5;
-		break;
-	case AArch64_AM_SXTW:
-		return 6;
-		break;
-	case AArch64_AM_SXTX:
-		return 7;
-		break;
-	}
-}
-
-/// getArithExtendImm - Encode the extend type and shift amount for an
-///                     arithmetic instruction:
-///   imm:     3-bit extend amount
-///   {5-3}  = shifter
-///   {2-0}  = imm3
-static inline unsigned
-AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm)
-{
-	return (AArch64_AM_getExtendEncoding(ET) << 3) | (Imm & 0x7);
-}
-
-/// getMemDoShift - Extract the "do shift" flag value for load/store
-/// instructions.
-static inline bool AArch64_AM_getMemDoShift(unsigned Imm)
-{
-	return (Imm & 0x1) != 0;
-}
-
-/// getExtendType - Extract the extend type for the offset operand of
-/// loads/stores.
-static inline AArch64_AM_ShiftExtendType
-AArch64_AM_getMemExtendType(unsigned Imm)
-{
-	return AArch64_AM_getExtendType((Imm >> 1) & 0x7);
-}
-
-/// getExtendImm - Encode the extend type and amount for a load/store inst:
-///   doshift:     should the offset be scaled by the access size
-///   shifter: 000 ==> uxtb
-///            001 ==> uxth
-///            010 ==> uxtw
-///            011 ==> uxtx
-///            100 ==> sxtb
-///            101 ==> sxth
-///            110 ==> sxtw
-///            111 ==> sxtx
-///   {3-1}  = shifter
-///   {0}  = doshift
-static inline unsigned AArch64_AM_getMemExtendImm(AArch64_AM_ShiftExtendType ET,
-						  bool DoShift)
-{
-	return (AArch64_AM_getExtendEncoding(ET) << 1) | (unsigned)DoShift;
-}
-
-static inline uint64_t AArch64_AM_ror(uint64_t elt, unsigned size)
-{
-	return ((elt & 1) << (size - 1)) | (elt >> 1);
-}
-
-/// processLogicalImmediate - Determine if an immediate value can be encoded
-/// as the immediate operand of a logical instruction for the given register
-/// size.  If so, return true with "encoding" set to the encoded value in
-/// the form N:immr:imms.
-static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm,
-						      unsigned RegSize,
-						      uint64_t *Encoding)
-{
-	if (Imm == 0ULL || Imm == ~0ULL ||
-	    (RegSize != 64 &&
-	     (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize)))))
-		return false;
-
-	// First, determine the element size.
-	unsigned Size = RegSize;
-
-	do {
-		Size /= 2;
-		uint64_t Mask = (1ULL << Size) - 1;
-
-		if ((Imm & Mask) != ((Imm >> Size) & Mask)) {
-			Size *= 2;
-			break;
-		}
-	} while (Size > 2);
-
-	// Second, determine the rotation to make the element be: 0^m 1^n.
-	uint32_t CTO, I;
-	uint64_t Mask = ((uint64_t)-1LL) >> (64 - Size);
-	Imm &= Mask;
-
-	if (isShiftedMask_64(Imm)) {
-		I = CountTrailingZeros_64(Imm);
-
-		CTO = CountTrailingOnes_64(Imm >> I);
-	} else {
-		Imm |= ~Mask;
-		if (!isShiftedMask_64(~Imm))
-			return false;
-
-		unsigned CLO = CountLeadingOnes_64(Imm);
-		I = 64 - CLO;
-		CTO = CLO + CountTrailingOnes_64(Imm) - (64 - Size);
-	}
-
-	// Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
-	// to our target value, where I is the number of RORs to go the opposite
-	// direction.
-
-	unsigned Immr = (Size - I) & (Size - 1);
-
-	// If size has a 1 in the n'th bit, create a value that has zeroes in
-	// bits [0, n] and ones above that.
-	uint64_t NImms = ~(Size - 1) << 1;
-
-	// Or the CTO value into the low bits, which must be below the Nth bit
-	// bit mentioned above.
-	NImms |= (CTO - 1);
-
-	// Extract the seventh bit and toggle it to create the N field.
-	unsigned N = ((NImms >> 6) & 1) ^ 1;
-
-	*Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f);
-	return true;
-}
-
-/// isLogicalImmediate - Return true if the immediate is valid for a logical
-/// immediate instruction of the given register size. Return false otherwise.
-static inline bool AArch64_AM_isLogicalImmediate(uint64_t imm, unsigned regSize)
-{
-	uint64_t encoding = 0;
-	return AArch64_AM_processLogicalImmediate(imm, regSize, &encoding);
-}
-
-/// encodeLogicalImmediate - Return the encoded immediate value for a logical
-/// immediate instruction of the given register size.
-static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm,
-							 unsigned regSize)
-{
-	uint64_t encoding = 0;
-	bool res = AArch64_AM_processLogicalImmediate(imm, regSize, &encoding);
-
-	(void)res;
-	return encoding;
-}
-
-/// decodeLogicalImmediate - Decode a logical immediate value in the form
-/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
-/// integer value it represents with regSize bits.
-static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val,
-							 unsigned regSize)
-{
-	// Extract the N, imms, and immr fields.
-	unsigned N = (val >> 12) & 1;
-	unsigned immr = (val >> 6) & 0x3f;
-	unsigned imms = val & 0x3f;
-
-	int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
-	assert(len >= 1);
-
-	unsigned size = (1 << len);
-	unsigned R = immr & (size - 1);
-	unsigned S = imms & (size - 1);
-
-	uint64_t pattern = (1ULL << (S + 1)) - 1;
-	for (unsigned i = 0; i < R; ++i)
-		pattern = AArch64_AM_ror(pattern, size);
-
-	// Replicate the pattern to fill the regSize.
-	while (size != regSize) {
-		pattern |= (pattern << size);
-		size *= 2;
-	}
-	return pattern;
-}
-
-/// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
-/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
-/// is a valid encoding for an integer value with regSize bits.
-static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val,
-							    unsigned regSize)
-{
-	// Extract the N and imms fields needed for checking.
-	unsigned N = (val >> 12) & 1;
-	unsigned imms = val & 0x3f;
-
-	if (regSize == 32 && N != 0) // undefined logical immediate encoding
-		return false;
-	int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
-	if (len < 0)		     // undefined logical immediate encoding
-		return false;
-	unsigned size = (1 << len);
-	unsigned S = imms & (size - 1);
-	if (S == size - 1) // undefined logical immediate encoding
-		return false;
-
-	return true;
-}
-
-//===----------------------------------------------------------------------===//
-// Floating-point Immediates
-//
-static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
-{
-	// We expect an 8-bit binary encoding of a floating-point number here.
-
-	uint8_t Sign = (Imm >> 7) & 0x1;
-	uint8_t Exp = (Imm >> 4) & 0x7;
-	uint8_t Mantissa = Imm & 0xf;
-
-	//   8-bit FP    IEEE Float Encoding
-	//   abcd efgh   aBbbbbbc defgh000 00000000 00000000
-	//
-	// where B = NOT(b);
-
-	uint32_t I = 0;
-	I |= Sign << 31;
-	I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
-	I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
-	I |= (Exp & 0x3) << 23;
-	I |= Mantissa << 19;
-	return BitsToFloat(I);
-}
-
-//===--------------------------------------------------------------------===//
-// AdvSIMD Modified Immediates
-//===--------------------------------------------------------------------===//
-// 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh
-static inline bool AArch64_AM_isAdvSIMDModImmType1(uint64_t Imm)
-{
-	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
-	       ((Imm & 0xffffff00ffffff00ULL) == 0);
-}
-
-static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm)
-{
-	return (Imm & 0xffULL);
-}
-
-static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm)
-{
-	uint64_t EncVal = Imm;
-	return (EncVal << 32) | EncVal;
-}
-
-// 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00
-static inline bool AArch64_AM_isAdvSIMDModImmType2(uint64_t Imm)
-{
-	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
-	       ((Imm & 0xffff00ffffff00ffULL) == 0);
-}
-
-static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType2(uint64_t Imm)
-{
-	return (Imm & 0xff00ULL) >> 8;
-}
-
-static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType2(uint8_t Imm)
-{
-	uint64_t EncVal = Imm;
-	return (EncVal << 40) | (EncVal << 8);
-}
-
-// 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00
-static inline bool AArch64_AM_isAdvSIMDModImmType3(uint64_t Imm)
-{
-	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
-	       ((Imm & 0xff00ffffff00ffffULL) == 0);
-}
-
-static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType3(uint64_t Imm)
-{
-	return (Imm & 0xff0000ULL) >> 16;
-}
-
-static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType3(uint8_t Imm)
-{
-	uint64_t EncVal = Imm;
-	return (EncVal << 48) | (EncVal << 16);
-}
-
-// abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00
-static inline bool AArch64_AM_isAdvSIMDModImmType4(uint64_t Imm)
-{
-	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
-	       ((Imm & 0x00ffffff00ffffffULL) == 0);
-}
-
-static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType4(uint64_t Imm)
-{
-	return (Imm & 0xff000000ULL) >> 24;
-}
-
-static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType4(uint8_t Imm)
-{
-	uint64_t EncVal = Imm;
-	return (EncVal << 56) | (EncVal << 24);
-}
-
-// 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh
-static inline bool AArch64_AM_isAdvSIMDModImmType5(uint64_t Imm)
-{
-	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
-	       (((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
-	       ((Imm & 0xff00ff00ff00ff00ULL) == 0);
-}
-
-static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType5(uint64_t Imm)
-{
-	return (Imm & 0xffULL);
-}
-
-static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType5(uint8_t Imm)
-{
-	uint64_t EncVal = Imm;
-	return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal;
-}
-
-// abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00
-static inline bool AArch64_AM_isAdvSIMDModImmType6(uint64_t Imm)
-{
-	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
-	       (((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
-	       ((Imm & 0x00ff00ff00ff00ffULL) == 0);
-}
-
-static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType6(uint64_t Imm)
-{
-	return (Imm & 0xff00ULL) >> 8;
-}
-
-static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType6(uint8_t Imm)
-{
-	uint64_t EncVal = Imm;
-	return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8);
-}
-
-// 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF
-static inline bool AArch64_AM_isAdvSIMDModImmType7(uint64_t Imm)
-{
-	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
-	       ((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
-}
-
-static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType7(uint64_t Imm)
-{
-	return (Imm & 0xff00ULL) >> 8;
-}
-
-static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType7(uint8_t Imm)
-{
-	uint64_t EncVal = Imm;
-	return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL;
-}
-
-// 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF
-static inline bool AArch64_AM_isAdvSIMDModImmType8(uint64_t Imm)
-{
-	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
-	       ((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
-}
-
-static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType8(uint8_t Imm)
-{
-	uint64_t EncVal = Imm;
-	return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL;
-}
-
-static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType8(uint64_t Imm)
-{
-	return (Imm & 0x00ff0000ULL) >> 16;
-}
-
-// abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh
-static inline bool AArch64_AM_isAdvSIMDModImmType9(uint64_t Imm)
-{
-	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
-	       ((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
-	       ((Imm >> 56) == (Imm & 0x000000ffULL));
-}
-
-static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType9(uint64_t Imm)
-{
-	return (Imm & 0xffULL);
-}
-
-static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType9(uint8_t Imm)
-{
-	uint64_t EncVal = Imm;
-	EncVal |= (EncVal << 8);
-	EncVal |= (EncVal << 16);
-	EncVal |= (EncVal << 32);
-	return EncVal;
-}
-
-// aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
-// cmode: 1110, op: 1
-static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm)
-{
-#if defined(_MSC_VER) && _MSC_VER == 1937 && !defined(__clang__) && \
-	defined(_M_ARM64)
-	// The MSVC compiler 19.37 for ARM64 has an optimization bug that
-	// causes an incorrect behavior with the orignal version. Work around
-	// by using a slightly different variation.
-	// https://developercommunity.visualstudio.com/t/C-ARM64-compiler-optimization-bug/10481261
-	constexpr uint64_t Mask = 0xFFULL;
-	uint64_t ByteA = (Imm >> 56) & Mask;
-	uint64_t ByteB = (Imm >> 48) & Mask;
-	uint64_t ByteC = (Imm >> 40) & Mask;
-	uint64_t ByteD = (Imm >> 32) & Mask;
-	uint64_t ByteE = (Imm >> 24) & Mask;
-	uint64_t ByteF = (Imm >> 16) & Mask;
-	uint64_t ByteG = (Imm >> 8) & Mask;
-	uint64_t ByteH = Imm & Mask;
-
-	return (ByteA == 0ULL || ByteA == Mask) &&
-	       (ByteB == 0ULL || ByteB == Mask) &&
-	       (ByteC == 0ULL || ByteC == Mask) &&
-	       (ByteD == 0ULL || ByteD == Mask) &&
-	       (ByteE == 0ULL || ByteE == Mask) &&
-	       (ByteF == 0ULL || ByteF == Mask) &&
-	       (ByteG == 0ULL || ByteG == Mask) &&
-	       (ByteH == 0ULL || ByteH == Mask);
-#else
-	uint64_t ByteA = Imm & 0xff00000000000000ULL;
-	uint64_t ByteB = Imm & 0x00ff000000000000ULL;
-	uint64_t ByteC = Imm & 0x0000ff0000000000ULL;
-	uint64_t ByteD = Imm & 0x000000ff00000000ULL;
-	uint64_t ByteE = Imm & 0x00000000ff000000ULL;
-	uint64_t ByteF = Imm & 0x0000000000ff0000ULL;
-	uint64_t ByteG = Imm & 0x000000000000ff00ULL;
-	uint64_t ByteH = Imm & 0x00000000000000ffULL;
-
-	return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&
-	       (ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
-	       (ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
-	       (ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
-	       (ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
-	       (ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
-	       (ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
-	       (ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
-#endif
-}
-
-static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm)
-{
-	uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0;
-	uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0;
-	uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0;
-	uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0;
-	uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0;
-	uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0;
-	uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0;
-	uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0;
-
-	uint8_t EncVal = BitA;
-	EncVal <<= 1;
-	EncVal |= BitB;
-	EncVal <<= 1;
-	EncVal |= BitC;
-	EncVal <<= 1;
-	EncVal |= BitD;
-	EncVal <<= 1;
-	EncVal |= BitE;
-	EncVal <<= 1;
-	EncVal |= BitF;
-	EncVal <<= 1;
-	EncVal |= BitG;
-	EncVal <<= 1;
-	EncVal |= BitH;
-	return EncVal;
-}
-
-static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm)
-{
-	uint64_t EncVal = 0;
-	if (Imm & 0x80)
-		EncVal |= 0xff00000000000000ULL;
-	if (Imm & 0x40)
-		EncVal |= 0x00ff000000000000ULL;
-	if (Imm & 0x20)
-		EncVal |= 0x0000ff0000000000ULL;
-	if (Imm & 0x10)
-		EncVal |= 0x000000ff00000000ULL;
-	if (Imm & 0x08)
-		EncVal |= 0x00000000ff000000ULL;
-	if (Imm & 0x04)
-		EncVal |= 0x0000000000ff0000ULL;
-	if (Imm & 0x02)
-		EncVal |= 0x000000000000ff00ULL;
-	if (Imm & 0x01)
-		EncVal |= 0x00000000000000ffULL;
-	return EncVal;
-}
-
-// aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00
-static inline bool AArch64_AM_isAdvSIMDModImmType11(uint64_t Imm)
-{
-	uint64_t BString = (Imm & 0x7E000000ULL) >> 25;
-	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
-	       (BString == 0x1f || BString == 0x20) &&
-	       ((Imm & 0x0007ffff0007ffffULL) == 0);
-}
-
-static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm)
-{
-	uint8_t BitA = (Imm & 0x80000000ULL) != 0;
-	uint8_t BitB = (Imm & 0x20000000ULL) != 0;
-	uint8_t BitC = (Imm & 0x01000000ULL) != 0;
-	uint8_t BitD = (Imm & 0x00800000ULL) != 0;
-	uint8_t BitE = (Imm & 0x00400000ULL) != 0;
-	uint8_t BitF = (Imm & 0x00200000ULL) != 0;
-	uint8_t BitG = (Imm & 0x00100000ULL) != 0;
-	uint8_t BitH = (Imm & 0x00080000ULL) != 0;
-
-	uint8_t EncVal = BitA;
-	EncVal <<= 1;
-	EncVal |= BitB;
-	EncVal <<= 1;
-	EncVal |= BitC;
-	EncVal <<= 1;
-	EncVal |= BitD;
-	EncVal <<= 1;
-	EncVal |= BitE;
-	EncVal <<= 1;
-	EncVal |= BitF;
-	EncVal <<= 1;
-	EncVal |= BitG;
-	EncVal <<= 1;
-	EncVal |= BitH;
-	return EncVal;
-}
-
-static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType11(uint8_t Imm)
-{
-	uint64_t EncVal = 0;
-	if (Imm & 0x80)
-		EncVal |= 0x80000000ULL;
-	if (Imm & 0x40)
-		EncVal |= 0x3e000000ULL;
-	else
-		EncVal |= 0x40000000ULL;
-	if (Imm & 0x20)
-		EncVal |= 0x01000000ULL;
-	if (Imm & 0x10)
-		EncVal |= 0x00800000ULL;
-	if (Imm & 0x08)
-		EncVal |= 0x00400000ULL;
-	if (Imm & 0x04)
-		EncVal |= 0x00200000ULL;
-	if (Imm & 0x02)
-		EncVal |= 0x00100000ULL;
-	if (Imm & 0x01)
-		EncVal |= 0x00080000ULL;
-	return (EncVal << 32) | EncVal;
-}
-
-// aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00
-static inline bool AArch64_AM_isAdvSIMDModImmType12(uint64_t Imm)
-{
-	uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54;
-	return ((BString == 0xff || BString == 0x100) &&
-		((Imm & 0x0000ffffffffffffULL) == 0));
-}
-
-static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm)
-{
-	uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0;
-	uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0;
-	uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0;
-	uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0;
-	uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0;
-	uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0;
-	uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0;
-	uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0;
-
-	uint8_t EncVal = BitA;
-	EncVal <<= 1;
-	EncVal |= BitB;
-	EncVal <<= 1;
-	EncVal |= BitC;
-	EncVal <<= 1;
-	EncVal |= BitD;
-	EncVal <<= 1;
-	EncVal |= BitE;
-	EncVal <<= 1;
-	EncVal |= BitF;
-	EncVal <<= 1;
-	EncVal |= BitG;
-	EncVal <<= 1;
-	EncVal |= BitH;
-	return EncVal;
-}
-
-static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType12(uint8_t Imm)
-{
-	uint64_t EncVal = 0;
-	if (Imm & 0x80)
-		EncVal |= 0x8000000000000000ULL;
-	if (Imm & 0x40)
-		EncVal |= 0x3fc0000000000000ULL;
-	else
-		EncVal |= 0x4000000000000000ULL;
-	if (Imm & 0x20)
-		EncVal |= 0x0020000000000000ULL;
-	if (Imm & 0x10)
-		EncVal |= 0x0010000000000000ULL;
-	if (Imm & 0x08)
-		EncVal |= 0x0008000000000000ULL;
-	if (Imm & 0x04)
-		EncVal |= 0x0004000000000000ULL;
-	if (Imm & 0x02)
-		EncVal |= 0x0002000000000000ULL;
-	if (Imm & 0x01)
-		EncVal |= 0x0001000000000000ULL;
-	return (EncVal << 32) | EncVal;
-}
-
-/// Returns true if Imm is the concatenation of a repeating pattern of type T.
-#define DEFINE_isSVEMaskOfIdenticalElements(T) \
-	static inline bool CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, \
-				  T)(int64_t Imm) \
-	{ \
-		union { \
-			int64_t In; \
-			T Out[sizeof(int64_t) / sizeof(T)]; \
-		} U_Parts; \
-		U_Parts.In = Imm; \
-		T *Parts = U_Parts.Out; \
-		for (int i = 0; i < (sizeof(int64_t) / sizeof(T)); i++) { \
-			if (Parts[i] != Parts[0]) \
-				return false; \
-		} \
-		return true; \
-	}
-DEFINE_isSVEMaskOfIdenticalElements(int8_t);
-DEFINE_isSVEMaskOfIdenticalElements(int16_t);
-DEFINE_isSVEMaskOfIdenticalElements(int32_t);
-DEFINE_isSVEMaskOfIdenticalElements(int64_t);
-
-static inline bool isSVECpyImm8(int64_t Imm)
-{
-	bool IsImm8 = (int8_t)Imm == Imm;
-
-	return IsImm8 || (uint8_t)Imm == Imm;
-}
-
-static inline bool isSVECpyImm16(int64_t Imm)
-{
-	bool IsImm8 = (int8_t)Imm == Imm;
-	bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm;
-
-	return IsImm8 || IsImm16 || (uint16_t)(Imm & ~0xff) == Imm;
-}
-
-static inline bool isSVECpyImm32(int64_t Imm)
-{
-	bool IsImm8 = (int8_t)Imm == Imm;
-	bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm;
-
-	return IsImm8 || IsImm16;
-}
-
-static inline bool isSVECpyImm64(int64_t Imm)
-{
-	bool IsImm8 = (int8_t)Imm == Imm;
-	bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm;
-
-	return IsImm8 || IsImm16;
-}
-
-/// Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent.
-static inline bool
-AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm)
-{
-	if (isSVECpyImm64(Imm))
-		return false;
-
-	union {
-		int64_t In;
-		int32_t Out[2];
-	} U_S;
-	U_S.In = Imm;
-	int32_t *S = U_S.Out;
-	union {
-		int64_t In;
-		int16_t Out[4];
-	} U_H;
-	U_H.In = Imm;
-	int16_t *H = U_H.Out;
-	union {
-		int64_t In;
-		int8_t Out[8];
-	} U_B;
-	U_B.In = Imm;
-	int8_t *B = U_B.Out;
-
-	if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int32_t)(Imm) &&
-	    isSVECpyImm32(S[0]))
-		return false;
-	if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int16_t)(Imm) &&
-	    isSVECpyImm16(H[0]))
-		return false;
-	if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int8_t)(Imm) &&
-	    isSVECpyImm8(B[0]))
-		return false;
-	return AArch64_AM_isLogicalImmediate(Imm, 64);
-}
-
-inline static bool AArch64_AM_isAnyMOVZMovAlias(uint64_t Value, int RegWidth)
-{
-	for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16)
-		if ((Value & ~(0xffffULL << Shift)) == 0)
-			return true;
-
-	return false;
-}
-
-inline static bool AArch64_AM_isMOVZMovAlias(uint64_t Value, int Shift,
-					     int RegWidth)
-{
-	if (RegWidth == 32)
-		Value &= 0xffffffffULL;
-
-	// "lsl #0" takes precedence: in practice this only affects "#0, lsl #0".
-	if (Value == 0 && Shift != 0)
-		return false;
-
-	return (Value & ~(0xffffULL << Shift)) == 0;
-}
-
-inline static bool AArch64_AM_isMOVNMovAlias(uint64_t Value, int Shift,
-					     int RegWidth)
-{
-	// MOVZ takes precedence over MOVN.
-	if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth))
-		return false;
-
-	Value = ~Value;
-	if (RegWidth == 32)
-		Value &= 0xffffffffULL;
-
-	return AArch64_AM_isMOVZMovAlias(Value, Shift, RegWidth);
-}
-
-inline static bool AArch64_AM_isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
-{
-	if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth))
-		return true;
-
-	// It's not a MOVZ, but it might be a MOVN.
-	Value = ~Value;
-	if (RegWidth == 32)
-		Value &= 0xffffffffULL;
-
-	return AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth);
-}
-
-// CS namespace end: AArch64_AM
-
-// end namespace AArch64_AM
-
-// end namespace llvm
-
-#endif

thirdparty/capstone/arch/AArch64/AArch64BaseInfo.c

@@ -1,175 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
-/* Automatically translated source file from LLVM. */
-
-/* LLVM-commit: <commit> */
-/* LLVM-tag: <tag> */
-
-/* Only small edits allowed. */
-/* For multiple similar edits, please create a Patch for the translator. */
-
-/* Capstone's C++ file translator: */
-/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
-
-//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides basic encoding and assembly information for AArch64.
-//
-//===----------------------------------------------------------------------===//
-#include <capstone/platform.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "AArch64BaseInfo.h"
-
-#define CONCAT(a, b) CONCAT_(a, b)
-#define CONCAT_(a, b) a##_##b
-
-#define GET_AT_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_AT_IMPL
-
-#define GET_DBNXS_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_DBNXS_IMPL
-
-#define GET_DB_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_DB_IMPL
-
-#define GET_DC_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_DC_IMPL
-
-#define GET_IC_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_IC_IMPL
-
-#define GET_ISB_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_ISB_IMPL
-
-#define GET_TSB_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_TSB_IMPL
-
-#define GET_PRCTX_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_PRCTX_IMPL
-
-#define GET_PRFM_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_PRFM_IMPL
-
-#define GET_SVEPRFM_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_SVEPRFM_IMPL
-
-#define GET_RPRFM_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_RPRFM_IMPL
-
-// namespace AArch64RPRFM
-// namespace llvm
-
-#define GET_SVEPREDPAT_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_SVEPREDPAT_IMPL
-
-#define GET_SVEVECLENSPECIFIER_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_SVEVECLENSPECIFIER_IMPL
-
-// namespace AArch64SVEVecLenSpecifier
-// namespace llvm
-
-#define GET_EXACTFPIMM_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_EXACTFPIMM_IMPL
-
-#define GET_PSTATEIMM0_15_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_PSTATEIMM0_15_IMPL
-
-#define GET_PSTATEIMM0_1_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_PSTATEIMM0_1_IMPL
-
-#define GET_PSB_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_PSB_IMPL
-
-#define GET_BTI_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_BTI_IMPL
-
-#define SysReg AArch64SysReg_SysReg
-#define GET_SYSREG_IMPL
-#include "AArch64GenSystemOperands.inc"
-#undef GET_SYSREG_IMPL
-
-#undef SysReg
-
-// return a string representing the number X
-// NOTE: result must be big enough to contain the data
-static void utostr(uint64_t X, bool isNeg, char *result)
-{
-	char Buffer[22];
-	char *BufPtr = Buffer + 21;
-
-	Buffer[21] = '\0';
-	if (X == 0)
-		*--BufPtr = '0'; // Handle special case...
-
-	while (X) {
-		*--BufPtr = X % 10 + '0';
-		X /= 10;
-	}
-
-	if (isNeg)
-		*--BufPtr = '-'; // Add negative sign...
-
-	// suppose that result is big enough
-	strncpy(result, BufPtr, sizeof(Buffer));
-}
-
-// NOTE: result must be big enough to contain the result
-void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result)
-{
-	// assert(Bits < 0x10000);
-	char Op0Str[32], Op1Str[32], CRnStr[32], CRmStr[32], Op2Str[32];
-	int dummy;
-	uint32_t Op0 = (Bits >> 14) & 0x3;
-	uint32_t Op1 = (Bits >> 11) & 0x7;
-	uint32_t CRn = (Bits >> 7) & 0xf;
-	uint32_t CRm = (Bits >> 3) & 0xf;
-	uint32_t Op2 = Bits & 0x7;
-
-	utostr(Op0, false, Op0Str);
-	utostr(Op1, false, Op1Str);
-	utostr(Op2, false, Op2Str);
-	utostr(CRn, false, CRnStr);
-	utostr(CRm, false, CRmStr);
-
-	dummy = cs_snprintf(result, AARCH64_GRS_LEN, "s%s_%s_c%s_c%s_%s",
-			    Op0Str, Op1Str, CRnStr, CRmStr, Op2Str);
-	(void)dummy;
-}
-
-#define GET_TLBITable_IMPL
-
-#include "AArch64GenSystemOperands.inc"
-#undef GET_TLBITable_IMPL
-
-#define GET_SVCR_IMPL
-
-#include "AArch64GenSystemOperands.inc"
-#undef GET_SVCR_IMPL

thirdparty/capstone/arch/AArch64/AArch64BaseInfo.h

@@ -1,983 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
-/* Automatically translated source file from LLVM. */
-
-/* LLVM-commit: <commit> */
-/* LLVM-tag: <tag> */
-
-/* Only small edits allowed. */
-/* For multiple similar edits, please create a Patch for the translator. */
-
-/* Capstone's C++ file translator: */
-/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
-
-//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains small standalone helper functions and enum definitions for
-// the AArch64 target useful for the compiler back-end and the MC libraries.
-// As such, it deliberately does not include references to LLVM core
-// code gen types, passes, etc..
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
-#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
-
-// FIXME: Is it easiest to fix this layering violation by moving the .inc
-// #includes from AArch64MCTargetDesc.h to here?
-#include <capstone/platform.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "../../MCInstPrinter.h"
-
-#include "../../utils.h"
-#include "capstone/aarch64.h"
-
-#define GET_SUBTARGETINFO_ENUM
-#include "AArch64GenSubtargetInfo.inc"
-
-#define GET_REGINFO_ENUM
-#define GET_REGINFO_MC_DESC
-#include "AArch64GenRegisterInfo.inc"
-
-#define GET_INSTRINFO_ENUM
-#include "AArch64GenInstrInfo.inc"
-
-#define CONCAT(a, b) CONCAT_(a, b)
-#define CONCAT_(a, b) a##_##b
-
-static inline unsigned getWRegFromXReg(unsigned Reg)
-{
-	switch (Reg) {
-	case AArch64_X0:
-		return AArch64_W0;
-	case AArch64_X1:
-		return AArch64_W1;
-	case AArch64_X2:
-		return AArch64_W2;
-	case AArch64_X3:
-		return AArch64_W3;
-	case AArch64_X4:
-		return AArch64_W4;
-	case AArch64_X5:
-		return AArch64_W5;
-	case AArch64_X6:
-		return AArch64_W6;
-	case AArch64_X7:
-		return AArch64_W7;
-	case AArch64_X8:
-		return AArch64_W8;
-	case AArch64_X9:
-		return AArch64_W9;
-	case AArch64_X10:
-		return AArch64_W10;
-	case AArch64_X11:
-		return AArch64_W11;
-	case AArch64_X12:
-		return AArch64_W12;
-	case AArch64_X13:
-		return AArch64_W13;
-	case AArch64_X14:
-		return AArch64_W14;
-	case AArch64_X15:
-		return AArch64_W15;
-	case AArch64_X16:
-		return AArch64_W16;
-	case AArch64_X17:
-		return AArch64_W17;
-	case AArch64_X18:
-		return AArch64_W18;
-	case AArch64_X19:
-		return AArch64_W19;
-	case AArch64_X20:
-		return AArch64_W20;
-	case AArch64_X21:
-		return AArch64_W21;
-	case AArch64_X22:
-		return AArch64_W22;
-	case AArch64_X23:
-		return AArch64_W23;
-	case AArch64_X24:
-		return AArch64_W24;
-	case AArch64_X25:
-		return AArch64_W25;
-	case AArch64_X26:
-		return AArch64_W26;
-	case AArch64_X27:
-		return AArch64_W27;
-	case AArch64_X28:
-		return AArch64_W28;
-	case AArch64_FP:
-		return AArch64_W29;
-	case AArch64_LR:
-		return AArch64_W30;
-	case AArch64_SP:
-		return AArch64_WSP;
-	case AArch64_XZR:
-		return AArch64_WZR;
-	}
-	// For anything else, return it unchanged.
-	return Reg;
-}
-
-static inline unsigned getXRegFromWReg(unsigned Reg)
-{
-	switch (Reg) {
-	case AArch64_W0:
-		return AArch64_X0;
-	case AArch64_W1:
-		return AArch64_X1;
-	case AArch64_W2:
-		return AArch64_X2;
-	case AArch64_W3:
-		return AArch64_X3;
-	case AArch64_W4:
-		return AArch64_X4;
-	case AArch64_W5:
-		return AArch64_X5;
-	case AArch64_W6:
-		return AArch64_X6;
-	case AArch64_W7:
-		return AArch64_X7;
-	case AArch64_W8:
-		return AArch64_X8;
-	case AArch64_W9:
-		return AArch64_X9;
-	case AArch64_W10:
-		return AArch64_X10;
-	case AArch64_W11:
-		return AArch64_X11;
-	case AArch64_W12:
-		return AArch64_X12;
-	case AArch64_W13:
-		return AArch64_X13;
-	case AArch64_W14:
-		return AArch64_X14;
-	case AArch64_W15:
-		return AArch64_X15;
-	case AArch64_W16:
-		return AArch64_X16;
-	case AArch64_W17:
-		return AArch64_X17;
-	case AArch64_W18:
-		return AArch64_X18;
-	case AArch64_W19:
-		return AArch64_X19;
-	case AArch64_W20:
-		return AArch64_X20;
-	case AArch64_W21:
-		return AArch64_X21;
-	case AArch64_W22:
-		return AArch64_X22;
-	case AArch64_W23:
-		return AArch64_X23;
-	case AArch64_W24:
-		return AArch64_X24;
-	case AArch64_W25:
-		return AArch64_X25;
-	case AArch64_W26:
-		return AArch64_X26;
-	case AArch64_W27:
-		return AArch64_X27;
-	case AArch64_W28:
-		return AArch64_X28;
-	case AArch64_W29:
-		return AArch64_FP;
-	case AArch64_W30:
-		return AArch64_LR;
-	case AArch64_WSP:
-		return AArch64_SP;
-	case AArch64_WZR:
-		return AArch64_XZR;
-	}
-	// For anything else, return it unchanged.
-	return Reg;
-}
-
-static inline unsigned getXRegFromXRegTuple(unsigned RegTuple)
-{
-	switch (RegTuple) {
-	case AArch64_X0_X1_X2_X3_X4_X5_X6_X7:
-		return AArch64_X0;
-	case AArch64_X2_X3_X4_X5_X6_X7_X8_X9:
-		return AArch64_X2;
-	case AArch64_X4_X5_X6_X7_X8_X9_X10_X11:
-		return AArch64_X4;
-	case AArch64_X6_X7_X8_X9_X10_X11_X12_X13:
-		return AArch64_X6;
-	case AArch64_X8_X9_X10_X11_X12_X13_X14_X15:
-		return AArch64_X8;
-	case AArch64_X10_X11_X12_X13_X14_X15_X16_X17:
-		return AArch64_X10;
-	case AArch64_X12_X13_X14_X15_X16_X17_X18_X19:
-		return AArch64_X12;
-	case AArch64_X14_X15_X16_X17_X18_X19_X20_X21:
-		return AArch64_X14;
-	case AArch64_X16_X17_X18_X19_X20_X21_X22_X23:
-		return AArch64_X16;
-	case AArch64_X18_X19_X20_X21_X22_X23_X24_X25:
-		return AArch64_X18;
-	case AArch64_X20_X21_X22_X23_X24_X25_X26_X27:
-		return AArch64_X20;
-	case AArch64_X22_X23_X24_X25_X26_X27_X28_FP:
-		return AArch64_X22;
-	}
-	// For anything else, return it unchanged.
-	return RegTuple;
-}
-
-static inline unsigned getBRegFromDReg(unsigned Reg)
-{
-	switch (Reg) {
-	case AArch64_D0:
-		return AArch64_B0;
-	case AArch64_D1:
-		return AArch64_B1;
-	case AArch64_D2:
-		return AArch64_B2;
-	case AArch64_D3:
-		return AArch64_B3;
-	case AArch64_D4:
-		return AArch64_B4;
-	case AArch64_D5:
-		return AArch64_B5;
-	case AArch64_D6:
-		return AArch64_B6;
-	case AArch64_D7:
-		return AArch64_B7;
-	case AArch64_D8:
-		return AArch64_B8;
-	case AArch64_D9:
-		return AArch64_B9;
-	case AArch64_D10:
-		return AArch64_B10;
-	case AArch64_D11:
-		return AArch64_B11;
-	case AArch64_D12:
-		return AArch64_B12;
-	case AArch64_D13:
-		return AArch64_B13;
-	case AArch64_D14:
-		return AArch64_B14;
-	case AArch64_D15:
-		return AArch64_B15;
-	case AArch64_D16:
-		return AArch64_B16;
-	case AArch64_D17:
-		return AArch64_B17;
-	case AArch64_D18:
-		return AArch64_B18;
-	case AArch64_D19:
-		return AArch64_B19;
-	case AArch64_D20:
-		return AArch64_B20;
-	case AArch64_D21:
-		return AArch64_B21;
-	case AArch64_D22:
-		return AArch64_B22;
-	case AArch64_D23:
-		return AArch64_B23;
-	case AArch64_D24:
-		return AArch64_B24;
-	case AArch64_D25:
-		return AArch64_B25;
-	case AArch64_D26:
-		return AArch64_B26;
-	case AArch64_D27:
-		return AArch64_B27;
-	case AArch64_D28:
-		return AArch64_B28;
-	case AArch64_D29:
-		return AArch64_B29;
-	case AArch64_D30:
-		return AArch64_B30;
-	case AArch64_D31:
-		return AArch64_B31;
-	}
-	// For anything else, return it unchanged.
-	return Reg;
-}
-
-static inline unsigned getDRegFromBReg(unsigned Reg)
-{
-	switch (Reg) {
-	case AArch64_B0:
-		return AArch64_D0;
-	case AArch64_B1:
-		return AArch64_D1;
-	case AArch64_B2:
-		return AArch64_D2;
-	case AArch64_B3:
-		return AArch64_D3;
-	case AArch64_B4:
-		return AArch64_D4;
-	case AArch64_B5:
-		return AArch64_D5;
-	case AArch64_B6:
-		return AArch64_D6;
-	case AArch64_B7:
-		return AArch64_D7;
-	case AArch64_B8:
-		return AArch64_D8;
-	case AArch64_B9:
-		return AArch64_D9;
-	case AArch64_B10:
-		return AArch64_D10;
-	case AArch64_B11:
-		return AArch64_D11;
-	case AArch64_B12:
-		return AArch64_D12;
-	case AArch64_B13:
-		return AArch64_D13;
-	case AArch64_B14:
-		return AArch64_D14;
-	case AArch64_B15:
-		return AArch64_D15;
-	case AArch64_B16:
-		return AArch64_D16;
-	case AArch64_B17:
-		return AArch64_D17;
-	case AArch64_B18:
-		return AArch64_D18;
-	case AArch64_B19:
-		return AArch64_D19;
-	case AArch64_B20:
-		return AArch64_D20;
-	case AArch64_B21:
-		return AArch64_D21;
-	case AArch64_B22:
-		return AArch64_D22;
-	case AArch64_B23:
-		return AArch64_D23;
-	case AArch64_B24:
-		return AArch64_D24;
-	case AArch64_B25:
-		return AArch64_D25;
-	case AArch64_B26:
-		return AArch64_D26;
-	case AArch64_B27:
-		return AArch64_D27;
-	case AArch64_B28:
-		return AArch64_D28;
-	case AArch64_B29:
-		return AArch64_D29;
-	case AArch64_B30:
-		return AArch64_D30;
-	case AArch64_B31:
-		return AArch64_D31;
-	}
-	// For anything else, return it unchanged.
-	return Reg;
-}
-
-static inline bool atomicBarrierDroppedOnZero(unsigned Opcode)
-{
-	switch (Opcode) {
-	case AArch64_LDADDAB:
-	case AArch64_LDADDAH:
-	case AArch64_LDADDAW:
-	case AArch64_LDADDAX:
-	case AArch64_LDADDALB:
-	case AArch64_LDADDALH:
-	case AArch64_LDADDALW:
-	case AArch64_LDADDALX:
-	case AArch64_LDCLRAB:
-	case AArch64_LDCLRAH:
-	case AArch64_LDCLRAW:
-	case AArch64_LDCLRAX:
-	case AArch64_LDCLRALB:
-	case AArch64_LDCLRALH:
-	case AArch64_LDCLRALW:
-	case AArch64_LDCLRALX:
-	case AArch64_LDEORAB:
-	case AArch64_LDEORAH:
-	case AArch64_LDEORAW:
-	case AArch64_LDEORAX:
-	case AArch64_LDEORALB:
-	case AArch64_LDEORALH:
-	case AArch64_LDEORALW:
-	case AArch64_LDEORALX:
-	case AArch64_LDSETAB:
-	case AArch64_LDSETAH:
-	case AArch64_LDSETAW:
-	case AArch64_LDSETAX:
-	case AArch64_LDSETALB:
-	case AArch64_LDSETALH:
-	case AArch64_LDSETALW:
-	case AArch64_LDSETALX:
-	case AArch64_LDSMAXAB:
-	case AArch64_LDSMAXAH:
-	case AArch64_LDSMAXAW:
-	case AArch64_LDSMAXAX:
-	case AArch64_LDSMAXALB:
-	case AArch64_LDSMAXALH:
-	case AArch64_LDSMAXALW:
-	case AArch64_LDSMAXALX:
-	case AArch64_LDSMINAB:
-	case AArch64_LDSMINAH:
-	case AArch64_LDSMINAW:
-	case AArch64_LDSMINAX:
-	case AArch64_LDSMINALB:
-	case AArch64_LDSMINALH:
-	case AArch64_LDSMINALW:
-	case AArch64_LDSMINALX:
-	case AArch64_LDUMAXAB:
-	case AArch64_LDUMAXAH:
-	case AArch64_LDUMAXAW:
-	case AArch64_LDUMAXAX:
-	case AArch64_LDUMAXALB:
-	case AArch64_LDUMAXALH:
-	case AArch64_LDUMAXALW:
-	case AArch64_LDUMAXALX:
-	case AArch64_LDUMINAB:
-	case AArch64_LDUMINAH:
-	case AArch64_LDUMINAW:
-	case AArch64_LDUMINAX:
-	case AArch64_LDUMINALB:
-	case AArch64_LDUMINALH:
-	case AArch64_LDUMINALW:
-	case AArch64_LDUMINALX:
-	case AArch64_SWPAB:
-	case AArch64_SWPAH:
-	case AArch64_SWPAW:
-	case AArch64_SWPAX:
-	case AArch64_SWPALB:
-	case AArch64_SWPALH:
-	case AArch64_SWPALW:
-	case AArch64_SWPALX:
-		return true;
-	}
-	return false;
-}
-
-// MOVE-NOTICE: AArch64CC_CondCode : moved to aarch64.h
-// MOVE-NOTICE: AArch64CC_getCondCodeName : moved to aarch64.h
-// MOVE-NOTICE: AArch64CC_getInvertedCondCode : moved to aarch64.h
-// MOVE-NOTICE: AArch64CC_getNZCVToSatisfyCondCode : moved to aarch64.h
-
-typedef struct SysAlias {
-	const char *Name;
-	aarch64_sysop_alias SysAlias;
-	uint16_t Encoding;
-	aarch64_insn_group FeaturesRequired[3];
-} SysAlias;
-
-typedef struct SysAliasReg {
-	const char *Name;
-	aarch64_sysop_reg SysReg;
-	uint16_t Encoding;
-	bool NeedsReg;
-	aarch64_insn_group FeaturesRequired[3];
-} SysAliasReg;
-
-typedef struct SysAliasImm {
-	const char *Name;
-	aarch64_sysop_imm SysImm;
-	uint16_t ImmValue;
-	uint16_t Encoding;
-	aarch64_insn_group FeaturesRequired[3];
-} SysAliasImm;
-
-// CS namespace begin: AArch64SVCR
-
-#define AArch64SVCR_SVCR SysAlias
-
-#define GET_SVCR_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64SVCR
-
-// CS namespace begin: AArch64AT
-
-#define AArch64AT_AT SysAlias
-
-#define GET_AT_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64AT
-
-// CS namespace begin: AArch64DB
-
-#define AArch64DB_DB SysAlias
-
-#define GET_DB_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64DB
-
-// CS namespace begin: AArch64DBnXS
-
-#define AArch64DBnXS_DBnXS SysAliasImm
-
-#define GET_DBNXS_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64DBnXS
-
-// CS namespace begin: AArch64DC
-
-#define AArch64DC_DC SysAlias
-
-#define GET_DC_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64DC
-
-// CS namespace begin: AArch64IC
-
-#define AArch64IC_IC SysAliasReg
-
-#define GET_IC_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64IC
-
-// CS namespace begin: AArch64ISB
-
-#define AArch64ISB_ISB SysAlias
-
-#define GET_ISB_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64ISB
-
-// CS namespace begin: AArch64TSB
-
-#define AArch64TSB_TSB SysAlias
-
-#define GET_TSB_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64TSB
-
-// CS namespace begin: AArch64PRFM
-
-#define AArch64PRFM_PRFM SysAlias
-
-#define GET_PRFM_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64PRFM
-
-// CS namespace begin: AArch64SVEPRFM
-
-#define AArch64SVEPRFM_SVEPRFM SysAlias
-
-#define GET_SVEPRFM_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64SVEPRFM
-
-// CS namespace begin: AArch64RPRFM
-
-#define AArch64RPRFM_RPRFM SysAlias
-
-#define GET_RPRFM_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64RPRFM
-
-// CS namespace begin: AArch64SVEPredPattern
-
-typedef struct SVEPREDPAT {
-	const char *Name;
-	aarch64_sysop_alias SysAlias;
-	uint16_t Encoding;
-} AArch64SVEPredPattern_SVEPREDPAT;
-
-#define GET_SVEPREDPAT_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64SVEPredPattern
-
-// CS namespace begin: AArch64SVEVecLenSpecifier
-
-typedef struct SVEVECLENSPECIFIER {
-	const char *Name;
-	aarch64_sysop_alias SysAlias;
-	uint16_t Encoding;
-} AArch64SVEVecLenSpecifier_SVEVECLENSPECIFIER;
-
-#define GET_SVEVECLENSPECIFIER_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64SVEVecLenSpecifier
-
-// namespace AArch64SVEVecLenSpecifier
-
-/// Return the number of active elements for VL1 to VL256 predicate pattern,
-/// zero for all other patterns.
-static inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
-{
-	switch (Pattern) {
-	default:
-		return 0;
-	case AARCH64_SVEPREDPAT_VL1:
-	case AARCH64_SVEPREDPAT_VL2:
-	case AARCH64_SVEPREDPAT_VL3:
-	case AARCH64_SVEPREDPAT_VL4:
-	case AARCH64_SVEPREDPAT_VL5:
-	case AARCH64_SVEPREDPAT_VL6:
-	case AARCH64_SVEPREDPAT_VL7:
-	case AARCH64_SVEPREDPAT_VL8:
-		return Pattern;
-	case AARCH64_SVEPREDPAT_VL16:
-		return 16;
-	case AARCH64_SVEPREDPAT_VL32:
-		return 32;
-	case AARCH64_SVEPREDPAT_VL64:
-		return 64;
-	case AARCH64_SVEPREDPAT_VL128:
-		return 128;
-	case AARCH64_SVEPREDPAT_VL256:
-		return 256;
-	}
-}
-
-/// Return specific VL predicate pattern based on the number of elements.
-static inline unsigned getSVEPredPatternFromNumElements(unsigned MinNumElts)
-{
-	switch (MinNumElts) {
-	default:
-		return 0;
-	case 1:
-	case 2:
-	case 3:
-	case 4:
-	case 5:
-	case 6:
-	case 7:
-	case 8:
-		return MinNumElts;
-	case 16:
-		return AARCH64_SVEPREDPAT_VL16;
-	case 32:
-		return AARCH64_SVEPREDPAT_VL32;
-	case 64:
-		return AARCH64_SVEPREDPAT_VL64;
-	case 128:
-		return AARCH64_SVEPREDPAT_VL128;
-	case 256:
-		return AARCH64_SVEPREDPAT_VL256;
-	}
-}
-
-// CS namespace begin: AArch64ExactFPImm
-
-typedef struct ExactFPImm {
-	const char *Name;
-	aarch64_sysop_imm SysImm;
-	int Enum;
-	const char *Repr;
-} AArch64ExactFPImm_ExactFPImm;
-
-enum {
-	AArch64ExactFPImm_half = 1,
-	AArch64ExactFPImm_one = 2,
-	AArch64ExactFPImm_two = 3,
-	AArch64ExactFPImm_zero = 0,
-};
-
-#define GET_EXACTFPIMM_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64ExactFPImm
-
-// CS namespace begin: AArch64PState
-
-#define AArch64PState_PStateImm0_15 SysAlias
-
-#define GET_PSTATEIMM0_15_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-#define AArch64PState_PStateImm0_1 SysAlias
-
-#define GET_PSTATEIMM0_1_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64PState
-
-// CS namespace begin: AArch64PSBHint
-
-#define AArch64PSBHint_PSB SysAlias
-
-#define GET_PSB_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64PSBHint
-
-// CS namespace begin: AArch64BTIHint
-
-#define AArch64BTIHint_BTI SysAlias
-
-#define GET_BTI_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64BTIHint
-
-// CS namespace begin: AArch64SE
-
-typedef enum ShiftExtSpecifiers {
-	AArch64SE_Invalid = -1,
-	AArch64SE_LSL,
-	AArch64SE_MSL,
-	AArch64SE_LSR,
-	AArch64SE_ASR,
-	AArch64SE_ROR,
-
-	AArch64SE_UXTB,
-	AArch64SE_UXTH,
-	AArch64SE_UXTW,
-	AArch64SE_UXTX,
-
-	AArch64SE_SXTB,
-	AArch64SE_SXTH,
-	AArch64SE_SXTW,
-	AArch64SE_SXTX
-} AArch64SE_ShiftExtSpecifiers;
-
-// CS namespace end: AArch64SE
-
-// CS namespace begin: AArch64Layout
-
-// MOVE_NOTICE: AArch64Layout_VectorLayout - move to aarch64.h
-// MOVE_NOTICE: AArch64VectorLayoutToString - move to aarch64.h
-// MOVE_NOTICE: AArch64StringToVectorLayout - move to aarch64.h
-
-// CS namespace end: AArch64Layout
-
-// CS namespace begin: AArch64SysReg
-
-typedef struct SysReg {
-	const char *Name;
-	aarch64_sysop_reg SysReg;
-	const char *AltName;
-	aarch64_sysop_reg AliasReg;
-	unsigned Encoding;
-	bool Readable;
-	bool Writeable;
-	aarch64_insn_group FeaturesRequired[3];
-} AArch64SysReg_SysReg;
-
-#define GET_SYSREG_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-const AArch64SysReg_SysReg *AArch64SysReg_lookupSysRegByName(const char *Name);
-const AArch64SysReg_SysReg *
-AArch64SysReg_lookupSysRegByEncoding(uint16_t Encoding);
-#define AARCH64_GRS_LEN 128
-void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result);
-
-// CS namespace end: AArch64SysReg
-
-// CS namespace begin: AArch64TLBI
-
-#define AArch64TLBI_TLBI SysAliasReg
-
-#define GET_TLBITable_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64TLBI
-
-// CS namespace begin: AArch64PRCTX
-
-#define AArch64PRCTX_PRCTX SysAliasReg
-
-#define GET_PRCTX_DECL
-
-#include "AArch64GenSystemOperands.inc"
-
-// CS namespace end: AArch64PRCTX
-
-// CS namespace begin: AArch64II
-
-/// Target Operand Flag enum.
-typedef enum TOF {
-	//===------------------------------------------------------------------===//
-	// AArch64 Specific MachineOperand flags.
-
-	AArch64II_MO_NO_FLAG,
-
-	AArch64II_MO_FRAGMENT = 0x7,
-
-	/// MO_PAGE - A symbol operand with this flag represents the pc-relative
-	/// offset of the 4K page containing the symbol.  This is used with the
-	/// ADRP instruction.
-	AArch64II_MO_PAGE = 1,
-
-	/// MO_PAGEOFF - A symbol operand with this flag represents the offset of
-	/// that symbol within a 4K page.  This offset is added to the page address
-	/// to produce the complete address.
-	AArch64II_MO_PAGEOFF = 2,
-
-	/// MO_G3 - A symbol operand with this flag (granule 3) represents the high
-	/// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
-	AArch64II_MO_G3 = 3,
-
-	/// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
-	/// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
-	AArch64II_MO_G2 = 4,
-
-	/// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
-	/// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
-	AArch64II_MO_G1 = 5,
-
-	/// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
-	/// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
-	AArch64II_MO_G0 = 6,
-
-	/// MO_HI12 - This flag indicates that a symbol operand represents the bits
-	/// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
-	/// by-12-bits instruction.
-	AArch64II_MO_HI12 = 7,
-
-	/// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
-	/// reference is actually to the ".refptr.FOO" symbol.  This is used for
-	/// stub symbols on windows.
-	AArch64II_MO_COFFSTUB = 0x8,
-
-	/// MO_GOT - This flag indicates that a symbol operand represents the
-	/// address of the GOT entry for the symbol, rather than the address of
-	/// the symbol itself.
-	AArch64II_MO_GOT = 0x10,
-
-	/// MO_NC - Indicates whether the linker is expected to check the symbol
-	/// reference for overflow. For example in an ADRP/ADD pair of relocations
-	/// the ADRP usually does check, but not the ADD.
-	AArch64II_MO_NC = 0x20,
-
-	/// MO_TLS - Indicates that the operand being accessed is some kind of
-	/// thread-local symbol. On Darwin, only one type of thread-local access
-	/// exists (pre linker-relaxation), but on ELF the TLSModel used for the
-	/// referee will affect interpretation.
-	AArch64II_MO_TLS = 0x40,
-
-	/// MO_DLLIMPORT - On a symbol operand, this represents that the reference
-	/// to the symbol is for an import stub.  This is used for DLL import
-	/// storage class indication on Windows.
-	AArch64II_MO_DLLIMPORT = 0x80,
-
-	/// MO_S - Indicates that the bits of the symbol operand represented by
-	/// MO_G0 etc are signed.
-	AArch64II_MO_S = 0x100,
-
-	/// MO_PREL - Indicates that the bits of the symbol operand represented by
-	/// MO_G0 etc are PC relative.
-	AArch64II_MO_PREL = 0x200,
-
-	/// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag
-	/// in bits 56-63.
-	/// On a FrameIndex operand, indicates that the underlying memory is tagged
-	/// with an unknown tag value (MTE); this needs to be lowered either to an
-	/// SP-relative load or store instruction (which do not check tags), or to
-	/// an LDG instruction to obtain the tag value.
-	AArch64II_MO_TAGGED = 0x400,
-
-	/// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version
-	/// of a symbol, not the original. For dllimport symbols, this means it
-	/// uses "__imp_aux".  For other symbols, this means it uses the mangled
-	/// ("#" prefix for C) name.
-	AArch64II_MO_ARM64EC_CALLMANGLE = 0x800,
-} AArch64II_TOF;
-
-// CS namespace end: AArch64II
-
-// end namespace AArch64II
-
-//===----------------------------------------------------------------------===//
-// v8.3a Pointer Authentication
-//
-
-// CS namespace begin: AArch64PACKey
-
-typedef enum ID {
-	AArch64PACKey_IA = 0,
-	AArch64PACKey_IB = 1,
-	AArch64PACKey_DA = 2,
-	AArch64PACKey_DB = 3,
-	AArch64PACKey_LAST = AArch64PACKey_DB
-} AArch64PACKey_ID;
-
-// CS namespace end: AArch64PACKey
-
-// namespace AArch64PACKey
-
-/// Return 2-letter identifier string for numeric key ID.
-static inline const char *AArch64PACKeyIDToString(AArch64PACKey_ID KeyID)
-{
-	switch (KeyID) {
-	case AArch64PACKey_IA:
-		return "ia";
-	case AArch64PACKey_IB:
-		return "ib";
-	case AArch64PACKey_DA:
-		return "da";
-	case AArch64PACKey_DB:
-		return "db";
-	}
-	return NULL;
-}
-
-/// Return numeric key ID for 2-letter identifier string.
-static inline AArch64PACKey_ID AArch64StringToPACKeyID(const char *Name)
-{
-	if (strcmp(Name, "ia") == 0)
-		return AArch64PACKey_IA;
-	if (strcmp(Name, "ib") == 0)
-		return AArch64PACKey_IB;
-	if (strcmp(Name, "da") == 0)
-		return AArch64PACKey_DA;
-	if (strcmp(Name, "db") == 0)
-		return AArch64PACKey_DB;
-	assert(0 && "Invalid PAC key");
-	return AArch64PACKey_LAST;
-}
-
-// CS namespace begin: AArch64
-
-// The number of bits in a SVE register is architecturally defined
-// to be a multiple of this value.  If <M x t> has this number of bits,
-// a <n x M x t> vector can be stored in a SVE register without any
-// redundant bits.  If <M x t> has this number of bits divided by P,
-// a <n x M x t> vector is stored in a SVE register by placing index i
-// in index i*P of a <n x (M*P) x t> vector.  The other elements of the
-// <n x (M*P) x t> vector (such as index 1) are undefined.
-static const unsigned SVEBitsPerBlock = 128;
-
-static const unsigned SVEMaxBitsPerVector = 2048;
-
-// CS namespace end: AArch64
-
-// end namespace AArch64
-// end namespace llvm
-
-#endif

thirdparty/capstone/arch/AArch64/AArch64DisassemblerExtension.c

@@ -1,24 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
-
-#include "AArch64DisassemblerExtension.h"
-#include "AArch64BaseInfo.h"
-
-bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature)
-{
-	// we support everything
-	return true;
-}
-
-/// Tests a NULL terminated array of features if they are enabled.
-bool AArch64_testFeatureList(unsigned int mode, const unsigned int *features)
-{
-	int i = 0;
-	while (features[i]) {
-		if (!AArch64_getFeatureBits(mode, features[i]))
-			return false;
-		++i;
-	}
-	return true;
-}

thirdparty/capstone/arch/AArch64/AArch64DisassemblerExtension.h

@@ -1,19 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
-
-#ifndef CS_AARCH64_DISASSEMBLER_EXTENSION_H
-#define CS_AARCH64_DISASSEMBLER_EXTENSION_H
-
-#include "../../MCDisassembler.h"
-#include "../../MCRegisterInfo.h"
-#include "../../MathExtras.h"
-#include "../../cs_priv.h"
-#include "AArch64AddressingModes.h"
-#include "capstone/aarch64.h"
-#include "capstone/capstone.h"
-
-bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
-bool AArch64_testFeatureList(unsigned int mode, const unsigned int *features);
-
-#endif // CS_AARCH64_DISASSEMBLER_EXTENSION_H

thirdparty/capstone/arch/AArch64/AArch64GenCSAliasMnemMap.inc

@@ -1,375 +0,0 @@
-/* Capstone Disassembly Engine, https://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2024 */
-/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
-
-/* LLVM-commit: <commit> */
-/* LLVM-tag: <tag> */
-
-/* Do not edit. */
-
-/* Capstone's LLVM TableGen Backends: */
-/* https://github.com/capstone-engine/llvm-capstone */
-
-	{ AARCH64_INS_ALIAS_ADDPT, "addpt" },
-	{ AARCH64_INS_ALIAS_GCSB, "gcsb" },
-	{ AARCH64_INS_ALIAS_GCSPOPM, "gcspopm" },
-	{ AARCH64_INS_ALIAS_LDAPUR, "ldapur" },
-	{ AARCH64_INS_ALIAS_STLLRB, "stllrb" },
-	{ AARCH64_INS_ALIAS_STLLRH, "stllrh" },
-	{ AARCH64_INS_ALIAS_STLLR, "stllr" },
-	{ AARCH64_INS_ALIAS_STLRB, "stlrb" },
-	{ AARCH64_INS_ALIAS_STLRH, "stlrh" },
-	{ AARCH64_INS_ALIAS_STLR, "stlr" },
-	{ AARCH64_INS_ALIAS_STLUR, "stlur" },
-	{ AARCH64_INS_ALIAS_SUBPT, "subpt" },
-	{ AARCH64_INS_ALIAS_LDRAA, "ldraa" },
-	{ AARCH64_INS_ALIAS_ADD, "add" },
-	{ AARCH64_INS_ALIAS_CMN, "cmn" },
-	{ AARCH64_INS_ALIAS_ADDS, "adds" },
-	{ AARCH64_INS_ALIAS_AND, "and" },
-	{ AARCH64_INS_ALIAS_ANDS, "ands" },
-	{ AARCH64_INS_ALIAS_LDR, "ldr" },
-	{ AARCH64_INS_ALIAS_STR, "str" },
-	{ AARCH64_INS_ALIAS_LDRB, "ldrb" },
-	{ AARCH64_INS_ALIAS_STRB, "strb" },
-	{ AARCH64_INS_ALIAS_LDRH, "ldrh" },
-	{ AARCH64_INS_ALIAS_STRH, "strh" },
-	{ AARCH64_INS_ALIAS_PRFM, "prfm" },
-	{ AARCH64_INS_ALIAS_LDAPURB, "ldapurb" },
-	{ AARCH64_INS_ALIAS_STLURB, "stlurb" },
-	{ AARCH64_INS_ALIAS_LDUR, "ldur" },
-	{ AARCH64_INS_ALIAS_STUR, "stur" },
-	{ AARCH64_INS_ALIAS_PRFUM, "prfum" },
-	{ AARCH64_INS_ALIAS_LDTR, "ldtr" },
-	{ AARCH64_INS_ALIAS_STTR, "sttr" },
-	{ AARCH64_INS_ALIAS_LDP, "ldp" },
-	{ AARCH64_INS_ALIAS_STGP, "stgp" },
-	{ AARCH64_INS_ALIAS_LDNP, "ldnp" },
-	{ AARCH64_INS_ALIAS_STNP, "stnp" },
-	{ AARCH64_INS_ALIAS_STG, "stg" },
-	{ AARCH64_INS_ALIAS_MOV, "mov" },
-	{ AARCH64_INS_ALIAS_LD1, "ld1" },
-	{ AARCH64_INS_ALIAS_LD1R, "ld1r" },
-	{ AARCH64_INS_ALIAS_STADDLB, "staddlb" },
-	{ AARCH64_INS_ALIAS_STADDLH, "staddlh" },
-	{ AARCH64_INS_ALIAS_STADDL, "staddl" },
-	{ AARCH64_INS_ALIAS_STADDB, "staddb" },
-	{ AARCH64_INS_ALIAS_STADDH, "staddh" },
-	{ AARCH64_INS_ALIAS_STADD, "stadd" },
-	{ AARCH64_INS_ALIAS_PTRUE, "ptrue" },
-	{ AARCH64_INS_ALIAS_PTRUES, "ptrues" },
-	{ AARCH64_INS_ALIAS_CNTB, "cntb" },
-	{ AARCH64_INS_ALIAS_SQINCH, "sqinch" },
-	{ AARCH64_INS_ALIAS_INCB, "incb" },
-	{ AARCH64_INS_ALIAS_SQINCB, "sqincb" },
-	{ AARCH64_INS_ALIAS_UQINCB, "uqincb" },
-	{ AARCH64_INS_ALIAS_ORR, "orr" },
-	{ AARCH64_INS_ALIAS_DUPM, "dupm" },
-	{ AARCH64_INS_ALIAS_FMOV, "fmov" },
-	{ AARCH64_INS_ALIAS_EOR3, "eor3" },
-	{ AARCH64_INS_ALIAS_ST1B, "st1b" },
-	{ AARCH64_INS_ALIAS_ST2B, "st2b" },
-	{ AARCH64_INS_ALIAS_ST2Q, "st2q" },
-	{ AARCH64_INS_ALIAS_STNT1B, "stnt1b" },
-	{ AARCH64_INS_ALIAS_LD1B, "ld1b" },
-	{ AARCH64_INS_ALIAS_LDNT1B, "ldnt1b" },
-	{ AARCH64_INS_ALIAS_LD1RQB, "ld1rqb" },
-	{ AARCH64_INS_ALIAS_LD1RB, "ld1rb" },
-	{ AARCH64_INS_ALIAS_LDFF1B, "ldff1b" },
-	{ AARCH64_INS_ALIAS_LDNF1B, "ldnf1b" },
-	{ AARCH64_INS_ALIAS_LD2B, "ld2b" },
-	{ AARCH64_INS_ALIAS_LD1SB, "ld1sb" },
-	{ AARCH64_INS_ALIAS_PRFB, "prfb" },
-	{ AARCH64_INS_ALIAS_LDNT1SB, "ldnt1sb" },
-	{ AARCH64_INS_ALIAS_LD1ROB, "ld1rob" },
-	{ AARCH64_INS_ALIAS_LD1Q, "ld1q" },
-	{ AARCH64_INS_ALIAS_ST1Q, "st1q" },
-	{ AARCH64_INS_ALIAS_LD1W, "ld1w" },
-	{ AARCH64_INS_ALIAS_PMOV, "pmov" },
-	{ AARCH64_INS_ALIAS_SMSTART, "smstart" },
-	{ AARCH64_INS_ALIAS_SMSTOP, "smstop" },
-	{ AARCH64_INS_ALIAS_ZERO, "zero" },
-	{ AARCH64_INS_ALIAS_MOVT, "movt" },
-	{ AARCH64_INS_ALIAS_NOP, "nop" },
-	{ AARCH64_INS_ALIAS_YIELD, "yield" },
-	{ AARCH64_INS_ALIAS_WFE, "wfe" },
-	{ AARCH64_INS_ALIAS_WFI, "wfi" },
-	{ AARCH64_INS_ALIAS_SEV, "sev" },
-	{ AARCH64_INS_ALIAS_SEVL, "sevl" },
-	{ AARCH64_INS_ALIAS_DGH, "dgh" },
-	{ AARCH64_INS_ALIAS_ESB, "esb" },
-	{ AARCH64_INS_ALIAS_CSDB, "csdb" },
-	{ AARCH64_INS_ALIAS_BTI, "bti" },
-	{ AARCH64_INS_ALIAS_PSB, "psb" },
-	{ AARCH64_INS_ALIAS_CHKFEAT, "chkfeat" },
-	{ AARCH64_INS_ALIAS_PACIAZ, "paciaz" },
-	{ AARCH64_INS_ALIAS_PACIBZ, "pacibz" },
-	{ AARCH64_INS_ALIAS_AUTIAZ, "autiaz" },
-	{ AARCH64_INS_ALIAS_AUTIBZ, "autibz" },
-	{ AARCH64_INS_ALIAS_PACIASP, "paciasp" },
-	{ AARCH64_INS_ALIAS_PACIBSP, "pacibsp" },
-	{ AARCH64_INS_ALIAS_AUTIASP, "autiasp" },
-	{ AARCH64_INS_ALIAS_AUTIBSP, "autibsp" },
-	{ AARCH64_INS_ALIAS_PACIA1716, "pacia1716" },
-	{ AARCH64_INS_ALIAS_PACIB1716, "pacib1716" },
-	{ AARCH64_INS_ALIAS_AUTIA1716, "autia1716" },
-	{ AARCH64_INS_ALIAS_AUTIB1716, "autib1716" },
-	{ AARCH64_INS_ALIAS_XPACLRI, "xpaclri" },
-	{ AARCH64_INS_ALIAS_LDRAB, "ldrab" },
-	{ AARCH64_INS_ALIAS_PACM, "pacm" },
-	{ AARCH64_INS_ALIAS_CLREX, "clrex" },
-	{ AARCH64_INS_ALIAS_ISB, "isb" },
-	{ AARCH64_INS_ALIAS_SSBB, "ssbb" },
-	{ AARCH64_INS_ALIAS_PSSBB, "pssbb" },
-	{ AARCH64_INS_ALIAS_DFB, "dfb" },
-	{ AARCH64_INS_ALIAS_SYS, "sys" },
-	{ AARCH64_INS_ALIAS_MOVN, "movn" },
-	{ AARCH64_INS_ALIAS_MOVZ, "movz" },
-	{ AARCH64_INS_ALIAS_NGC, "ngc" },
-	{ AARCH64_INS_ALIAS_NGCS, "ngcs" },
-	{ AARCH64_INS_ALIAS_SUB, "sub" },
-	{ AARCH64_INS_ALIAS_CMP, "cmp" },
-	{ AARCH64_INS_ALIAS_SUBS, "subs" },
-	{ AARCH64_INS_ALIAS_NEG, "neg" },
-	{ AARCH64_INS_ALIAS_NEGS, "negs" },
-	{ AARCH64_INS_ALIAS_MUL, "mul" },
-	{ AARCH64_INS_ALIAS_MNEG, "mneg" },
-	{ AARCH64_INS_ALIAS_SMULL, "smull" },
-	{ AARCH64_INS_ALIAS_SMNEGL, "smnegl" },
-	{ AARCH64_INS_ALIAS_UMULL, "umull" },
-	{ AARCH64_INS_ALIAS_UMNEGL, "umnegl" },
-	{ AARCH64_INS_ALIAS_STCLRLB, "stclrlb" },
-	{ AARCH64_INS_ALIAS_STCLRLH, "stclrlh" },
-	{ AARCH64_INS_ALIAS_STCLRL, "stclrl" },
-	{ AARCH64_INS_ALIAS_STCLRB, "stclrb" },
-	{ AARCH64_INS_ALIAS_STCLRH, "stclrh" },
-	{ AARCH64_INS_ALIAS_STCLR, "stclr" },
-	{ AARCH64_INS_ALIAS_STEORLB, "steorlb" },
-	{ AARCH64_INS_ALIAS_STEORLH, "steorlh" },
-	{ AARCH64_INS_ALIAS_STEORL, "steorl" },
-	{ AARCH64_INS_ALIAS_STEORB, "steorb" },
-	{ AARCH64_INS_ALIAS_STEORH, "steorh" },
-	{ AARCH64_INS_ALIAS_STEOR, "steor" },
-	{ AARCH64_INS_ALIAS_STSETLB, "stsetlb" },
-	{ AARCH64_INS_ALIAS_STSETLH, "stsetlh" },
-	{ AARCH64_INS_ALIAS_STSETL, "stsetl" },
-	{ AARCH64_INS_ALIAS_STSETB, "stsetb" },
-	{ AARCH64_INS_ALIAS_STSETH, "stseth" },
-	{ AARCH64_INS_ALIAS_STSET, "stset" },
-	{ AARCH64_INS_ALIAS_STSMAXLB, "stsmaxlb" },
-	{ AARCH64_INS_ALIAS_STSMAXLH, "stsmaxlh" },
-	{ AARCH64_INS_ALIAS_STSMAXL, "stsmaxl" },
-	{ AARCH64_INS_ALIAS_STSMAXB, "stsmaxb" },
-	{ AARCH64_INS_ALIAS_STSMAXH, "stsmaxh" },
-	{ AARCH64_INS_ALIAS_STSMAX, "stsmax" },
-	{ AARCH64_INS_ALIAS_STSMINLB, "stsminlb" },
-	{ AARCH64_INS_ALIAS_STSMINLH, "stsminlh" },
-	{ AARCH64_INS_ALIAS_STSMINL, "stsminl" },
-	{ AARCH64_INS_ALIAS_STSMINB, "stsminb" },
-	{ AARCH64_INS_ALIAS_STSMINH, "stsminh" },
-	{ AARCH64_INS_ALIAS_STSMIN, "stsmin" },
-	{ AARCH64_INS_ALIAS_STUMAXLB, "stumaxlb" },
-	{ AARCH64_INS_ALIAS_STUMAXLH, "stumaxlh" },
-	{ AARCH64_INS_ALIAS_STUMAXL, "stumaxl" },
-	{ AARCH64_INS_ALIAS_STUMAXB, "stumaxb" },
-	{ AARCH64_INS_ALIAS_STUMAXH, "stumaxh" },
-	{ AARCH64_INS_ALIAS_STUMAX, "stumax" },
-	{ AARCH64_INS_ALIAS_STUMINLB, "stuminlb" },
-	{ AARCH64_INS_ALIAS_STUMINLH, "stuminlh" },
-	{ AARCH64_INS_ALIAS_STUMINL, "stuminl" },
-	{ AARCH64_INS_ALIAS_STUMINB, "stuminb" },
-	{ AARCH64_INS_ALIAS_STUMINH, "stuminh" },
-	{ AARCH64_INS_ALIAS_STUMIN, "stumin" },
-	{ AARCH64_INS_ALIAS_IRG, "irg" },
-	{ AARCH64_INS_ALIAS_LDG, "ldg" },
-	{ AARCH64_INS_ALIAS_STZG, "stzg" },
-	{ AARCH64_INS_ALIAS_ST2G, "st2g" },
-	{ AARCH64_INS_ALIAS_STZ2G, "stz2g" },
-	{ AARCH64_INS_ALIAS_BICS, "bics" },
-	{ AARCH64_INS_ALIAS_BIC, "bic" },
-	{ AARCH64_INS_ALIAS_EON, "eon" },
-	{ AARCH64_INS_ALIAS_EOR, "eor" },
-	{ AARCH64_INS_ALIAS_ORN, "orn" },
-	{ AARCH64_INS_ALIAS_MVN, "mvn" },
-	{ AARCH64_INS_ALIAS_TST, "tst" },
-	{ AARCH64_INS_ALIAS_ROR, "ror" },
-	{ AARCH64_INS_ALIAS_ASR, "asr" },
-	{ AARCH64_INS_ALIAS_SXTB, "sxtb" },
-	{ AARCH64_INS_ALIAS_SXTH, "sxth" },
-	{ AARCH64_INS_ALIAS_SXTW, "sxtw" },
-	{ AARCH64_INS_ALIAS_LSR, "lsr" },
-	{ AARCH64_INS_ALIAS_UXTB, "uxtb" },
-	{ AARCH64_INS_ALIAS_UXTH, "uxth" },
-	{ AARCH64_INS_ALIAS_UXTW, "uxtw" },
-	{ AARCH64_INS_ALIAS_CSET, "cset" },
-	{ AARCH64_INS_ALIAS_CSETM, "csetm" },
-	{ AARCH64_INS_ALIAS_CINC, "cinc" },
-	{ AARCH64_INS_ALIAS_CINV, "cinv" },
-	{ AARCH64_INS_ALIAS_CNEG, "cneg" },
-	{ AARCH64_INS_ALIAS_RET, "ret" },
-	{ AARCH64_INS_ALIAS_DCPS1, "dcps1" },
-	{ AARCH64_INS_ALIAS_DCPS2, "dcps2" },
-	{ AARCH64_INS_ALIAS_DCPS3, "dcps3" },
-	{ AARCH64_INS_ALIAS_LDPSW, "ldpsw" },
-	{ AARCH64_INS_ALIAS_LDRSH, "ldrsh" },
-	{ AARCH64_INS_ALIAS_LDRSB, "ldrsb" },
-	{ AARCH64_INS_ALIAS_LDRSW, "ldrsw" },
-	{ AARCH64_INS_ALIAS_LDURH, "ldurh" },
-	{ AARCH64_INS_ALIAS_LDURB, "ldurb" },
-	{ AARCH64_INS_ALIAS_LDURSH, "ldursh" },
-	{ AARCH64_INS_ALIAS_LDURSB, "ldursb" },
-	{ AARCH64_INS_ALIAS_LDURSW, "ldursw" },
-	{ AARCH64_INS_ALIAS_LDTRH, "ldtrh" },
-	{ AARCH64_INS_ALIAS_LDTRB, "ldtrb" },
-	{ AARCH64_INS_ALIAS_LDTRSH, "ldtrsh" },
-	{ AARCH64_INS_ALIAS_LDTRSB, "ldtrsb" },
-	{ AARCH64_INS_ALIAS_LDTRSW, "ldtrsw" },
-	{ AARCH64_INS_ALIAS_STP, "stp" },
-	{ AARCH64_INS_ALIAS_STURH, "sturh" },
-	{ AARCH64_INS_ALIAS_STURB, "sturb" },
-	{ AARCH64_INS_ALIAS_STLURH, "stlurh" },
-	{ AARCH64_INS_ALIAS_LDAPURSB, "ldapursb" },
-	{ AARCH64_INS_ALIAS_LDAPURH, "ldapurh" },
-	{ AARCH64_INS_ALIAS_LDAPURSH, "ldapursh" },
-	{ AARCH64_INS_ALIAS_LDAPURSW, "ldapursw" },
-	{ AARCH64_INS_ALIAS_STTRH, "sttrh" },
-	{ AARCH64_INS_ALIAS_STTRB, "sttrb" },
-	{ AARCH64_INS_ALIAS_BIC_4H, "bic_4h" },
-	{ AARCH64_INS_ALIAS_BIC_8H, "bic_8h" },
-	{ AARCH64_INS_ALIAS_BIC_2S, "bic_2s" },
-	{ AARCH64_INS_ALIAS_BIC_4S, "bic_4s" },
-	{ AARCH64_INS_ALIAS_ORR_4H, "orr_4h" },
-	{ AARCH64_INS_ALIAS_ORR_8H, "orr_8h" },
-	{ AARCH64_INS_ALIAS_ORR_2S, "orr_2s" },
-	{ AARCH64_INS_ALIAS_ORR_4S, "orr_4s" },
-	{ AARCH64_INS_ALIAS_SXTL_8H, "sxtl_8h" },
-	{ AARCH64_INS_ALIAS_SXTL, "sxtl" },
-	{ AARCH64_INS_ALIAS_SXTL_4S, "sxtl_4s" },
-	{ AARCH64_INS_ALIAS_SXTL_2D, "sxtl_2d" },
-	{ AARCH64_INS_ALIAS_SXTL2_8H, "sxtl2_8h" },
-	{ AARCH64_INS_ALIAS_SXTL2, "sxtl2" },
-	{ AARCH64_INS_ALIAS_SXTL2_4S, "sxtl2_4s" },
-	{ AARCH64_INS_ALIAS_SXTL2_2D, "sxtl2_2d" },
-	{ AARCH64_INS_ALIAS_UXTL_8H, "uxtl_8h" },
-	{ AARCH64_INS_ALIAS_UXTL, "uxtl" },
-	{ AARCH64_INS_ALIAS_UXTL_4S, "uxtl_4s" },
-	{ AARCH64_INS_ALIAS_UXTL_2D, "uxtl_2d" },
-	{ AARCH64_INS_ALIAS_UXTL2_8H, "uxtl2_8h" },
-	{ AARCH64_INS_ALIAS_UXTL2, "uxtl2" },
-	{ AARCH64_INS_ALIAS_UXTL2_4S, "uxtl2_4s" },
-	{ AARCH64_INS_ALIAS_UXTL2_2D, "uxtl2_2d" },
-	{ AARCH64_INS_ALIAS_LD2, "ld2" },
-	{ AARCH64_INS_ALIAS_LD3, "ld3" },
-	{ AARCH64_INS_ALIAS_LD4, "ld4" },
-	{ AARCH64_INS_ALIAS_ST1, "st1" },
-	{ AARCH64_INS_ALIAS_ST2, "st2" },
-	{ AARCH64_INS_ALIAS_ST3, "st3" },
-	{ AARCH64_INS_ALIAS_ST4, "st4" },
-	{ AARCH64_INS_ALIAS_LD2R, "ld2r" },
-	{ AARCH64_INS_ALIAS_LD3R, "ld3r" },
-	{ AARCH64_INS_ALIAS_LD4R, "ld4r" },
-	{ AARCH64_INS_ALIAS_CLRBHB, "clrbhb" },
-	{ AARCH64_INS_ALIAS_STILP, "stilp" },
-	{ AARCH64_INS_ALIAS_STL1, "stl1" },
-	{ AARCH64_INS_ALIAS_SYSP, "sysp" },
-	{ AARCH64_INS_ALIAS_LD1SW, "ld1sw" },
-	{ AARCH64_INS_ALIAS_LD1H, "ld1h" },
-	{ AARCH64_INS_ALIAS_LD1SH, "ld1sh" },
-	{ AARCH64_INS_ALIAS_LD1D, "ld1d" },
-	{ AARCH64_INS_ALIAS_LD1RSW, "ld1rsw" },
-	{ AARCH64_INS_ALIAS_LD1RH, "ld1rh" },
-	{ AARCH64_INS_ALIAS_LD1RSH, "ld1rsh" },
-	{ AARCH64_INS_ALIAS_LD1RW, "ld1rw" },
-	{ AARCH64_INS_ALIAS_LD1RSB, "ld1rsb" },
-	{ AARCH64_INS_ALIAS_LD1RD, "ld1rd" },
-	{ AARCH64_INS_ALIAS_LD1RQH, "ld1rqh" },
-	{ AARCH64_INS_ALIAS_LD1RQW, "ld1rqw" },
-	{ AARCH64_INS_ALIAS_LD1RQD, "ld1rqd" },
-	{ AARCH64_INS_ALIAS_LDNF1SW, "ldnf1sw" },
-	{ AARCH64_INS_ALIAS_LDNF1H, "ldnf1h" },
-	{ AARCH64_INS_ALIAS_LDNF1SH, "ldnf1sh" },
-	{ AARCH64_INS_ALIAS_LDNF1W, "ldnf1w" },
-	{ AARCH64_INS_ALIAS_LDNF1SB, "ldnf1sb" },
-	{ AARCH64_INS_ALIAS_LDNF1D, "ldnf1d" },
-	{ AARCH64_INS_ALIAS_LDFF1SW, "ldff1sw" },
-	{ AARCH64_INS_ALIAS_LDFF1H, "ldff1h" },
-	{ AARCH64_INS_ALIAS_LDFF1SH, "ldff1sh" },
-	{ AARCH64_INS_ALIAS_LDFF1W, "ldff1w" },
-	{ AARCH64_INS_ALIAS_LDFF1SB, "ldff1sb" },
-	{ AARCH64_INS_ALIAS_LDFF1D, "ldff1d" },
-	{ AARCH64_INS_ALIAS_LD3B, "ld3b" },
-	{ AARCH64_INS_ALIAS_LD4B, "ld4b" },
-	{ AARCH64_INS_ALIAS_LD2H, "ld2h" },
-	{ AARCH64_INS_ALIAS_LD3H, "ld3h" },
-	{ AARCH64_INS_ALIAS_LD4H, "ld4h" },
-	{ AARCH64_INS_ALIAS_LD2W, "ld2w" },
-	{ AARCH64_INS_ALIAS_LD3W, "ld3w" },
-	{ AARCH64_INS_ALIAS_LD4W, "ld4w" },
-	{ AARCH64_INS_ALIAS_LD2D, "ld2d" },
-	{ AARCH64_INS_ALIAS_LD3D, "ld3d" },
-	{ AARCH64_INS_ALIAS_LD4D, "ld4d" },
-	{ AARCH64_INS_ALIAS_LD2Q, "ld2q" },
-	{ AARCH64_INS_ALIAS_LD3Q, "ld3q" },
-	{ AARCH64_INS_ALIAS_LD4Q, "ld4q" },
-	{ AARCH64_INS_ALIAS_LDNT1H, "ldnt1h" },
-	{ AARCH64_INS_ALIAS_LDNT1W, "ldnt1w" },
-	{ AARCH64_INS_ALIAS_LDNT1D, "ldnt1d" },
-	{ AARCH64_INS_ALIAS_ST1H, "st1h" },
-	{ AARCH64_INS_ALIAS_ST1W, "st1w" },
-	{ AARCH64_INS_ALIAS_ST1D, "st1d" },
-	{ AARCH64_INS_ALIAS_ST3B, "st3b" },
-	{ AARCH64_INS_ALIAS_ST4B, "st4b" },
-	{ AARCH64_INS_ALIAS_ST2H, "st2h" },
-	{ AARCH64_INS_ALIAS_ST3H, "st3h" },
-	{ AARCH64_INS_ALIAS_ST4H, "st4h" },
-	{ AARCH64_INS_ALIAS_ST2W, "st2w" },
-	{ AARCH64_INS_ALIAS_ST3W, "st3w" },
-	{ AARCH64_INS_ALIAS_ST4W, "st4w" },
-	{ AARCH64_INS_ALIAS_ST2D, "st2d" },
-	{ AARCH64_INS_ALIAS_ST3D, "st3d" },
-	{ AARCH64_INS_ALIAS_ST4D, "st4d" },
-	{ AARCH64_INS_ALIAS_ST3Q, "st3q" },
-	{ AARCH64_INS_ALIAS_ST4Q, "st4q" },
-	{ AARCH64_INS_ALIAS_STNT1H, "stnt1h" },
-	{ AARCH64_INS_ALIAS_STNT1W, "stnt1w" },
-	{ AARCH64_INS_ALIAS_STNT1D, "stnt1d" },
-	{ AARCH64_INS_ALIAS_PRFH, "prfh" },
-	{ AARCH64_INS_ALIAS_PRFW, "prfw" },
-	{ AARCH64_INS_ALIAS_PRFD, "prfd" },
-	{ AARCH64_INS_ALIAS_CNTH, "cnth" },
-	{ AARCH64_INS_ALIAS_CNTW, "cntw" },
-	{ AARCH64_INS_ALIAS_CNTD, "cntd" },
-	{ AARCH64_INS_ALIAS_DECB, "decb" },
-	{ AARCH64_INS_ALIAS_INCH, "inch" },
-	{ AARCH64_INS_ALIAS_DECH, "dech" },
-	{ AARCH64_INS_ALIAS_INCW, "incw" },
-	{ AARCH64_INS_ALIAS_DECW, "decw" },
-	{ AARCH64_INS_ALIAS_INCD, "incd" },
-	{ AARCH64_INS_ALIAS_DECD, "decd" },
-	{ AARCH64_INS_ALIAS_SQDECB, "sqdecb" },
-	{ AARCH64_INS_ALIAS_UQDECB, "uqdecb" },
-	{ AARCH64_INS_ALIAS_UQINCH, "uqinch" },
-	{ AARCH64_INS_ALIAS_SQDECH, "sqdech" },
-	{ AARCH64_INS_ALIAS_UQDECH, "uqdech" },
-	{ AARCH64_INS_ALIAS_SQINCW, "sqincw" },
-	{ AARCH64_INS_ALIAS_UQINCW, "uqincw" },
-	{ AARCH64_INS_ALIAS_SQDECW, "sqdecw" },
-	{ AARCH64_INS_ALIAS_UQDECW, "uqdecw" },
-	{ AARCH64_INS_ALIAS_SQINCD, "sqincd" },
-	{ AARCH64_INS_ALIAS_UQINCD, "uqincd" },
-	{ AARCH64_INS_ALIAS_SQDECD, "sqdecd" },
-	{ AARCH64_INS_ALIAS_UQDECD, "uqdecd" },
-	{ AARCH64_INS_ALIAS_MOVS, "movs" },
-	{ AARCH64_INS_ALIAS_NOT, "not" },
-	{ AARCH64_INS_ALIAS_NOTS, "nots" },
-	{ AARCH64_INS_ALIAS_LD1ROH, "ld1roh" },
-	{ AARCH64_INS_ALIAS_LD1ROW, "ld1row" },
-	{ AARCH64_INS_ALIAS_LD1ROD, "ld1rod" },
-	{ AARCH64_INS_ALIAS_BCAX, "bcax" },
-	{ AARCH64_INS_ALIAS_BSL, "bsl" },
-	{ AARCH64_INS_ALIAS_BSL1N, "bsl1n" },
-	{ AARCH64_INS_ALIAS_BSL2N, "bsl2n" },
-	{ AARCH64_INS_ALIAS_NBSL, "nbsl" },
-	{ AARCH64_INS_ALIAS_LDNT1SH, "ldnt1sh" },
-	{ AARCH64_INS_ALIAS_LDNT1SW, "ldnt1sw" },

thirdparty/capstone/arch/AArch64/AArch64GenCSFeatureName.inc

@@ -1,136 +0,0 @@
-/* Capstone Disassembly Engine, https://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2024 */
-/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
-
-/* LLVM-commit: <commit> */
-/* LLVM-tag: <tag> */
-
-/* Do not edit. */
-
-/* Capstone's LLVM TableGen Backends: */
-/* https://github.com/capstone-engine/llvm-capstone */
-
-{ AARCH64_FEATURE_HASV8_0A, "HasV8_0a" },
-{ AARCH64_FEATURE_HASV8_1A, "HasV8_1a" },
-{ AARCH64_FEATURE_HASV8_2A, "HasV8_2a" },
-{ AARCH64_FEATURE_HASV8_3A, "HasV8_3a" },
-{ AARCH64_FEATURE_HASV8_4A, "HasV8_4a" },
-{ AARCH64_FEATURE_HASV8_5A, "HasV8_5a" },
-{ AARCH64_FEATURE_HASV8_6A, "HasV8_6a" },
-{ AARCH64_FEATURE_HASV8_7A, "HasV8_7a" },
-{ AARCH64_FEATURE_HASV8_8A, "HasV8_8a" },
-{ AARCH64_FEATURE_HASV8_9A, "HasV8_9a" },
-{ AARCH64_FEATURE_HASV9_0A, "HasV9_0a" },
-{ AARCH64_FEATURE_HASV9_1A, "HasV9_1a" },
-{ AARCH64_FEATURE_HASV9_2A, "HasV9_2a" },
-{ AARCH64_FEATURE_HASV9_3A, "HasV9_3a" },
-{ AARCH64_FEATURE_HASV9_4A, "HasV9_4a" },
-{ AARCH64_FEATURE_HASV8_0R, "HasV8_0r" },
-{ AARCH64_FEATURE_HASEL2VMSA, "HasEL2VMSA" },
-{ AARCH64_FEATURE_HASEL3, "HasEL3" },
-{ AARCH64_FEATURE_HASVH, "HasVH" },
-{ AARCH64_FEATURE_HASLOR, "HasLOR" },
-{ AARCH64_FEATURE_HASPAUTH, "HasPAuth" },
-{ AARCH64_FEATURE_HASPAUTHLR, "HasPAuthLR" },
-{ AARCH64_FEATURE_HASJS, "HasJS" },
-{ AARCH64_FEATURE_HASCCIDX, "HasCCIDX" },
-{ AARCH64_FEATURE_HASCOMPLXNUM, "HasComplxNum" },
-{ AARCH64_FEATURE_HASNV, "HasNV" },
-{ AARCH64_FEATURE_HASMPAM, "HasMPAM" },
-{ AARCH64_FEATURE_HASDIT, "HasDIT" },
-{ AARCH64_FEATURE_HASTRACEV8_4, "HasTRACEV8_4" },
-{ AARCH64_FEATURE_HASAM, "HasAM" },
-{ AARCH64_FEATURE_HASSEL2, "HasSEL2" },
-{ AARCH64_FEATURE_HASTLB_RMI, "HasTLB_RMI" },
-{ AARCH64_FEATURE_HASFLAGM, "HasFlagM" },
-{ AARCH64_FEATURE_HASRCPC_IMMO, "HasRCPC_IMMO" },
-{ AARCH64_FEATURE_HASFPARMV8, "HasFPARMv8" },
-{ AARCH64_FEATURE_HASNEON, "HasNEON" },
-{ AARCH64_FEATURE_HASSM4, "HasSM4" },
-{ AARCH64_FEATURE_HASSHA3, "HasSHA3" },
-{ AARCH64_FEATURE_HASSHA2, "HasSHA2" },
-{ AARCH64_FEATURE_HASAES, "HasAES" },
-{ AARCH64_FEATURE_HASDOTPROD, "HasDotProd" },
-{ AARCH64_FEATURE_HASCRC, "HasCRC" },
-{ AARCH64_FEATURE_HASCSSC, "HasCSSC" },
-{ AARCH64_FEATURE_HASLSE, "HasLSE" },
-{ AARCH64_FEATURE_HASRAS, "HasRAS" },
-{ AARCH64_FEATURE_HASRDM, "HasRDM" },
-{ AARCH64_FEATURE_HASFULLFP16, "HasFullFP16" },
-{ AARCH64_FEATURE_HASFP16FML, "HasFP16FML" },
-{ AARCH64_FEATURE_HASSPE, "HasSPE" },
-{ AARCH64_FEATURE_HASFUSEAES, "HasFuseAES" },
-{ AARCH64_FEATURE_HASSVE, "HasSVE" },
-{ AARCH64_FEATURE_HASSVE2, "HasSVE2" },
-{ AARCH64_FEATURE_HASSVE2P1, "HasSVE2p1" },
-{ AARCH64_FEATURE_HASSVE2AES, "HasSVE2AES" },
-{ AARCH64_FEATURE_HASSVE2SM4, "HasSVE2SM4" },
-{ AARCH64_FEATURE_HASSVE2SHA3, "HasSVE2SHA3" },
-{ AARCH64_FEATURE_HASSVE2BITPERM, "HasSVE2BitPerm" },
-{ AARCH64_FEATURE_HASB16B16, "HasB16B16" },
-{ AARCH64_FEATURE_HASSME, "HasSME" },
-{ AARCH64_FEATURE_HASSMEF64F64, "HasSMEF64F64" },
-{ AARCH64_FEATURE_HASSMEF16F16, "HasSMEF16F16" },
-{ AARCH64_FEATURE_HASSMEFA64, "HasSMEFA64" },
-{ AARCH64_FEATURE_HASSMEI16I64, "HasSMEI16I64" },
-{ AARCH64_FEATURE_HASSME2, "HasSME2" },
-{ AARCH64_FEATURE_HASSME2P1, "HasSME2p1" },
-{ AARCH64_FEATURE_HASFPMR, "HasFPMR" },
-{ AARCH64_FEATURE_HASFP8, "HasFP8" },
-{ AARCH64_FEATURE_HASFAMINMAX, "HasFAMINMAX" },
-{ AARCH64_FEATURE_HASFP8FMA, "HasFP8FMA" },
-{ AARCH64_FEATURE_HASSSVE_FP8FMA, "HasSSVE_FP8FMA" },
-{ AARCH64_FEATURE_HASFP8DOT2, "HasFP8DOT2" },
-{ AARCH64_FEATURE_HASSSVE_FP8DOT2, "HasSSVE_FP8DOT2" },
-{ AARCH64_FEATURE_HASFP8DOT4, "HasFP8DOT4" },
-{ AARCH64_FEATURE_HASSSVE_FP8DOT4, "HasSSVE_FP8DOT4" },
-{ AARCH64_FEATURE_HASLUT, "HasLUT" },
-{ AARCH64_FEATURE_HASSME_LUTV2, "HasSME_LUTv2" },
-{ AARCH64_FEATURE_HASSMEF8F16, "HasSMEF8F16" },
-{ AARCH64_FEATURE_HASSMEF8F32, "HasSMEF8F32" },
-{ AARCH64_FEATURE_HASSVEORSME, "HasSVEorSME" },
-{ AARCH64_FEATURE_HASSVE2ORSME, "HasSVE2orSME" },
-{ AARCH64_FEATURE_HASSVE2ORSME2, "HasSVE2orSME2" },
-{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME, "HasSVE2p1_or_HasSME" },
-{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME2, "HasSVE2p1_or_HasSME2" },
-{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME2P1, "HasSVE2p1_or_HasSME2p1" },
-{ AARCH64_FEATURE_HASNEONORSME, "HasNEONorSME" },
-{ AARCH64_FEATURE_HASRCPC, "HasRCPC" },
-{ AARCH64_FEATURE_HASALTNZCV, "HasAltNZCV" },
-{ AARCH64_FEATURE_HASFRINT3264, "HasFRInt3264" },
-{ AARCH64_FEATURE_HASSB, "HasSB" },
-{ AARCH64_FEATURE_HASPREDRES, "HasPredRes" },
-{ AARCH64_FEATURE_HASCCDP, "HasCCDP" },
-{ AARCH64_FEATURE_HASBTI, "HasBTI" },
-{ AARCH64_FEATURE_HASMTE, "HasMTE" },
-{ AARCH64_FEATURE_HASTME, "HasTME" },
-{ AARCH64_FEATURE_HASETE, "HasETE" },
-{ AARCH64_FEATURE_HASTRBE, "HasTRBE" },
-{ AARCH64_FEATURE_HASBF16, "HasBF16" },
-{ AARCH64_FEATURE_HASMATMULINT8, "HasMatMulInt8" },
-{ AARCH64_FEATURE_HASMATMULFP32, "HasMatMulFP32" },
-{ AARCH64_FEATURE_HASMATMULFP64, "HasMatMulFP64" },
-{ AARCH64_FEATURE_HASXS, "HasXS" },
-{ AARCH64_FEATURE_HASWFXT, "HasWFxT" },
-{ AARCH64_FEATURE_HASLS64, "HasLS64" },
-{ AARCH64_FEATURE_HASBRBE, "HasBRBE" },
-{ AARCH64_FEATURE_HASSPE_EEF, "HasSPE_EEF" },
-{ AARCH64_FEATURE_HASHBC, "HasHBC" },
-{ AARCH64_FEATURE_HASMOPS, "HasMOPS" },
-{ AARCH64_FEATURE_HASCLRBHB, "HasCLRBHB" },
-{ AARCH64_FEATURE_HASSPECRES2, "HasSPECRES2" },
-{ AARCH64_FEATURE_HASITE, "HasITE" },
-{ AARCH64_FEATURE_HASTHE, "HasTHE" },
-{ AARCH64_FEATURE_HASRCPC3, "HasRCPC3" },
-{ AARCH64_FEATURE_HASLSE128, "HasLSE128" },
-{ AARCH64_FEATURE_HASD128, "HasD128" },
-{ AARCH64_FEATURE_HASCHK, "HasCHK" },
-{ AARCH64_FEATURE_HASGCS, "HasGCS" },
-{ AARCH64_FEATURE_HASCPA, "HasCPA" },
-{ AARCH64_FEATURE_USENEGATIVEIMMEDIATES, "UseNegativeImmediates" },
-{ AARCH64_FEATURE_HASCCPP, "HasCCPP" },
-{ AARCH64_FEATURE_HASPAN, "HasPAN" },
-{ AARCH64_FEATURE_HASPSUAO, "HasPsUAO" },
-{ AARCH64_FEATURE_HASPAN_RWV, "HasPAN_RWV" },
-{ AARCH64_FEATURE_HASCONTEXTIDREL2, "HasCONTEXTIDREL2" },

thirdparty/capstone/arch/AArch64/AArch64GenCSOpGroup.inc

@@ -1,180 +0,0 @@
-/* Capstone Disassembly Engine, https://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2024 */
-/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
-
-/* LLVM-commit: <commit> */
-/* LLVM-tag: <tag> */
-
-/* Do not edit. */
-
-/* Capstone's LLVM TableGen Backends: */
-/* https://github.com/capstone-engine/llvm-capstone */
-
-  AArch64_OP_GROUP_AMNoIndex = 0,
-  AArch64_OP_GROUP_AdrLabel = 1,
-  AArch64_OP_GROUP_AdrpLabel = 2,
-  AArch64_OP_GROUP_BTIHintOp = 3,
-  AArch64_OP_GROUP_ImplicitlyTypedVectorList = 4,
-  AArch64_OP_GROUP_InverseCondCode = 5,
-  AArch64_OP_GROUP_LogicalImm_int16_t = 6,
-  AArch64_OP_GROUP_LogicalImm_int8_t = 7,
-  AArch64_OP_GROUP_MatrixIndex_0 = 8,
-  AArch64_OP_GROUP_MatrixIndex_1 = 9,
-  AArch64_OP_GROUP_MatrixIndex_8 = 10,
-  AArch64_OP_GROUP_PSBHintOp = 11,
-  AArch64_OP_GROUP_PrefetchOp_1 = 12,
-  AArch64_OP_GROUP_SVELogicalImm_int16_t = 13,
-  AArch64_OP_GROUP_SVELogicalImm_int32_t = 14,
-  AArch64_OP_GROUP_SVELogicalImm_int64_t = 15,
-  AArch64_OP_GROUP_SVERegOp_0 = 16,
-  AArch64_OP_GROUP_VectorIndex_8 = 17,
-  AArch64_OP_GROUP_ZPRasFPR_128 = 18,
-  AArch64_OP_GROUP_Operand = 19,
-  AArch64_OP_GROUP_SVERegOp_b = 20,
-  AArch64_OP_GROUP_SVERegOp_d = 21,
-  AArch64_OP_GROUP_SVERegOp_h = 22,
-  AArch64_OP_GROUP_SVERegOp_s = 23,
-  AArch64_OP_GROUP_TypedVectorList_0_d = 24,
-  AArch64_OP_GROUP_TypedVectorList_0_s = 25,
-  AArch64_OP_GROUP_VRegOperand = 26,
-  AArch64_OP_GROUP_TypedVectorList_0_h = 27,
-  AArch64_OP_GROUP_VectorIndex_1 = 28,
-  AArch64_OP_GROUP_ImmRangeScale_2_1 = 29,
-  AArch64_OP_GROUP_AlignedLabel = 30,
-  AArch64_OP_GROUP_CondCode = 31,
-  AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_one = 32,
-  AArch64_OP_GROUP_TypedVectorList_0_b = 33,
-  AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_zero_AArch64ExactFPImm_one = 34,
-  AArch64_OP_GROUP_ImmRangeScale_4_3 = 35,
-  AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_two = 36,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_d = 37,
-  AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_d = 38,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_d = 39,
-  AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_s = 40,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_s = 41,
-  AArch64_OP_GROUP_ImmScale_8 = 42,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_d = 43,
-  AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_d = 44,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_d = 45,
-  AArch64_OP_GROUP_ImmScale_2 = 46,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_d = 47,
-  AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_d = 48,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_d = 49,
-  AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_s = 50,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_s = 51,
-  AArch64_OP_GROUP_ImmScale_4 = 52,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_d = 53,
-  AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_d = 54,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_d = 55,
-  AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_s = 56,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_s = 57,
-  AArch64_OP_GROUP_PredicateAsCounter_0 = 58,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_0 = 59,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_0 = 60,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_0 = 61,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_0 = 62,
-  AArch64_OP_GROUP_SVCROp = 63,
-  AArch64_OP_GROUP_ImmScale_16 = 64,
-  AArch64_OP_GROUP_MatrixTile = 65,
-  AArch64_OP_GROUP_Shifter = 66,
-  AArch64_OP_GROUP_AddSubImm = 67,
-  AArch64_OP_GROUP_ShiftedRegister = 68,
-  AArch64_OP_GROUP_ExtendedRegister = 69,
-  AArch64_OP_GROUP_ArithExtend = 70,
-  AArch64_OP_GROUP_Matrix_64 = 71,
-  AArch64_OP_GROUP_Matrix_32 = 72,
-  AArch64_OP_GROUP_Imm8OptLsl_uint8_t = 73,
-  AArch64_OP_GROUP_Imm8OptLsl_uint64_t = 74,
-  AArch64_OP_GROUP_Imm8OptLsl_uint16_t = 75,
-  AArch64_OP_GROUP_Imm8OptLsl_uint32_t = 76,
-  AArch64_OP_GROUP_AdrAdrpLabel = 77,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_s = 78,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_s = 79,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_s = 80,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_s = 81,
-  AArch64_OP_GROUP_LogicalImm_int32_t = 82,
-  AArch64_OP_GROUP_LogicalImm_int64_t = 83,
-  AArch64_OP_GROUP_ZPRasFPR_8 = 84,
-  AArch64_OP_GROUP_ZPRasFPR_64 = 85,
-  AArch64_OP_GROUP_ZPRasFPR_16 = 86,
-  AArch64_OP_GROUP_ZPRasFPR_32 = 87,
-  AArch64_OP_GROUP_Matrix_16 = 88,
-  AArch64_OP_GROUP_Imm = 89,
-  AArch64_OP_GROUP_ImmHex = 90,
-  AArch64_OP_GROUP_ComplexRotationOp_180_90 = 91,
-  AArch64_OP_GROUP_GPRSeqPairsClassOperand_32 = 92,
-  AArch64_OP_GROUP_GPRSeqPairsClassOperand_64 = 93,
-  AArch64_OP_GROUP_ComplexRotationOp_90_0 = 94,
-  AArch64_OP_GROUP_SVEPattern = 95,
-  AArch64_OP_GROUP_PredicateAsCounter_8 = 96,
-  AArch64_OP_GROUP_SVEVecLenSpecifier = 97,
-  AArch64_OP_GROUP_PredicateAsCounter_64 = 98,
-  AArch64_OP_GROUP_PredicateAsCounter_16 = 99,
-  AArch64_OP_GROUP_PredicateAsCounter_32 = 100,
-  AArch64_OP_GROUP_Imm8OptLsl_int8_t = 101,
-  AArch64_OP_GROUP_Imm8OptLsl_int64_t = 102,
-  AArch64_OP_GROUP_Imm8OptLsl_int16_t = 103,
-  AArch64_OP_GROUP_Imm8OptLsl_int32_t = 104,
-  AArch64_OP_GROUP_BarrierOption = 105,
-  AArch64_OP_GROUP_BarriernXSOption = 106,
-  AArch64_OP_GROUP_SVERegOp_q = 107,
-  AArch64_OP_GROUP_MatrixTileVector_0 = 108,
-  AArch64_OP_GROUP_MatrixTileVector_1 = 109,
-  AArch64_OP_GROUP_FPImmOperand = 110,
-  AArch64_OP_GROUP_TypedVectorList_0_q = 111,
-  AArch64_OP_GROUP_SImm_8 = 112,
-  AArch64_OP_GROUP_SImm_16 = 113,
-  AArch64_OP_GROUP_TypedVectorList_16_b = 114,
-  AArch64_OP_GROUP_PostIncOperand_64 = 115,
-  AArch64_OP_GROUP_TypedVectorList_1_d = 116,
-  AArch64_OP_GROUP_PostIncOperand_32 = 117,
-  AArch64_OP_GROUP_TypedVectorList_2_d = 118,
-  AArch64_OP_GROUP_TypedVectorList_2_s = 119,
-  AArch64_OP_GROUP_TypedVectorList_4_h = 120,
-  AArch64_OP_GROUP_TypedVectorList_4_s = 121,
-  AArch64_OP_GROUP_TypedVectorList_8_b = 122,
-  AArch64_OP_GROUP_TypedVectorList_8_h = 123,
-  AArch64_OP_GROUP_PostIncOperand_16 = 124,
-  AArch64_OP_GROUP_PostIncOperand_8 = 125,
-  AArch64_OP_GROUP_ImmScale_32 = 126,
-  AArch64_OP_GROUP_PostIncOperand_1 = 127,
-  AArch64_OP_GROUP_PostIncOperand_4 = 128,
-  AArch64_OP_GROUP_PostIncOperand_2 = 129,
-  AArch64_OP_GROUP_PostIncOperand_48 = 130,
-  AArch64_OP_GROUP_PostIncOperand_24 = 131,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_128_x_0 = 132,
-  AArch64_OP_GROUP_ImmScale_3 = 133,
-  AArch64_OP_GROUP_PostIncOperand_3 = 134,
-  AArch64_OP_GROUP_PostIncOperand_12 = 135,
-  AArch64_OP_GROUP_PostIncOperand_6 = 136,
-  AArch64_OP_GROUP_GPR64x8 = 137,
-  AArch64_OP_GROUP_MemExtend_w_8 = 138,
-  AArch64_OP_GROUP_MemExtend_x_8 = 139,
-  AArch64_OP_GROUP_UImm12Offset_1 = 140,
-  AArch64_OP_GROUP_MemExtend_w_64 = 141,
-  AArch64_OP_GROUP_MemExtend_x_64 = 142,
-  AArch64_OP_GROUP_UImm12Offset_8 = 143,
-  AArch64_OP_GROUP_MemExtend_w_16 = 144,
-  AArch64_OP_GROUP_MemExtend_x_16 = 145,
-  AArch64_OP_GROUP_UImm12Offset_2 = 146,
-  AArch64_OP_GROUP_MemExtend_w_128 = 147,
-  AArch64_OP_GROUP_MemExtend_x_128 = 148,
-  AArch64_OP_GROUP_UImm12Offset_16 = 149,
-  AArch64_OP_GROUP_MemExtend_w_32 = 150,
-  AArch64_OP_GROUP_MemExtend_x_32 = 151,
-  AArch64_OP_GROUP_UImm12Offset_4 = 152,
-  AArch64_OP_GROUP_Matrix_0 = 153,
-  AArch64_OP_GROUP_TypedVectorList_0_0 = 154,
-  AArch64_OP_GROUP_SIMDType10Operand = 155,
-  AArch64_OP_GROUP_MRSSystemRegister = 156,
-  AArch64_OP_GROUP_MSRSystemRegister = 157,
-  AArch64_OP_GROUP_SystemPStateField = 158,
-  AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_s = 159,
-  AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_s = 160,
-  AArch64_OP_GROUP_PrefetchOp_0 = 161,
-  AArch64_OP_GROUP_RPRFMOperand = 162,
-  AArch64_OP_GROUP_GPR64as32 = 163,
-  AArch64_OP_GROUP_SysCROperand = 164,
-  AArch64_OP_GROUP_SyspXzrPair = 165,
-  AArch64_OP_GROUP_MatrixTileList = 166,

thirdparty/capstone/arch/AArch64/AArch64GenRegisterName.inc

@@ -1,714 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-/// getRegisterName - This method is automatically generated by tblgen
-/// from the register set description.  This returns the assembler name
-/// for the specified register.
-static const char *getRegisterName(unsigned RegNo, unsigned AltIdx)
-{
-
-
-#ifdef __GNUC__
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Woverlength-strings"
-#endif
-#ifndef CAPSTONE_DIET
-  static const char AsmStrsNoRegAltName[] = {
-  /* 0 */ "D7_D8_D9_D10\0"
-  /* 13 */ "Q7_Q8_Q9_Q10\0"
-  /* 26 */ "Z7_Z8_Z9_Z10\0"
-  /* 39 */ "b10\0"
-  /* 43 */ "d10\0"
-  /* 47 */ "h10\0"
-  /* 51 */ "p10\0"
-  /* 55 */ "q10\0"
-  /* 59 */ "s10\0"
-  /* 63 */ "w10\0"
-  /* 67 */ "x10\0"
-  /* 71 */ "z10\0"
-  /* 75 */ "D17_D18_D19_D20\0"
-  /* 91 */ "Q17_Q18_Q19_Q20\0"
-  /* 107 */ "Z17_Z18_Z19_Z20\0"
-  /* 123 */ "b20\0"
-  /* 127 */ "d20\0"
-  /* 131 */ "h20\0"
-  /* 135 */ "q20\0"
-  /* 139 */ "s20\0"
-  /* 143 */ "w20\0"
-  /* 147 */ "x20\0"
-  /* 151 */ "z20\0"
-  /* 155 */ "D27_D28_D29_D30\0"
-  /* 171 */ "Q27_Q28_Q29_Q30\0"
-  /* 187 */ "Z27_Z28_Z29_Z30\0"
-  /* 203 */ "b30\0"
-  /* 207 */ "d30\0"
-  /* 211 */ "h30\0"
-  /* 215 */ "q30\0"
-  /* 219 */ "s30\0"
-  /* 223 */ "w30\0"
-  /* 227 */ "x30\0"
-  /* 231 */ "z30\0"
-  /* 235 */ "D29_D30_D31_D0\0"
-  /* 250 */ "Q29_Q30_Q31_Q0\0"
-  /* 265 */ "Z29_Z30_Z31_Z0\0"
-  /* 280 */ "b0\0"
-  /* 283 */ "d0\0"
-  /* 286 */ "h0\0"
-  /* 289 */ "p0\0"
-  /* 292 */ "q0\0"
-  /* 295 */ "s0\0"
-  /* 298 */ "w0\0"
-  /* 301 */ "x0\0"
-  /* 304 */ "z0\0"
-  /* 307 */ "D8_D9_D10_D11\0"
-  /* 321 */ "Q8_Q9_Q10_Q11\0"
-  /* 335 */ "W10_W11\0"
-  /* 343 */ "X4_X5_X6_X7_X8_X9_X10_X11\0"
-  /* 369 */ "Z8_Z9_Z10_Z11\0"
-  /* 383 */ "b11\0"
-  /* 387 */ "d11\0"
-  /* 391 */ "h11\0"
-  /* 395 */ "p11\0"
-  /* 399 */ "q11\0"
-  /* 403 */ "s11\0"
-  /* 407 */ "w11\0"
-  /* 411 */ "x11\0"
-  /* 415 */ "z11\0"
-  /* 419 */ "D18_D19_D20_D21\0"
-  /* 435 */ "Q18_Q19_Q20_Q21\0"
-  /* 451 */ "W20_W21\0"
-  /* 459 */ "X14_X15_X16_X17_X18_X19_X20_X21\0"
-  /* 491 */ "Z18_Z19_Z20_Z21\0"
-  /* 507 */ "b21\0"
-  /* 511 */ "d21\0"
-  /* 515 */ "h21\0"
-  /* 519 */ "q21\0"
-  /* 523 */ "s21\0"
-  /* 527 */ "w21\0"
-  /* 531 */ "x21\0"
-  /* 535 */ "z21\0"
-  /* 539 */ "D28_D29_D30_D31\0"
-  /* 555 */ "Q28_Q29_Q30_Q31\0"
-  /* 571 */ "Z28_Z29_Z30_Z31\0"
-  /* 587 */ "b31\0"
-  /* 591 */ "d31\0"
-  /* 595 */ "h31\0"
-  /* 599 */ "q31\0"
-  /* 603 */ "s31\0"
-  /* 607 */ "z31\0"
-  /* 611 */ "D30_D31_D0_D1\0"
-  /* 625 */ "Q30_Q31_Q0_Q1\0"
-  /* 639 */ "W0_W1\0"
-  /* 645 */ "X0_X1\0"
-  /* 651 */ "Z30_Z31_Z0_Z1\0"
-  /* 665 */ "b1\0"
-  /* 668 */ "d1\0"
-  /* 671 */ "h1\0"
-  /* 674 */ "p1\0"
-  /* 677 */ "q1\0"
-  /* 680 */ "s1\0"
-  /* 683 */ "w1\0"
-  /* 686 */ "x1\0"
-  /* 689 */ "z1\0"
-  /* 692 */ "D9_D10_D11_D12\0"
-  /* 707 */ "Q9_Q10_Q11_Q12\0"
-  /* 722 */ "Z9_Z10_Z11_Z12\0"
-  /* 737 */ "b12\0"
-  /* 741 */ "d12\0"
-  /* 745 */ "h12\0"
-  /* 749 */ "p12\0"
-  /* 753 */ "q12\0"
-  /* 757 */ "s12\0"
-  /* 761 */ "w12\0"
-  /* 765 */ "x12\0"
-  /* 769 */ "z12\0"
-  /* 773 */ "D19_D20_D21_D22\0"
-  /* 789 */ "Q19_Q20_Q21_Q22\0"
-  /* 805 */ "Z19_Z20_Z21_Z22\0"
-  /* 821 */ "b22\0"
-  /* 825 */ "d22\0"
-  /* 829 */ "h22\0"
-  /* 833 */ "q22\0"
-  /* 837 */ "s22\0"
-  /* 841 */ "w22\0"
-  /* 845 */ "x22\0"
-  /* 849 */ "z22\0"
-  /* 853 */ "D31_D0_D1_D2\0"
-  /* 866 */ "Q31_Q0_Q1_Q2\0"
-  /* 879 */ "Z31_Z0_Z1_Z2\0"
-  /* 892 */ "b2\0"
-  /* 895 */ "d2\0"
-  /* 898 */ "h2\0"
-  /* 901 */ "p2\0"
-  /* 904 */ "q2\0"
-  /* 907 */ "s2\0"
-  /* 910 */ "w2\0"
-  /* 913 */ "x2\0"
-  /* 916 */ "z2\0"
-  /* 919 */ "D10_D11_D12_D13\0"
-  /* 935 */ "Q10_Q11_Q12_Q13\0"
-  /* 951 */ "W12_W13\0"
-  /* 959 */ "X6_X7_X8_X9_X10_X11_X12_X13\0"
-  /* 987 */ "Z10_Z11_Z12_Z13\0"
-  /* 1003 */ "b13\0"
-  /* 1007 */ "d13\0"
-  /* 1011 */ "h13\0"
-  /* 1015 */ "p13\0"
-  /* 1019 */ "q13\0"
-  /* 1023 */ "s13\0"
-  /* 1027 */ "w13\0"
-  /* 1031 */ "x13\0"
-  /* 1035 */ "z13\0"
-  /* 1039 */ "D20_D21_D22_D23\0"
-  /* 1055 */ "Q20_Q21_Q22_Q23\0"
-  /* 1071 */ "W22_W23\0"
-  /* 1079 */ "X16_X17_X18_X19_X20_X21_X22_X23\0"
-  /* 1111 */ "Z20_Z21_Z22_Z23\0"
-  /* 1127 */ "b23\0"
-  /* 1131 */ "d23\0"
-  /* 1135 */ "h23\0"
-  /* 1139 */ "q23\0"
-  /* 1143 */ "s23\0"
-  /* 1147 */ "w23\0"
-  /* 1151 */ "x23\0"
-  /* 1155 */ "z23\0"
-  /* 1159 */ "D0_D1_D2_D3\0"
-  /* 1171 */ "Q0_Q1_Q2_Q3\0"
-  /* 1183 */ "W2_W3\0"
-  /* 1189 */ "X2_X3\0"
-  /* 1195 */ "Z0_Z1_Z2_Z3\0"
-  /* 1207 */ "b3\0"
-  /* 1210 */ "d3\0"
-  /* 1213 */ "h3\0"
-  /* 1216 */ "p3\0"
-  /* 1219 */ "q3\0"
-  /* 1222 */ "s3\0"
-  /* 1225 */ "w3\0"
-  /* 1228 */ "x3\0"
-  /* 1231 */ "z3\0"
-  /* 1234 */ "D11_D12_D13_D14\0"
-  /* 1250 */ "Q11_Q12_Q13_Q14\0"
-  /* 1266 */ "Z11_Z12_Z13_Z14\0"
-  /* 1282 */ "b14\0"
-  /* 1286 */ "d14\0"
-  /* 1290 */ "h14\0"
-  /* 1294 */ "p14\0"
-  /* 1298 */ "q14\0"
-  /* 1302 */ "s14\0"
-  /* 1306 */ "w14\0"
-  /* 1310 */ "x14\0"
-  /* 1314 */ "z14\0"
-  /* 1318 */ "D21_D22_D23_D24\0"
-  /* 1334 */ "Q21_Q22_Q23_Q24\0"
-  /* 1350 */ "Z21_Z22_Z23_Z24\0"
-  /* 1366 */ "b24\0"
-  /* 1370 */ "d24\0"
-  /* 1374 */ "h24\0"
-  /* 1378 */ "q24\0"
-  /* 1382 */ "s24\0"
-  /* 1386 */ "w24\0"
-  /* 1390 */ "x24\0"
-  /* 1394 */ "z24\0"
-  /* 1398 */ "D1_D2_D3_D4\0"
-  /* 1410 */ "Q1_Q2_Q3_Q4\0"
-  /* 1422 */ "Z1_Z2_Z3_Z4\0"
-  /* 1434 */ "b4\0"
-  /* 1437 */ "d4\0"
-  /* 1440 */ "h4\0"
-  /* 1443 */ "p4\0"
-  /* 1446 */ "q4\0"
-  /* 1449 */ "s4\0"
-  /* 1452 */ "w4\0"
-  /* 1455 */ "x4\0"
-  /* 1458 */ "z4\0"
-  /* 1461 */ "D12_D13_D14_D15\0"
-  /* 1477 */ "Q12_Q13_Q14_Q15\0"
-  /* 1493 */ "W14_W15\0"
-  /* 1501 */ "X8_X9_X10_X11_X12_X13_X14_X15\0"
-  /* 1531 */ "Z12_Z13_Z14_Z15\0"
-  /* 1547 */ "b15\0"
-  /* 1551 */ "d15\0"
-  /* 1555 */ "h15\0"
-  /* 1559 */ "p15\0"
-  /* 1563 */ "q15\0"
-  /* 1567 */ "s15\0"
-  /* 1571 */ "w15\0"
-  /* 1575 */ "x15\0"
-  /* 1579 */ "z15\0"
-  /* 1583 */ "D22_D23_D24_D25\0"
-  /* 1599 */ "Q22_Q23_Q24_Q25\0"
-  /* 1615 */ "W24_W25\0"
-  /* 1623 */ "X18_X19_X20_X21_X22_X23_X24_X25\0"
-  /* 1655 */ "Z22_Z23_Z24_Z25\0"
-  /* 1671 */ "b25\0"
-  /* 1675 */ "d25\0"
-  /* 1679 */ "h25\0"
-  /* 1683 */ "q25\0"
-  /* 1687 */ "s25\0"
-  /* 1691 */ "w25\0"
-  /* 1695 */ "x25\0"
-  /* 1699 */ "z25\0"
-  /* 1703 */ "D2_D3_D4_D5\0"
-  /* 1715 */ "Q2_Q3_Q4_Q5\0"
-  /* 1727 */ "W4_W5\0"
-  /* 1733 */ "X4_X5\0"
-  /* 1739 */ "Z2_Z3_Z4_Z5\0"
-  /* 1751 */ "b5\0"
-  /* 1754 */ "d5\0"
-  /* 1757 */ "h5\0"
-  /* 1760 */ "p5\0"
-  /* 1763 */ "q5\0"
-  /* 1766 */ "s5\0"
-  /* 1769 */ "w5\0"
-  /* 1772 */ "x5\0"
-  /* 1775 */ "z5\0"
-  /* 1778 */ "D13_D14_D15_D16\0"
-  /* 1794 */ "Q13_Q14_Q15_Q16\0"
-  /* 1810 */ "Z13_Z14_Z15_Z16\0"
-  /* 1826 */ "b16\0"
-  /* 1830 */ "d16\0"
-  /* 1834 */ "h16\0"
-  /* 1838 */ "q16\0"
-  /* 1842 */ "s16\0"
-  /* 1846 */ "w16\0"
-  /* 1850 */ "x16\0"
-  /* 1854 */ "z16\0"
-  /* 1858 */ "D23_D24_D25_D26\0"
-  /* 1874 */ "Q23_Q24_Q25_Q26\0"
-  /* 1890 */ "Z23_Z24_Z25_Z26\0"
-  /* 1906 */ "b26\0"
-  /* 1910 */ "d26\0"
-  /* 1914 */ "h26\0"
-  /* 1918 */ "q26\0"
-  /* 1922 */ "s26\0"
-  /* 1926 */ "w26\0"
-  /* 1930 */ "x26\0"
-  /* 1934 */ "z26\0"
-  /* 1938 */ "D3_D4_D5_D6\0"
-  /* 1950 */ "Q3_Q4_Q5_Q6\0"
-  /* 1962 */ "Z3_Z4_Z5_Z6\0"
-  /* 1974 */ "b6\0"
-  /* 1977 */ "d6\0"
-  /* 1980 */ "h6\0"
-  /* 1983 */ "p6\0"
-  /* 1986 */ "q6\0"
-  /* 1989 */ "s6\0"
-  /* 1992 */ "w6\0"
-  /* 1995 */ "x6\0"
-  /* 1998 */ "z6\0"
-  /* 2001 */ "D14_D15_D16_D17\0"
-  /* 2017 */ "Q14_Q15_Q16_Q17\0"
-  /* 2033 */ "W16_W17\0"
-  /* 2041 */ "X10_X11_X12_X13_X14_X15_X16_X17\0"
-  /* 2073 */ "Z14_Z15_Z16_Z17\0"
-  /* 2089 */ "b17\0"
-  /* 2093 */ "d17\0"
-  /* 2097 */ "h17\0"
-  /* 2101 */ "q17\0"
-  /* 2105 */ "s17\0"
-  /* 2109 */ "w17\0"
-  /* 2113 */ "x17\0"
-  /* 2117 */ "z17\0"
-  /* 2121 */ "D24_D25_D26_D27\0"
-  /* 2137 */ "Q24_Q25_Q26_Q27\0"
-  /* 2153 */ "W26_W27\0"
-  /* 2161 */ "X20_X21_X22_X23_X24_X25_X26_X27\0"
-  /* 2193 */ "Z24_Z25_Z26_Z27\0"
-  /* 2209 */ "b27\0"
-  /* 2213 */ "d27\0"
-  /* 2217 */ "h27\0"
-  /* 2221 */ "q27\0"
-  /* 2225 */ "s27\0"
-  /* 2229 */ "w27\0"
-  /* 2233 */ "x27\0"
-  /* 2237 */ "z27\0"
-  /* 2241 */ "D4_D5_D6_D7\0"
-  /* 2253 */ "Q4_Q5_Q6_Q7\0"
-  /* 2265 */ "W6_W7\0"
-  /* 2271 */ "X0_X1_X2_X3_X4_X5_X6_X7\0"
-  /* 2295 */ "Z4_Z5_Z6_Z7\0"
-  /* 2307 */ "b7\0"
-  /* 2310 */ "d7\0"
-  /* 2313 */ "h7\0"
-  /* 2316 */ "p7\0"
-  /* 2319 */ "q7\0"
-  /* 2322 */ "s7\0"
-  /* 2325 */ "w7\0"
-  /* 2328 */ "x7\0"
-  /* 2331 */ "z7\0"
-  /* 2334 */ "D15_D16_D17_D18\0"
-  /* 2350 */ "Q15_Q16_Q17_Q18\0"
-  /* 2366 */ "Z15_Z16_Z17_Z18\0"
-  /* 2382 */ "b18\0"
-  /* 2386 */ "d18\0"
-  /* 2390 */ "h18\0"
-  /* 2394 */ "q18\0"
-  /* 2398 */ "s18\0"
-  /* 2402 */ "w18\0"
-  /* 2406 */ "x18\0"
-  /* 2410 */ "z18\0"
-  /* 2414 */ "D25_D26_D27_D28\0"
-  /* 2430 */ "Q25_Q26_Q27_Q28\0"
-  /* 2446 */ "Z25_Z26_Z27_Z28\0"
-  /* 2462 */ "b28\0"
-  /* 2466 */ "d28\0"
-  /* 2470 */ "h28\0"
-  /* 2474 */ "q28\0"
-  /* 2478 */ "s28\0"
-  /* 2482 */ "w28\0"
-  /* 2486 */ "x28\0"
-  /* 2490 */ "z28\0"
-  /* 2494 */ "D5_D6_D7_D8\0"
-  /* 2506 */ "Q5_Q6_Q7_Q8\0"
-  /* 2518 */ "Z5_Z6_Z7_Z8\0"
-  /* 2530 */ "b8\0"
-  /* 2533 */ "d8\0"
-  /* 2536 */ "h8\0"
-  /* 2539 */ "p8\0"
-  /* 2542 */ "q8\0"
-  /* 2545 */ "s8\0"
-  /* 2548 */ "w8\0"
-  /* 2551 */ "x8\0"
-  /* 2554 */ "z8\0"
-  /* 2557 */ "D16_D17_D18_D19\0"
-  /* 2573 */ "Q16_Q17_Q18_Q19\0"
-  /* 2589 */ "W18_W19\0"
-  /* 2597 */ "X12_X13_X14_X15_X16_X17_X18_X19\0"
-  /* 2629 */ "Z16_Z17_Z18_Z19\0"
-  /* 2645 */ "b19\0"
-  /* 2649 */ "d19\0"
-  /* 2653 */ "h19\0"
-  /* 2657 */ "q19\0"
-  /* 2661 */ "s19\0"
-  /* 2665 */ "w19\0"
-  /* 2669 */ "x19\0"
-  /* 2673 */ "z19\0"
-  /* 2677 */ "D26_D27_D28_D29\0"
-  /* 2693 */ "Q26_Q27_Q28_Q29\0"
-  /* 2709 */ "W28_W29\0"
-  /* 2717 */ "Z26_Z27_Z28_Z29\0"
-  /* 2733 */ "b29\0"
-  /* 2737 */ "d29\0"
-  /* 2741 */ "h29\0"
-  /* 2745 */ "q29\0"
-  /* 2749 */ "s29\0"
-  /* 2753 */ "w29\0"
-  /* 2757 */ "x29\0"
-  /* 2761 */ "z29\0"
-  /* 2765 */ "D6_D7_D8_D9\0"
-  /* 2777 */ "Q6_Q7_Q8_Q9\0"
-  /* 2789 */ "W8_W9\0"
-  /* 2795 */ "X2_X3_X4_X5_X6_X7_X8_X9\0"
-  /* 2819 */ "Z6_Z7_Z8_Z9\0"
-  /* 2831 */ "b9\0"
-  /* 2834 */ "d9\0"
-  /* 2837 */ "h9\0"
-  /* 2840 */ "p9\0"
-  /* 2843 */ "q9\0"
-  /* 2846 */ "s9\0"
-  /* 2849 */ "w9\0"
-  /* 2852 */ "x9\0"
-  /* 2855 */ "z9\0"
-  /* 2858 */ "X22_X23_X24_X25_X26_X27_X28_FP\0"
-  /* 2889 */ "W30_WZR\0"
-  /* 2897 */ "LR_XZR\0"
-  /* 2904 */ "za\0"
-  /* 2907 */ "za0.b\0"
-  /* 2913 */ "za0.d\0"
-  /* 2919 */ "za1.d\0"
-  /* 2925 */ "za2.d\0"
-  /* 2931 */ "za3.d\0"
-  /* 2937 */ "za4.d\0"
-  /* 2943 */ "za5.d\0"
-  /* 2949 */ "za6.d\0"
-  /* 2955 */ "za7.d\0"
-  /* 2961 */ "vg\0"
-  /* 2964 */ "za0.h\0"
-  /* 2970 */ "za1.h\0"
-  /* 2976 */ "z10_hi\0"
-  /* 2983 */ "z20_hi\0"
-  /* 2990 */ "z30_hi\0"
-  /* 2997 */ "z0_hi\0"
-  /* 3003 */ "z11_hi\0"
-  /* 3010 */ "z21_hi\0"
-  /* 3017 */ "z31_hi\0"
-  /* 3024 */ "z1_hi\0"
-  /* 3030 */ "z12_hi\0"
-  /* 3037 */ "z22_hi\0"
-  /* 3044 */ "z2_hi\0"
-  /* 3050 */ "z13_hi\0"
-  /* 3057 */ "z23_hi\0"
-  /* 3064 */ "z3_hi\0"
-  /* 3070 */ "z14_hi\0"
-  /* 3077 */ "z24_hi\0"
-  /* 3084 */ "z4_hi\0"
-  /* 3090 */ "z15_hi\0"
-  /* 3097 */ "z25_hi\0"
-  /* 3104 */ "z5_hi\0"
-  /* 3110 */ "z16_hi\0"
-  /* 3117 */ "z26_hi\0"
-  /* 3124 */ "z6_hi\0"
-  /* 3130 */ "z17_hi\0"
-  /* 3137 */ "z27_hi\0"
-  /* 3144 */ "z7_hi\0"
-  /* 3150 */ "z18_hi\0"
-  /* 3157 */ "z28_hi\0"
-  /* 3164 */ "z8_hi\0"
-  /* 3170 */ "z19_hi\0"
-  /* 3177 */ "z29_hi\0"
-  /* 3184 */ "z9_hi\0"
-  /* 3190 */ "wsp\0"
-  /* 3194 */ "za10.q\0"
-  /* 3201 */ "za0.q\0"
-  /* 3207 */ "za11.q\0"
-  /* 3214 */ "za1.q\0"
-  /* 3220 */ "za12.q\0"
-  /* 3227 */ "za2.q\0"
-  /* 3233 */ "za13.q\0"
-  /* 3240 */ "za3.q\0"
-  /* 3246 */ "za14.q\0"
-  /* 3253 */ "za4.q\0"
-  /* 3259 */ "za15.q\0"
-  /* 3266 */ "za5.q\0"
-  /* 3272 */ "za6.q\0"
-  /* 3278 */ "za7.q\0"
-  /* 3284 */ "za8.q\0"
-  /* 3290 */ "za9.q\0"
-  /* 3296 */ "ffr\0"
-  /* 3300 */ "wzr\0"
-  /* 3304 */ "xzr\0"
-  /* 3308 */ "za0.s\0"
-  /* 3314 */ "za1.s\0"
-  /* 3320 */ "za2.s\0"
-  /* 3326 */ "za3.s\0"
-  /* 3332 */ "nzcv\0"
-};
-#ifdef __GNUC__
-#pragma GCC diagnostic pop
-#endif
-
-  static const uint16_t RegAsmOffsetNoRegAltName[] = {
-    3296, 2757, 227, 3332, 3191, 2961, 3190, 3300, 3304, 2904, 280, 665, 892, 1207,
-    1434, 1751, 1974, 2307, 2530, 2831, 39, 383, 737, 1003, 1282, 1547, 1826, 2089,
-    2382, 2645, 123, 507, 821, 1127, 1366, 1671, 1906, 2209, 2462, 2733, 203, 587,
-    283, 668, 895, 1210, 1437, 1754, 1977, 2310, 2533, 2834, 43, 387, 741, 1007,
-    1286, 1551, 1830, 2093, 2386, 2649, 127, 511, 825, 1131, 1370, 1675, 1910, 2213,
-    2466, 2737, 207, 591, 286, 671, 898, 1213, 1440, 1757, 1980, 2313, 2536, 2837,
-    47, 391, 745, 1011, 1290, 1555, 1834, 2097, 2390, 2653, 131, 515, 829, 1135,
-    1374, 1679, 1914, 2217, 2470, 2741, 211, 595, 289, 674, 901, 1216, 1443, 1760,
-    1983, 2316, 2539, 2840, 51, 395, 749, 1015, 1294, 1559, 292, 677, 904, 1219,
-    1446, 1763, 1986, 2319, 2542, 2843, 55, 399, 753, 1019, 1298, 1563, 1838, 2101,
-    2394, 2657, 135, 519, 833, 1139, 1378, 1683, 1918, 2221, 2474, 2745, 215, 599,
-    295, 680, 907, 1222, 1449, 1766, 1989, 2322, 2545, 2846, 59, 403, 757, 1023,
-    1302, 1567, 1842, 2105, 2398, 2661, 139, 523, 837, 1143, 1382, 1687, 1922, 2225,
-    2478, 2749, 219, 603, 298, 683, 910, 1225, 1452, 1769, 1992, 2325, 2548, 2849,
-    63, 407, 761, 1027, 1306, 1571, 1846, 2109, 2402, 2665, 143, 527, 841, 1147,
-    1386, 1691, 1926, 2229, 2482, 2753, 223, 301, 686, 913, 1228, 1455, 1772, 1995,
-    2328, 2551, 2852, 67, 411, 765, 1031, 1310, 1575, 1850, 2113, 2406, 2669, 147,
-    531, 845, 1151, 1390, 1695, 1930, 2233, 2486, 304, 689, 916, 1231, 1458, 1775,
-    1998, 2331, 2554, 2855, 71, 415, 769, 1035, 1314, 1579, 1854, 2117, 2410, 2673,
-    151, 535, 849, 1155, 1394, 1699, 1934, 2237, 2490, 2761, 231, 607, 2907, 2913,
-    2919, 2925, 2931, 2937, 2943, 2949, 2955, 2964, 2970, 3201, 3214, 3227, 3240, 3253,
-    3266, 3272, 3278, 3284, 3290, 3194, 3207, 3220, 3233, 3246, 3259, 3308, 3314, 3320,
-    3326, 2997, 3024, 3044, 3064, 3084, 3104, 3124, 3144, 3164, 3184, 2976, 3003, 3030,
-    3050, 3070, 3090, 3110, 3130, 3150, 3170, 2983, 3010, 3037, 3057, 3077, 3097, 3117,
-    3137, 3157, 3177, 2990, 3017, 619, 860, 1165, 1404, 1709, 1944, 2247, 2500, 2771,
-    6, 313, 699, 927, 1242, 1469, 1786, 2009, 2342, 2565, 83, 427, 781, 1047,
-    1326, 1591, 1866, 2129, 2422, 2685, 163, 547, 243, 1159, 1398, 1703, 1938, 2241,
-    2494, 2765, 0, 307, 692, 919, 1234, 1461, 1778, 2001, 2334, 2557, 75, 419,
-    773, 1039, 1318, 1583, 1858, 2121, 2414, 2677, 155, 539, 235, 611, 853, 857,
-    1162, 1401, 1706, 1941, 2244, 2497, 2768, 3, 310, 695, 923, 1238, 1465, 1782,
-    2005, 2338, 2561, 79, 423, 777, 1043, 1322, 1587, 1862, 2125, 2418, 2681, 159,
-    543, 239, 615, 633, 873, 1177, 1416, 1721, 1956, 2259, 2512, 2783, 19, 327,
-    714, 943, 1258, 1485, 1802, 2025, 2358, 2581, 99, 443, 797, 1063, 1342, 1607,
-    1882, 2145, 2438, 2701, 179, 563, 258, 1171, 1410, 1715, 1950, 2253, 2506, 2777,
-    13, 321, 707, 935, 1250, 1477, 1794, 2017, 2350, 2573, 91, 435, 789, 1055,
-    1334, 1599, 1874, 2137, 2430, 2693, 171, 555, 250, 625, 866, 870, 1174, 1413,
-    1718, 1953, 2256, 2509, 2780, 16, 324, 710, 939, 1254, 1481, 1798, 2021, 2354,
-    2577, 95, 439, 793, 1059, 1338, 1603, 1878, 2141, 2434, 2697, 175, 559, 254,
-    629, 2858, 2271, 2795, 343, 959, 1501, 2041, 2597, 459, 1079, 1623, 2161, 2889,
-    639, 1183, 1727, 2265, 2789, 335, 951, 1493, 2033, 2589, 451, 1071, 1615, 2153,
-    2709, 2897, 2882, 645, 1189, 1733, 2289, 2813, 361, 979, 1523, 2065, 2621, 483,
-    1103, 1647, 2185, 659, 886, 1201, 1428, 1745, 1968, 2301, 2524, 2825, 32, 375,
-    729, 995, 1274, 1539, 1818, 2081, 2374, 2637, 115, 499, 813, 1119, 1358, 1663,
-    1898, 2201, 2454, 2725, 195, 579, 273, 1195, 1422, 1739, 1962, 2295, 2518, 2819,
-    26, 369, 722, 987, 1266, 1531, 1810, 2073, 2366, 2629, 107, 491, 805, 1111,
-    1350, 1655, 1890, 2193, 2446, 2717, 187, 571, 265, 651, 879, 883, 1198, 1425,
-    1742, 1965, 2298, 2521, 2822, 29, 372, 725, 991, 1270, 1535, 1814, 2077, 2370,
-    2633, 111, 495, 809, 1115, 1354, 1659, 1894, 2197, 2450, 2721, 191, 575, 269,
-    655,
-  };
-
-
-#ifdef __GNUC__
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Woverlength-strings"
-#endif
-  static const char AsmStrsvlist1[] = {
-  /* 0 */ "\0"
-};
-#ifdef __GNUC__
-#pragma GCC diagnostic pop
-#endif
-
-  static const uint8_t RegAsmOffsetvlist1[] = {
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0,
-  };
-
-
-#ifdef __GNUC__
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Woverlength-strings"
-#endif
-  static const char AsmStrsvreg[] = {
-  /* 0 */ "v10\0"
-  /* 4 */ "v20\0"
-  /* 8 */ "v30\0"
-  /* 12 */ "v0\0"
-  /* 15 */ "v11\0"
-  /* 19 */ "v21\0"
-  /* 23 */ "v31\0"
-  /* 27 */ "v1\0"
-  /* 30 */ "v12\0"
-  /* 34 */ "v22\0"
-  /* 38 */ "v2\0"
-  /* 41 */ "v13\0"
-  /* 45 */ "v23\0"
-  /* 49 */ "v3\0"
-  /* 52 */ "v14\0"
-  /* 56 */ "v24\0"
-  /* 60 */ "v4\0"
-  /* 63 */ "v15\0"
-  /* 67 */ "v25\0"
-  /* 71 */ "v5\0"
-  /* 74 */ "v16\0"
-  /* 78 */ "v26\0"
-  /* 82 */ "v6\0"
-  /* 85 */ "v17\0"
-  /* 89 */ "v27\0"
-  /* 93 */ "v7\0"
-  /* 96 */ "v18\0"
-  /* 100 */ "v28\0"
-  /* 104 */ "v8\0"
-  /* 107 */ "v19\0"
-  /* 111 */ "v29\0"
-  /* 115 */ "v9\0"
-};
-#ifdef __GNUC__
-#pragma GCC diagnostic pop
-#endif
-
-  static const uint8_t RegAsmOffsetvreg[] = {
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41,
-    52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89,
-    100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49,
-    60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85,
-    96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104,
-    115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34,
-    45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60,
-    71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96,
-    107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12,
-    27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52,
-    63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100,
-    111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0,
-    15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56,
-    67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82,
-    93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4,
-    19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38,
-    49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74,
-    85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8,
-    23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    3,
-  };
-
-  switch(AltIdx) {
-  default:
-    return (const char *)(sizeof(RegAsmOffsetvreg)/sizeof(RegAsmOffsetvreg[0]));
-  case AArch64_NoRegAltName:
-    return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
-  case AArch64_vlist1:
-    return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1];
-  case AArch64_vreg:
-    return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1];
-  }
-#else
-  return NULL;
-#endif
-}

thirdparty/capstone/arch/AArch64/AArch64GenSubtargetInfo.inc

@@ -1,298 +0,0 @@
-/* Capstone Disassembly Engine, https://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2024 */
-/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
-
-/* LLVM-commit: <commit> */
-/* LLVM-tag: <tag> */
-
-/* Do not edit. */
-
-/* Capstone's LLVM TableGen Backends: */
-/* https://github.com/capstone-engine/llvm-capstone */
-
-#ifdef GET_SUBTARGETINFO_ENUM
-#undef GET_SUBTARGETINFO_ENUM
-
-enum {
-  AArch64_FeatureAES = 0,
-  AArch64_FeatureALULSLFast = 1,
-  AArch64_FeatureAM = 2,
-  AArch64_FeatureAMVS = 3,
-  AArch64_FeatureAddrLSLFast = 4,
-  AArch64_FeatureAggressiveFMA = 5,
-  AArch64_FeatureAll = 6,
-  AArch64_FeatureAltFPCmp = 7,
-  AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 8,
-  AArch64_FeatureAppleA7SysReg = 9,
-  AArch64_FeatureArithmeticBccFusion = 10,
-  AArch64_FeatureArithmeticCbzFusion = 11,
-  AArch64_FeatureAscendStoreAddress = 12,
-  AArch64_FeatureB16B16 = 13,
-  AArch64_FeatureBF16 = 14,
-  AArch64_FeatureBRBE = 15,
-  AArch64_FeatureBalanceFPOps = 16,
-  AArch64_FeatureBranchTargetId = 17,
-  AArch64_FeatureCCIDX = 18,
-  AArch64_FeatureCCPP = 19,
-  AArch64_FeatureCHK = 20,
-  AArch64_FeatureCLRBHB = 21,
-  AArch64_FeatureCONTEXTIDREL2 = 22,
-  AArch64_FeatureCPA = 23,
-  AArch64_FeatureCRC = 24,
-  AArch64_FeatureCSSC = 25,
-  AArch64_FeatureCacheDeepPersist = 26,
-  AArch64_FeatureCallSavedX8 = 27,
-  AArch64_FeatureCallSavedX9 = 28,
-  AArch64_FeatureCallSavedX10 = 29,
-  AArch64_FeatureCallSavedX11 = 30,
-  AArch64_FeatureCallSavedX12 = 31,
-  AArch64_FeatureCallSavedX13 = 32,
-  AArch64_FeatureCallSavedX14 = 33,
-  AArch64_FeatureCallSavedX15 = 34,
-  AArch64_FeatureCallSavedX18 = 35,
-  AArch64_FeatureCmpBccFusion = 36,
-  AArch64_FeatureComplxNum = 37,
-  AArch64_FeatureCrypto = 38,
-  AArch64_FeatureD128 = 39,
-  AArch64_FeatureDIT = 40,
-  AArch64_FeatureDisableLatencySchedHeuristic = 41,
-  AArch64_FeatureDisableLdp = 42,
-  AArch64_FeatureDisableStp = 43,
-  AArch64_FeatureDotProd = 44,
-  AArch64_FeatureEL2VMSA = 45,
-  AArch64_FeatureEL3 = 46,
-  AArch64_FeatureETE = 47,
-  AArch64_FeatureEnableSelectOptimize = 48,
-  AArch64_FeatureEnhancedCounterVirtualization = 49,
-  AArch64_FeatureExperimentalZeroingPseudos = 50,
-  AArch64_FeatureExynosCheapAsMoveHandling = 51,
-  AArch64_FeatureFAMINMAX = 52,
-  AArch64_FeatureFMV = 53,
-  AArch64_FeatureFP8 = 54,
-  AArch64_FeatureFP8DOT2 = 55,
-  AArch64_FeatureFP8DOT4 = 56,
-  AArch64_FeatureFP8FMA = 57,
-  AArch64_FeatureFP16FML = 58,
-  AArch64_FeatureFPARMv8 = 59,
-  AArch64_FeatureFPMR = 60,
-  AArch64_FeatureFRInt3264 = 61,
-  AArch64_FeatureFineGrainedTraps = 62,
-  AArch64_FeatureFixCortexA53_835769 = 63,
-  AArch64_FeatureFlagM = 64,
-  AArch64_FeatureForce32BitJumpTables = 65,
-  AArch64_FeatureFullFP16 = 66,
-  AArch64_FeatureFuseAES = 67,
-  AArch64_FeatureFuseAddSub2RegAndConstOne = 68,
-  AArch64_FeatureFuseAddress = 69,
-  AArch64_FeatureFuseAdrpAdd = 70,
-  AArch64_FeatureFuseArithmeticLogic = 71,
-  AArch64_FeatureFuseCCSelect = 72,
-  AArch64_FeatureFuseCryptoEOR = 73,
-  AArch64_FeatureFuseLiterals = 74,
-  AArch64_FeatureGCS = 75,
-  AArch64_FeatureHBC = 76,
-  AArch64_FeatureHCX = 77,
-  AArch64_FeatureHardenSlsBlr = 78,
-  AArch64_FeatureHardenSlsNoComdat = 79,
-  AArch64_FeatureHardenSlsRetBr = 80,
-  AArch64_FeatureITE = 81,
-  AArch64_FeatureJS = 82,
-  AArch64_FeatureLOR = 83,
-  AArch64_FeatureLS64 = 84,
-  AArch64_FeatureLSE = 85,
-  AArch64_FeatureLSE2 = 86,
-  AArch64_FeatureLSE128 = 87,
-  AArch64_FeatureLUT = 88,
-  AArch64_FeatureLdpAlignedOnly = 89,
-  AArch64_FeatureMEC = 90,
-  AArch64_FeatureMOPS = 91,
-  AArch64_FeatureMPAM = 92,
-  AArch64_FeatureMTE = 93,
-  AArch64_FeatureMatMulFP32 = 94,
-  AArch64_FeatureMatMulFP64 = 95,
-  AArch64_FeatureMatMulInt8 = 96,
-  AArch64_FeatureNEON = 97,
-  AArch64_FeatureNMI = 98,
-  AArch64_FeatureNV = 99,
-  AArch64_FeatureNoBTIAtReturnTwice = 100,
-  AArch64_FeatureNoNegativeImmediates = 101,
-  AArch64_FeatureNoSVEFPLD1R = 102,
-  AArch64_FeatureNoZCZeroingFP = 103,
-  AArch64_FeatureOutlineAtomics = 104,
-  AArch64_FeaturePAN = 105,
-  AArch64_FeaturePAN_RWV = 106,
-  AArch64_FeaturePAuth = 107,
-  AArch64_FeaturePAuthLR = 108,
-  AArch64_FeaturePRFM_SLC = 109,
-  AArch64_FeaturePerfMon = 110,
-  AArch64_FeaturePostRAScheduler = 111,
-  AArch64_FeaturePredRes = 112,
-  AArch64_FeaturePredictableSelectIsExpensive = 113,
-  AArch64_FeaturePsUAO = 114,
-  AArch64_FeatureRAS = 115,
-  AArch64_FeatureRASv2 = 116,
-  AArch64_FeatureRCPC = 117,
-  AArch64_FeatureRCPC3 = 118,
-  AArch64_FeatureRCPC_IMMO = 119,
-  AArch64_FeatureRDM = 120,
-  AArch64_FeatureRME = 121,
-  AArch64_FeatureRandGen = 122,
-  AArch64_FeatureReserveX1 = 123,
-  AArch64_FeatureReserveX2 = 124,
-  AArch64_FeatureReserveX3 = 125,
-  AArch64_FeatureReserveX4 = 126,
-  AArch64_FeatureReserveX5 = 127,
-  AArch64_FeatureReserveX6 = 128,
-  AArch64_FeatureReserveX7 = 129,
-  AArch64_FeatureReserveX9 = 130,
-  AArch64_FeatureReserveX10 = 131,
-  AArch64_FeatureReserveX11 = 132,
-  AArch64_FeatureReserveX12 = 133,
-  AArch64_FeatureReserveX13 = 134,
-  AArch64_FeatureReserveX14 = 135,
-  AArch64_FeatureReserveX15 = 136,
-  AArch64_FeatureReserveX18 = 137,
-  AArch64_FeatureReserveX20 = 138,
-  AArch64_FeatureReserveX21 = 139,
-  AArch64_FeatureReserveX22 = 140,
-  AArch64_FeatureReserveX23 = 141,
-  AArch64_FeatureReserveX24 = 142,
-  AArch64_FeatureReserveX25 = 143,
-  AArch64_FeatureReserveX26 = 144,
-  AArch64_FeatureReserveX27 = 145,
-  AArch64_FeatureReserveX28 = 146,
-  AArch64_FeatureReserveX30 = 147,
-  AArch64_FeatureSB = 148,
-  AArch64_FeatureSEL2 = 149,
-  AArch64_FeatureSHA2 = 150,
-  AArch64_FeatureSHA3 = 151,
-  AArch64_FeatureSM4 = 152,
-  AArch64_FeatureSME = 153,
-  AArch64_FeatureSME2 = 154,
-  AArch64_FeatureSME2p1 = 155,
-  AArch64_FeatureSMEF8F16 = 156,
-  AArch64_FeatureSMEF8F32 = 157,
-  AArch64_FeatureSMEF16F16 = 158,
-  AArch64_FeatureSMEF64F64 = 159,
-  AArch64_FeatureSMEFA64 = 160,
-  AArch64_FeatureSMEI16I64 = 161,
-  AArch64_FeatureSME_LUTv2 = 162,
-  AArch64_FeatureSPE = 163,
-  AArch64_FeatureSPECRES2 = 164,
-  AArch64_FeatureSPE_EEF = 165,
-  AArch64_FeatureSSBS = 166,
-  AArch64_FeatureSSVE_FP8DOT2 = 167,
-  AArch64_FeatureSSVE_FP8DOT4 = 168,
-  AArch64_FeatureSSVE_FP8FMA = 169,
-  AArch64_FeatureSVE = 170,
-  AArch64_FeatureSVE2 = 171,
-  AArch64_FeatureSVE2AES = 172,
-  AArch64_FeatureSVE2BitPerm = 173,
-  AArch64_FeatureSVE2SHA3 = 174,
-  AArch64_FeatureSVE2SM4 = 175,
-  AArch64_FeatureSVE2p1 = 176,
-  AArch64_FeatureSlowMisaligned128Store = 177,
-  AArch64_FeatureSlowPaired128 = 178,
-  AArch64_FeatureSlowSTRQro = 179,
-  AArch64_FeatureSpecRestrict = 180,
-  AArch64_FeatureStorePairSuppress = 181,
-  AArch64_FeatureStpAlignedOnly = 182,
-  AArch64_FeatureStrictAlign = 183,
-  AArch64_FeatureTHE = 184,
-  AArch64_FeatureTLBIW = 185,
-  AArch64_FeatureTLB_RMI = 186,
-  AArch64_FeatureTME = 187,
-  AArch64_FeatureTRACEV8_4 = 188,
-  AArch64_FeatureTRBE = 189,
-  AArch64_FeatureTaggedGlobals = 190,
-  AArch64_FeatureUseEL1ForTP = 191,
-  AArch64_FeatureUseEL2ForTP = 192,
-  AArch64_FeatureUseEL3ForTP = 193,
-  AArch64_FeatureUseROEL0ForTP = 194,
-  AArch64_FeatureUseRSqrt = 195,
-  AArch64_FeatureUseScalarIncVL = 196,
-  AArch64_FeatureVH = 197,
-  AArch64_FeatureWFxT = 198,
-  AArch64_FeatureXS = 199,
-  AArch64_FeatureZCRegMove = 200,
-  AArch64_FeatureZCZeroing = 201,
-  AArch64_FeatureZCZeroingFPWorkaround = 202,
-  AArch64_FeatureZCZeroingGP = 203,
-  AArch64_HasV8_0aOps = 204,
-  AArch64_HasV8_0rOps = 205,
-  AArch64_HasV8_1aOps = 206,
-  AArch64_HasV8_2aOps = 207,
-  AArch64_HasV8_3aOps = 208,
-  AArch64_HasV8_4aOps = 209,
-  AArch64_HasV8_5aOps = 210,
-  AArch64_HasV8_6aOps = 211,
-  AArch64_HasV8_7aOps = 212,
-  AArch64_HasV8_8aOps = 213,
-  AArch64_HasV8_9aOps = 214,
-  AArch64_HasV9_0aOps = 215,
-  AArch64_HasV9_1aOps = 216,
-  AArch64_HasV9_2aOps = 217,
-  AArch64_HasV9_3aOps = 218,
-  AArch64_HasV9_4aOps = 219,
-  AArch64_HasV9_5aOps = 220,
-  AArch64_TuneA35 = 221,
-  AArch64_TuneA53 = 222,
-  AArch64_TuneA55 = 223,
-  AArch64_TuneA57 = 224,
-  AArch64_TuneA64FX = 225,
-  AArch64_TuneA65 = 226,
-  AArch64_TuneA72 = 227,
-  AArch64_TuneA73 = 228,
-  AArch64_TuneA75 = 229,
-  AArch64_TuneA76 = 230,
-  AArch64_TuneA77 = 231,
-  AArch64_TuneA78 = 232,
-  AArch64_TuneA78C = 233,
-  AArch64_TuneA510 = 234,
-  AArch64_TuneA520 = 235,
-  AArch64_TuneA710 = 236,
-  AArch64_TuneA715 = 237,
-  AArch64_TuneA720 = 238,
-  AArch64_TuneAmpere1 = 239,
-  AArch64_TuneAmpere1A = 240,
-  AArch64_TuneAmpere1B = 241,
-  AArch64_TuneAppleA7 = 242,
-  AArch64_TuneAppleA10 = 243,
-  AArch64_TuneAppleA11 = 244,
-  AArch64_TuneAppleA12 = 245,
-  AArch64_TuneAppleA13 = 246,
-  AArch64_TuneAppleA14 = 247,
-  AArch64_TuneAppleA15 = 248,
-  AArch64_TuneAppleA16 = 249,
-  AArch64_TuneAppleA17 = 250,
-  AArch64_TuneCarmel = 251,
-  AArch64_TuneExynosM3 = 252,
-  AArch64_TuneExynosM4 = 253,
-  AArch64_TuneFalkor = 254,
-  AArch64_TuneKryo = 255,
-  AArch64_TuneNeoverse512TVB = 256,
-  AArch64_TuneNeoverseE1 = 257,
-  AArch64_TuneNeoverseN1 = 258,
-  AArch64_TuneNeoverseN2 = 259,
-  AArch64_TuneNeoverseV1 = 260,
-  AArch64_TuneNeoverseV2 = 261,
-  AArch64_TuneR82 = 262,
-  AArch64_TuneSaphira = 263,
-  AArch64_TuneTSV110 = 264,
-  AArch64_TuneThunderX = 265,
-  AArch64_TuneThunderX2T99 = 266,
-  AArch64_TuneThunderX3T110 = 267,
-  AArch64_TuneThunderXT81 = 268,
-  AArch64_TuneThunderXT83 = 269,
-  AArch64_TuneThunderXT88 = 270,
-  AArch64_TuneX1 = 271,
-  AArch64_TuneX2 = 272,
-  AArch64_TuneX3 = 273,
-  AArch64_TuneX4 = 274,
-  AArch64_NumSubtargetFeatures = 275
-};
-#endif // GET_SUBTARGETINFO_ENUM
-
-
-

thirdparty/capstone/arch/AArch64/AArch64InstPrinter.h

@@ -1,350 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
-/* Automatically translated source file from LLVM. */
-
-/* LLVM-commit: <commit> */
-/* LLVM-tag: <tag> */
-
-/* Only small edits allowed. */
-/* For multiple similar edits, please create a Patch for the translator. */
-
-/* Capstone's C++ file translator: */
-/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
-
-//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This class prints an AArch64 MCInst to a .s file.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
-#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
-
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-#include <capstone/platform.h>
-
-#include "AArch64Mapping.h"
-
-#include "../../MCInst.h"
-#include "../../MCRegisterInfo.h"
-#include "../../MCInstPrinter.h"
-#include "../../SStream.h"
-#include "../../utils.h"
-
-#define CONCAT(a, b) CONCAT_(a, b)
-#define CONCAT_(a, b) a##_##b
-#define CHAR(c) #c[0]
-
-void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
-void printRegName(SStream *OS, unsigned Reg);
-void printRegNameAlt(SStream *OS, unsigned Reg, unsigned AltIdx);
-// Autogenerated by tblgen.
-const char *getRegName(unsigned Reg);
-bool printSysAlias(MCInst *MI, SStream *O);
-bool printSyspAlias(MCInst *MI, SStream *O);
-bool printRangePrefetchAlias(MCInst *MI, SStream *O, const char *Annot);
-// Operand printers
-void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
-void printImm(MCInst *MI, unsigned OpNo, SStream *O);
-void printImmHex(MCInst *MI, unsigned OpNo, SStream *O);
-#define DECLARE_printSImm(Size) \
-	void CONCAT(printSImm, Size)(MCInst * MI, unsigned OpNo, SStream *O);
-DECLARE_printSImm(16);
-DECLARE_printSImm(8);
-
-#define DECLARE_printImmSVE(T) void CONCAT(printImmSVE, T)(T Val, SStream * O);
-DECLARE_printImmSVE(int16_t);
-DECLARE_printImmSVE(int8_t);
-DECLARE_printImmSVE(int64_t);
-DECLARE_printImmSVE(int32_t);
-DECLARE_printImmSVE(uint16_t);
-DECLARE_printImmSVE(uint8_t);
-DECLARE_printImmSVE(uint64_t);
-DECLARE_printImmSVE(uint32_t);
-
-void printPostIncOperand(MCInst *MI, unsigned OpNo, unsigned Imm, SStream *O);
-#define DEFINE_printPostIncOperand(Amount) \
-	static inline void CONCAT(printPostIncOperand, Amount)( \
-		MCInst * MI, unsigned OpNo, SStream *O) \
-	{ \
-		add_cs_detail(MI, \
-			      CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
-			      OpNo, Amount); \
-		printPostIncOperand(MI, OpNo, Amount, O); \
-	}
-DEFINE_printPostIncOperand(64);
-DEFINE_printPostIncOperand(32);
-DEFINE_printPostIncOperand(16);
-DEFINE_printPostIncOperand(8);
-DEFINE_printPostIncOperand(1);
-DEFINE_printPostIncOperand(4);
-DEFINE_printPostIncOperand(2);
-DEFINE_printPostIncOperand(48);
-DEFINE_printPostIncOperand(24);
-DEFINE_printPostIncOperand(3);
-DEFINE_printPostIncOperand(12);
-DEFINE_printPostIncOperand(6);
-
-void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O);
-void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O);
-void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printLogicalImm(T) \
-	void CONCAT(printLogicalImm, T)(MCInst * MI, unsigned OpNum, \
-					SStream *O);
-DECLARE_printLogicalImm(int64_t);
-DECLARE_printLogicalImm(int32_t);
-DECLARE_printLogicalImm(int8_t);
-DECLARE_printLogicalImm(int16_t);
-
-void printShifter(MCInst *MI, unsigned OpNum, SStream *O);
-void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O);
-void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O);
-void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O);
-
-void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
-		    unsigned Width);
-void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
-		    unsigned Width);
-#define DEFINE_printMemExtend(SrcRegKind, Width) \
-	static inline void CONCAT(printMemExtend, CONCAT(SrcRegKind, Width))( \
-		MCInst * MI, unsigned OpNum, SStream *O) \
-	{ \
-		add_cs_detail( \
-			MI, \
-			CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
-			       Width), \
-			OpNum, CHAR(SrcRegKind), Width); \
-		printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
-	}
-DEFINE_printMemExtend(w, 8);
-DEFINE_printMemExtend(x, 8);
-DEFINE_printMemExtend(w, 64);
-DEFINE_printMemExtend(x, 64);
-DEFINE_printMemExtend(w, 16);
-DEFINE_printMemExtend(x, 16);
-DEFINE_printMemExtend(w, 128);
-DEFINE_printMemExtend(x, 128);
-DEFINE_printMemExtend(w, 32);
-DEFINE_printMemExtend(x, 32);
-
-#define DECLARE_printRegWithShiftExtend(SignedExtend, ExtWidth, SrcRegKind, \
-					Suffix) \
-	void CONCAT(printRegWithShiftExtend, \
-		    CONCAT(SignedExtend, \
-			   CONCAT(ExtWidth, CONCAT(SrcRegKind, Suffix))))( \
-		MCInst * MI, unsigned OpNum, SStream *O);
-DECLARE_printRegWithShiftExtend(false, 8, x, d);
-DECLARE_printRegWithShiftExtend(true, 8, w, d);
-DECLARE_printRegWithShiftExtend(false, 8, w, d);
-DECLARE_printRegWithShiftExtend(false, 8, x, 0);
-DECLARE_printRegWithShiftExtend(true, 8, w, s);
-DECLARE_printRegWithShiftExtend(false, 8, w, s);
-DECLARE_printRegWithShiftExtend(false, 64, x, d);
-DECLARE_printRegWithShiftExtend(true, 64, w, d);
-DECLARE_printRegWithShiftExtend(false, 64, w, d);
-DECLARE_printRegWithShiftExtend(false, 64, x, 0);
-DECLARE_printRegWithShiftExtend(true, 64, w, s);
-DECLARE_printRegWithShiftExtend(false, 64, w, s);
-DECLARE_printRegWithShiftExtend(false, 16, x, d);
-DECLARE_printRegWithShiftExtend(true, 16, w, d);
-DECLARE_printRegWithShiftExtend(false, 16, w, d);
-DECLARE_printRegWithShiftExtend(false, 16, x, 0);
-DECLARE_printRegWithShiftExtend(true, 16, w, s);
-DECLARE_printRegWithShiftExtend(false, 16, w, s);
-DECLARE_printRegWithShiftExtend(false, 32, x, d);
-DECLARE_printRegWithShiftExtend(true, 32, w, d);
-DECLARE_printRegWithShiftExtend(false, 32, w, d);
-DECLARE_printRegWithShiftExtend(false, 32, x, 0);
-DECLARE_printRegWithShiftExtend(true, 32, w, s);
-DECLARE_printRegWithShiftExtend(false, 32, w, s);
-DECLARE_printRegWithShiftExtend(false, 8, x, s);
-DECLARE_printRegWithShiftExtend(false, 16, x, s);
-DECLARE_printRegWithShiftExtend(false, 32, x, s);
-DECLARE_printRegWithShiftExtend(false, 64, x, s);
-DECLARE_printRegWithShiftExtend(false, 128, x, 0);
-
-void printCondCode(MCInst *MI, unsigned OpNum, SStream *O);
-void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O);
-void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
-		       SStream *O);
-void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
-void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
-#define DEFINE_printUImm12Offset(Scale) \
-	static inline void CONCAT(printUImm12Offset, Scale)( \
-		MCInst * MI, unsigned OpNum, SStream *O) \
-	{ \
-		add_cs_detail(MI, \
-			      CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
-			      OpNum, Scale); \
-		printUImm12Offset(MI, OpNum, Scale, O); \
-	}
-DEFINE_printUImm12Offset(1);
-DEFINE_printUImm12Offset(8);
-DEFINE_printUImm12Offset(2);
-DEFINE_printUImm12Offset(16);
-DEFINE_printUImm12Offset(4);
-
-void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printImmScale(Scale) \
-	void CONCAT(printImmScale, Scale)(MCInst * MI, unsigned OpNum, \
-					  SStream *O);
-DECLARE_printImmScale(8);
-DECLARE_printImmScale(2);
-DECLARE_printImmScale(4);
-DECLARE_printImmScale(16);
-DECLARE_printImmScale(32);
-DECLARE_printImmScale(3);
-
-#define DECLARE_printImmRangeScale(Scale, Offset) \
-	void CONCAT(printImmRangeScale, CONCAT(Scale, Offset))( \
-		MCInst * MI, unsigned OpNum, SStream *O);
-DECLARE_printImmRangeScale(2, 1);
-DECLARE_printImmRangeScale(4, 3);
-
-#define DECLARE_printPrefetchOp(IsSVEPrefetch) \
-	void CONCAT(printPrefetchOp, \
-		    IsSVEPrefetch)(MCInst * MI, unsigned OpNum, SStream *O);
-DECLARE_printPrefetchOp(true);
-DECLARE_printPrefetchOp(false);
-
-void printRPRFMOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O);
-void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorList(MCInst *MI, unsigned OpNum, SStream *O,
-		     const char *LayoutSuffix);
-void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O);
-/// (i.e. attached to the instruction rather than the registers).
-/// Print a list of vector registers where the type suffix is implicit
-void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printTypedVectorList(NumLanes, LaneKind) \
-	void CONCAT(printTypedVectorList, CONCAT(NumLanes, LaneKind))( \
-		MCInst * MI, unsigned OpNum, SStream *O);
-DECLARE_printTypedVectorList(0, b);
-DECLARE_printTypedVectorList(0, d);
-DECLARE_printTypedVectorList(0, h);
-DECLARE_printTypedVectorList(0, s);
-DECLARE_printTypedVectorList(0, q);
-DECLARE_printTypedVectorList(16, b);
-DECLARE_printTypedVectorList(1, d);
-DECLARE_printTypedVectorList(2, d);
-DECLARE_printTypedVectorList(2, s);
-DECLARE_printTypedVectorList(4, h);
-DECLARE_printTypedVectorList(4, s);
-DECLARE_printTypedVectorList(8, b);
-DECLARE_printTypedVectorList(8, h);
-DECLARE_printTypedVectorList(0, 0);
-
-#define DECLARE_printVectorIndex(Scale) \
-	void CONCAT(printVectorIndex, Scale)(MCInst * MI, unsigned OpNum, \
-					     SStream *O);
-DECLARE_printVectorIndex(1);
-DECLARE_printVectorIndex(8);
-
-void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
-		       SStream *O);
-void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O);
-void printBarriernXSOption(MCInst *MI, unsigned OpNum, SStream *O);
-void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
-void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
-void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O);
-void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printPredicateAsCounter(EltSize) \
-	void CONCAT(printPredicateAsCounter, \
-		    EltSize)(MCInst * MI, unsigned OpNum, SStream *O);
-DECLARE_printPredicateAsCounter(8);
-DECLARE_printPredicateAsCounter(64);
-DECLARE_printPredicateAsCounter(16);
-DECLARE_printPredicateAsCounter(32);
-DECLARE_printPredicateAsCounter(0);
-
-#define DECLARE_printGPRSeqPairsClassOperand(size) \
-	void CONCAT(printGPRSeqPairsClassOperand, \
-		    size)(MCInst * MI, unsigned OpNum, SStream *O);
-DECLARE_printGPRSeqPairsClassOperand(32);
-DECLARE_printGPRSeqPairsClassOperand(64);
-
-#define DECLARE_printImm8OptLsl(T) \
-	void CONCAT(printImm8OptLsl, T)(MCInst * MI, unsigned OpNum, \
-					SStream *O);
-DECLARE_printImm8OptLsl(int16_t);
-DECLARE_printImm8OptLsl(int8_t);
-DECLARE_printImm8OptLsl(int64_t);
-DECLARE_printImm8OptLsl(int32_t);
-DECLARE_printImm8OptLsl(uint16_t);
-DECLARE_printImm8OptLsl(uint8_t);
-DECLARE_printImm8OptLsl(uint64_t);
-DECLARE_printImm8OptLsl(uint32_t);
-
-#define DECLARE_printSVELogicalImm(T) \
-	void CONCAT(printSVELogicalImm, T)(MCInst * MI, unsigned OpNum, \
-					   SStream *O);
-DECLARE_printSVELogicalImm(int16_t);
-DECLARE_printSVELogicalImm(int32_t);
-DECLARE_printSVELogicalImm(int64_t);
-
-void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O);
-void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printMatrixTileVector(IsVertical) \
-	void CONCAT(printMatrixTileVector, \
-		    IsVertical)(MCInst * MI, unsigned OpNum, SStream *O);
-DECLARE_printMatrixTileVector(0);
-DECLARE_printMatrixTileVector(1);
-
-void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printMatrix(EltSize) \
-	void CONCAT(printMatrix, EltSize)(MCInst * MI, unsigned OpNum, \
-					  SStream *O);
-DECLARE_printMatrix(64);
-DECLARE_printMatrix(32);
-DECLARE_printMatrix(16);
-DECLARE_printMatrix(0);
-
-void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printSVERegOp(char) \
-	void CONCAT(printSVERegOp, char)(MCInst * MI, unsigned OpNum, \
-					 SStream *O);
-DECLARE_printSVERegOp(b);
-DECLARE_printSVERegOp(d);
-DECLARE_printSVERegOp(h);
-DECLARE_printSVERegOp(s);
-DECLARE_printSVERegOp(0);
-DECLARE_printSVERegOp(q);
-
-void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O);
-void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O);
-void printSyspXzrPair(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printZPRasFPR(Width) \
-	void CONCAT(printZPRasFPR, Width)(MCInst * MI, unsigned OpNum, \
-					  SStream *O);
-DECLARE_printZPRasFPR(8);
-DECLARE_printZPRasFPR(64);
-DECLARE_printZPRasFPR(16);
-DECLARE_printZPRasFPR(32);
-DECLARE_printZPRasFPR(128);
-
-#define DECLARE_printExactFPImm(ImmIs0, ImmIs1) \
-	void CONCAT(printExactFPImm, CONCAT(ImmIs0, ImmIs1))( \
-		MCInst * MI, unsigned OpNum, SStream *O);
-DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_one);
-DECLARE_printExactFPImm(AArch64ExactFPImm_zero, AArch64ExactFPImm_one);
-DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_two);
-
-#define DECLARE_printMatrixIndex(Scale) \
-	void CONCAT(printMatrixIndex, Scale)(MCInst * MI, unsigned OpNum, \
-					     SStream *O);
-DECLARE_printMatrixIndex(8);
-DECLARE_printMatrixIndex(0);
-DECLARE_printMatrixIndex(1);
-
-// end namespace llvm
-
-#endif // LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H

thirdparty/capstone/arch/AArch64/AArch64Linkage.h

@@ -1,23 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Rot127 <unisono@quyllur.org> 2022-2023 */
-
-#ifndef CS_AARCH64_LINKAGE_H
-#define CS_AARCH64_LINKAGE_H
-
-// Function definitions to call static LLVM functions.
-
-#include "../../MCDisassembler.h"
-#include "../../MCInst.h"
-#include "../../MCRegisterInfo.h"
-#include "../../SStream.h"
-#include "capstone/capstone.h"
-
-DecodeStatus AArch64_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
-					 size_t ByteLen, MCInst *MI,
-					 uint16_t *Size, uint64_t Address,
-					 void *Info);
-const char *AArch64_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
-void AArch64_LLVM_printInstruction(MCInst *MI, SStream *O,
-				   void * /* MCRegisterInfo* */ info);
-
-#endif // CS_AARCH64_LINKAGE_H

thirdparty/capstone/arch/AArch64/AArch64Mapping.h

@@ -1,82 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#ifndef CS_AARCH64_MAP_H
-#define CS_AARCH64_MAP_H
-
-#include "capstone/capstone.h"
-#include "../../MCInst.h"
-#include "../../SStream.h"
-
-typedef enum {
-#include "AArch64GenCSOpGroup.inc"
-} aarch64_op_group;
-
-// return name of register in friendly string
-const char *AArch64_reg_name(csh handle, unsigned int reg);
-
-// given internal insn id, return public instruction info
-void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
-
-const char *AArch64_insn_name(csh handle, unsigned int id);
-
-const char *AArch64_group_name(csh handle, unsigned int id);
-
-void AArch64_reg_access(const cs_insn *insn, cs_regs regs_read,
-			uint8_t *regs_read_count, cs_regs regs_write,
-			uint8_t *regs_write_count);
-
-void AArch64_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group,
-			   va_list args);
-
-static inline void add_cs_detail(MCInst *MI,
-				 int /* aarch64_op_group */ op_group, ...)
-{
-	if (!MI->flat_insn->detail)
-		return;
-	va_list args;
-	va_start(args, op_group);
-	AArch64_add_cs_detail(MI, op_group, args);
-	va_end(args);
-}
-
-void AArch64_init_mri(MCRegisterInfo *MRI);
-
-void AArch64_init_cs_detail(MCInst *MI);
-
-void AArch64_set_instr_map_data(MCInst *MI);
-
-bool AArch64_getInstruction(csh handle, const uint8_t *code, size_t code_len,
-			    MCInst *instr, uint16_t *size, uint64_t address,
-			    void *info);
-
-void AArch64_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
-
-void AArch64_set_detail_op_reg(MCInst *MI, unsigned OpNum, aarch64_reg Reg);
-void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum,
-			       aarch64_op_type ImmType, int64_t Imm);
-void AArch64_set_detail_op_imm_range(MCInst *MI, unsigned OpNum,
-				     uint32_t FirstImm, uint32_t offset);
-void AArch64_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val);
-void AArch64_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val);
-void AArch64_set_detail_shift_ext(MCInst *MI, unsigned OpNum, bool SignExtend,
-				  bool DoShift, unsigned ExtWidth,
-				  char SrcRegKind);
-void AArch64_set_detail_op_float(MCInst *MI, unsigned OpNum, float Val);
-void AArch64_set_detail_op_sys(MCInst *MI, unsigned OpNum, aarch64_sysop sys_op,
-			       aarch64_op_type type);
-void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum,
-			       aarch64_sme_op_part part,
-			       AArch64Layout_VectorLayout vas, ...);
-void AArch64_set_detail_op_pred(MCInst *MI, unsigned OpNum);
-void AArch64_insert_detail_op_reg_at(MCInst *MI, unsigned index,
-				     aarch64_reg Reg, cs_ac_type access);
-void AArch64_insert_detail_op_float_at(MCInst *MI, unsigned index, double val,
-				       cs_ac_type access);
-void AArch64_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Imm);
-void AArch64_insert_detail_op_sys(MCInst *MI, unsigned index, aarch64_sysop sys_op,
-			       aarch64_op_type type);
-void AArch64_insert_detail_op_sme(MCInst *MI, unsigned index, aarch64_op_sme sme_op);
-void AArch64_add_vas(MCInst *MI, const SStream *OS);
-
-#endif

thirdparty/capstone/arch/AArch64/AArch64Module.c

@@ -1,46 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
-
-#ifdef CAPSTONE_HAS_AARCH64
-
-#include "../../utils.h"
-#include "../../MCRegisterInfo.h"
-#include "AArch64InstPrinter.h"
-#include "AArch64Mapping.h"
-#include "AArch64Module.h"
-
-cs_err AArch64_global_init(cs_struct *ud)
-{
-	MCRegisterInfo *mri;
-	mri = cs_mem_malloc(sizeof(*mri));
-
-	AArch64_init_mri(mri);
-	ud->printer = AArch64_printer;
-	ud->printer_info = mri;
-	ud->getinsn_info = mri;
-	ud->disasm = AArch64_getInstruction;
-	ud->reg_name = AArch64_reg_name;
-	ud->insn_id = AArch64_get_insn_id;
-	ud->insn_name = AArch64_insn_name;
-	ud->group_name = AArch64_group_name;
-	ud->post_printer = NULL;
-#ifndef CAPSTONE_DIET
-	ud->reg_access = AArch64_reg_access;
-#endif
-
-	return CS_ERR_OK;
-}
-
-cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value)
-{
-	if (type == CS_OPT_SYNTAX)
-		handle->syntax |= (int)value;
-
-	if (type == CS_OPT_MODE) {
-		handle->mode |= (cs_mode)value;
-	}
-
-	return CS_ERR_OK;
-}
-
-#endif

thirdparty/capstone/arch/AArch64/AArch64Module.h

@@ -1,12 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
-
-#ifndef CS_AARCH64_MODULE_H
-#define CS_AARCH64_MODULE_H
-
-#include "../../utils.h"
-
-cs_err AArch64_global_init(cs_struct *ud);
-cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value);
-
-#endif

thirdparty/capstone/arch/ARM/ARMAddressingModes.h

@@ -1,784 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
-/* Automatically translated source file from LLVM. */
-
-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
-
-/* Only small edits allowed. */
-/* For multiple similar edits, please create a Patch for the translator. */
-
-/* Capstone's C++ file translator: */
-/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
-
-//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the ARM addressing mode implementation stuff.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef CS_ARM_ADDRESSINGMODES_H
-#define CS_ARM_ADDRESSINGMODES_H
-
-#include <capstone/platform.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "../../MathExtras.h"
-#include <assert.h>
-
-#define CONCAT(a, b) CONCAT_(a, b)
-#define CONCAT_(a, b) a##_##b
-
-/// ARM_AM - ARM Addressing Mode Stuff
-typedef enum ShiftOpc {
-	ARM_AM_no_shift = 0,
-	ARM_AM_asr,
-	ARM_AM_lsl,
-	ARM_AM_lsr,
-	ARM_AM_ror,
-	ARM_AM_rrx,
-	ARM_AM_uxtw
-} ARM_AM_ShiftOpc;
-
-typedef enum AddrOpc { ARM_AM_sub = 0, ARM_AM_add } ARM_AM_AddrOpc;
-
-static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
-{
-	return Op == ARM_AM_sub ? "-" : "";
-}
-
-static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
-{
-	switch (Op) {
-	default:
-		assert(0 && "Unknown shift opc!");
-	case ARM_AM_asr:
-		return "asr";
-	case ARM_AM_lsl:
-		return "lsl";
-	case ARM_AM_lsr:
-		return "lsr";
-	case ARM_AM_ror:
-		return "ror";
-	case ARM_AM_rrx:
-		return "rrx";
-	case ARM_AM_uxtw:
-		return "uxtw";
-	}
-}
-
-static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op)
-{
-	switch (Op) {
-	default:
-		assert(0 && "Unknown shift opc!");
-	case ARM_AM_asr:
-		return 2;
-	case ARM_AM_lsl:
-		return 0;
-	case ARM_AM_lsr:
-		return 1;
-	case ARM_AM_ror:
-		return 3;
-	}
-}
-
-typedef enum AMSubMode {
-	ARM_AM_bad_am_submode = 0,
-	ARM_AM_ia,
-	ARM_AM_ib,
-	ARM_AM_da,
-	ARM_AM_db
-} ARM_AM_SubMode;
-
-static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_SubMode Mode)
-{
-	switch (Mode) {
-	default:
-		assert(0 && "Unknown addressing sub-mode!");
-	case ARM_AM_ia:
-		return "ia";
-	case ARM_AM_ib:
-		return "ib";
-	case ARM_AM_da:
-		return "da";
-	case ARM_AM_db:
-		return "db";
-	}
-}
-
-/// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
-///
-static inline unsigned ARM_AM_rotr32(unsigned Val, unsigned Amt)
-{
-	return (Val >> Amt) | (Val << ((32 - Amt) & 31));
-}
-
-/// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
-///
-static inline unsigned ARM_AM_rotl32(unsigned Val, unsigned Amt)
-{
-	return (Val << Amt) | (Val >> ((32 - Amt) & 31));
-}
-
-//===--------------------------------------------------------------------===//
-// Addressing Mode #1: shift_operand with registers
-//===--------------------------------------------------------------------===//
-//
-// This 'addressing mode' is used for arithmetic instructions.  It can
-// represent things like:
-//   reg
-//   reg [asr|lsl|lsr|ror|rrx] reg
-//   reg [asr|lsl|lsr|ror|rrx] imm
-//
-// This is stored three operands [rega, regb, opc].  The first is the base
-// reg, the second is the shift amount (or reg0 if not present or imm).  The
-// third operand encodes the shift opcode and the imm if a reg isn't present.
-//
-static inline unsigned ARM_AM_getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
-{
-	return ShOp | (Imm << 3);
-}
-
-static inline unsigned ARM_AM_getSORegOffset(unsigned Op)
-{
-	return Op >> 3;
-}
-
-static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op)
-{
-	return (ARM_AM_ShiftOpc)(Op & 7);
-}
-
-/// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
-/// the 8-bit imm value.
-static inline unsigned ARM_AM_getSOImmValImm(unsigned Imm)
-{
-	return Imm & 0xFF;
-}
-
-/// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
-/// the rotate amount.
-static inline unsigned ARM_AM_getSOImmValRot(unsigned Imm)
-{
-	return (Imm >> 8) * 2;
-}
-
-/// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
-/// computing the rotate amount to use.  If this immediate value cannot be
-/// handled with a single shifter-op, determine a good rotate amount that will
-/// take a maximal chunk of bits out of the immediate.
-static inline unsigned ARM_AM_getSOImmValRotate(unsigned Imm)
-{
-	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
-	// of zero.
-	if ((Imm & ~255U) == 0)
-		return 0;
-
-	// Use CTZ to compute the rotate amount.
-	unsigned TZ = CountTrailingZeros_32(Imm);
-
-	// Rotate amount must be even.  Something like 0x200 must be rotated 8 bits,
-	// not 9.
-	unsigned RotAmt = TZ & ~1;
-
-	// If we can handle this spread, return it.
-	if ((ARM_AM_rotr32(Imm, RotAmt) & ~255U) == 0)
-		return (32 - RotAmt) & 31; // HW rotates right, not left.
-
-	// For values like 0xF000000F, we should ignore the low 6 bits, then
-	// retry the hunt.
-	if (Imm & 63U) {
-		unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
-		unsigned RotAmt2 = TZ2 & ~1;
-		if ((ARM_AM_rotr32(Imm, RotAmt2) & ~255U) == 0)
-			return (32 - RotAmt2) &
-			       31; // HW rotates right, not left.
-	}
-
-	// Otherwise, we have no way to cover this span of bits with a single
-	// shifter_op immediate.  Return a chunk of bits that will be useful to
-	// handle.
-	return (32 - RotAmt) & 31; // HW rotates right, not left.
-}
-
-/// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
-/// into an shifter_operand immediate operand, return the 12-bit encoding for
-/// it.  If not, return -1.
-static inline int ARM_AM_getSOImmVal(unsigned Arg)
-{
-	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
-	// of zero.
-	if ((Arg & ~255U) == 0)
-		return Arg;
-
-	unsigned RotAmt = ARM_AM_getSOImmValRotate(Arg);
-
-	// If this cannot be handled with a single shifter_op, bail out.
-	if (ARM_AM_rotr32(~255U, RotAmt) & Arg)
-		return -1;
-
-	// Encode this correctly.
-	return ARM_AM_rotl32(Arg, RotAmt) | ((RotAmt >> 1) << 8);
-}
-
-/// isSOImmTwoPartVal - Return true if the specified value can be obtained by
-/// or'ing together two SOImmVal's.
-static inline bool ARM_AM_isSOImmTwoPartVal(unsigned V)
-{
-	// If this can be handled with a single shifter_op, bail out.
-	V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
-	if (V == 0)
-		return false;
-
-	// If this can be handled with two shifter_op's, accept.
-	V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
-	return V == 0;
-}
-
-/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
-/// return the first chunk of it.
-static inline unsigned ARM_AM_getSOImmTwoPartFirst(unsigned V)
-{
-	return ARM_AM_rotr32(255U, ARM_AM_getSOImmValRotate(V)) & V;
-}
-
-/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
-/// return the second chunk of it.
-static inline unsigned ARM_AM_getSOImmTwoPartSecond(unsigned V)
-{
-	// Mask out the first hunk.
-	V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
-
-	// Take what's left.
-
-	return V;
-}
-
-/// isSOImmTwoPartValNeg - Return true if the specified value can be obtained
-/// by two SOImmVal, that -V = First + Second.
-/// "R+V" can be optimized to (sub (sub R, First), Second).
-/// "R=V" can be optimized to (sub (mvn R, ~(-First)), Second).
-static inline bool ARM_AM_isSOImmTwoPartValNeg(unsigned V)
-{
-	unsigned First;
-	if (!ARM_AM_isSOImmTwoPartVal(-V))
-		return false;
-	// Return false if ~(-First) is not a SoImmval.
-	First = ARM_AM_getSOImmTwoPartFirst(-V);
-	First = ~(-First);
-	return !(ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(First)) & First);
-}
-
-/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
-/// by a left shift. Returns the shift amount to use.
-static inline unsigned ARM_AM_getThumbImmValShift(unsigned Imm)
-{
-	// 8-bit (or less) immediates are trivially immediate operand with a shift
-	// of zero.
-	if ((Imm & ~255U) == 0)
-		return 0;
-
-	// Use CTZ to compute the shift amount.
-	return CountTrailingZeros_32(Imm);
-}
-
-/// isThumbImmShiftedVal - Return true if the specified value can be obtained
-/// by left shifting a 8-bit immediate.
-static inline bool ARM_AM_isThumbImmShiftedVal(unsigned V)
-{
-	// If this can be handled with
-	V = (~255U << ARM_AM_getThumbImmValShift(V)) & V;
-	return V == 0;
-}
-
-/// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
-/// by a left shift. Returns the shift amount to use.
-static inline unsigned ARM_AM_getThumbImm16ValShift(unsigned Imm)
-{
-	// 16-bit (or less) immediates are trivially immediate operand with a shift
-	// of zero.
-	if ((Imm & ~65535U) == 0)
-		return 0;
-
-	// Use CTZ to compute the shift amount.
-	return CountTrailingZeros_32(Imm);
-}
-
-/// isThumbImm16ShiftedVal - Return true if the specified value can be
-/// obtained by left shifting a 16-bit immediate.
-static inline bool ARM_AM_isThumbImm16ShiftedVal(unsigned V)
-{
-	// If this can be handled with
-	V = (~65535U << ARM_AM_getThumbImm16ValShift(V)) & V;
-	return V == 0;
-}
-
-/// getThumbImmNonShiftedVal - If V is a value that satisfies
-/// isThumbImmShiftedVal, return the non-shiftd value.
-static inline unsigned ARM_AM_getThumbImmNonShiftedVal(unsigned V)
-{
-	return V >> ARM_AM_getThumbImmValShift(V);
-}
-
-/// getT2SOImmValSplat - Return the 12-bit encoded representation
-/// if the specified value can be obtained by splatting the low 8 bits
-/// into every other byte or every byte of a 32-bit value. i.e.,
-///     00000000 00000000 00000000 abcdefgh    control = 0
-///     00000000 abcdefgh 00000000 abcdefgh    control = 1
-///     abcdefgh 00000000 abcdefgh 00000000    control = 2
-///     abcdefgh abcdefgh abcdefgh abcdefgh    control = 3
-/// Return -1 if none of the above apply.
-/// See ARM Reference Manual A6.3.2.
-static inline int ARM_AM_getT2SOImmValSplatVal(unsigned V)
-{
-	unsigned u, Vs, Imm;
-	// control = 0
-	if ((V & 0xffffff00) == 0)
-		return V;
-
-	// If the value is zeroes in the first byte, just shift those off
-	Vs = ((V & 0xff) == 0) ? V >> 8 : V;
-	// Any passing value only has 8 bits of payload, splatted across the word
-	Imm = Vs & 0xff;
-	// Likewise, any passing values have the payload splatted into the 3rd byte
-	u = Imm | (Imm << 16);
-
-	// control = 1 or 2
-	if (Vs == u)
-		return (((Vs == V) ? 1 : 2) << 8) | Imm;
-
-	// control = 3
-	if (Vs == (u | (u << 8)))
-		return (3 << 8) | Imm;
-
-	return -1;
-}
-
-/// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
-/// specified value is a rotated 8-bit value. Return -1 if no rotation
-/// encoding is possible.
-/// See ARM Reference Manual A6.3.2.
-static inline int ARM_AM_getT2SOImmValRotateVal(unsigned V)
-{
-	unsigned RotAmt = CountLeadingZeros_32(V);
-	if (RotAmt >= 24)
-		return -1;
-
-	// If 'Arg' can be handled with a single shifter_op return the value.
-	if ((ARM_AM_rotr32(0xff000000U, RotAmt) & V) == V)
-		return (ARM_AM_rotr32(V, 24 - RotAmt) & 0x7f) |
-		       ((RotAmt + 8) << 7);
-
-	return -1;
-}
-
-/// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
-/// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
-/// encoding for it.  If not, return -1.
-/// See ARM Reference Manual A6.3.2.
-static inline int ARM_AM_getT2SOImmVal(unsigned Arg)
-{
-	// If 'Arg' is an 8-bit splat, then get the encoded value.
-	int Splat = ARM_AM_getT2SOImmValSplatVal(Arg);
-	if (Splat != -1)
-		return Splat;
-
-	// If 'Arg' can be handled with a single shifter_op return the value.
-	int Rot = ARM_AM_getT2SOImmValRotateVal(Arg);
-	if (Rot != -1)
-		return Rot;
-
-	return -1;
-}
-
-static inline unsigned ARM_AM_getT2SOImmValRotate(unsigned V)
-{
-	if ((V & ~255U) == 0)
-		return 0;
-	// Use CTZ to compute the rotate amount.
-	unsigned RotAmt = CountTrailingZeros_32(V);
-	return (32 - RotAmt) & 31;
-}
-
-static inline bool ARM_AM_isT2SOImmTwoPartVal(unsigned Imm)
-{
-	unsigned V = Imm;
-	// Passing values can be any combination of splat values and shifter
-	// values. If this can be handled with a single shifter or splat, bail
-	// out. Those should be handled directly, not with a two-part val.
-	if (ARM_AM_getT2SOImmValSplatVal(V) != -1)
-		return false;
-	V = ARM_AM_rotr32(~255U, ARM_AM_getT2SOImmValRotate(V)) & V;
-	if (V == 0)
-		return false;
-
-	// If this can be handled as an immediate, accept.
-	if (ARM_AM_getT2SOImmVal(V) != -1)
-		return true;
-
-	// Likewise, try masking out a splat value first.
-	V = Imm;
-	if (ARM_AM_getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
-		V &= ~0xff00ff00U;
-	else if (ARM_AM_getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
-		V &= ~0x00ff00ffU;
-	// If what's left can be handled as an immediate, accept.
-	if (ARM_AM_getT2SOImmVal(V) != -1)
-		return true;
-
-	// Otherwise, do not accept.
-	return false;
-}
-
-static inline unsigned ARM_AM_getT2SOImmTwoPartFirst(unsigned Imm)
-{
-	// Try a shifter operand as one part
-	unsigned V = ARM_AM_rotr32(~255, ARM_AM_getT2SOImmValRotate(Imm)) & Imm;
-	// If the rest is encodable as an immediate, then return it.
-	if (ARM_AM_getT2SOImmVal(V) != -1)
-		return V;
-
-	// Try masking out a splat value first.
-	if (ARM_AM_getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
-		return Imm & 0xff00ff00U;
-
-	// The other splat is all that's left as an option.
-
-	return Imm & 0x00ff00ffU;
-}
-
-static inline unsigned ARM_AM_getT2SOImmTwoPartSecond(unsigned Imm)
-{
-	// Mask out the first hunk
-	Imm ^= ARM_AM_getT2SOImmTwoPartFirst(Imm);
-	// Return what's left
-
-	return Imm;
-}
-
-//===--------------------------------------------------------------------===//
-// Addressing Mode #2
-//===--------------------------------------------------------------------===//
-//
-// This is used for most simple load/store instructions.
-//
-// addrmode2 := reg +/- reg shop imm
-// addrmode2 := reg +/- imm12
-//
-// The first operand is always a Reg.  The second operand is a reg if in
-// reg/reg form, otherwise it's reg#0.  The third field encodes the operation
-// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
-// fourth operand 16-17 encodes the index mode.
-//
-// If this addressing mode is a frame index (before prolog/epilog insertion
-// and code rewriting), this operand will have the form:  FI#, reg0, <offs>
-// with no shift amount for the frame offset.
-//
-static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12,
-					ARM_AM_ShiftOpc SO, unsigned IdxMode)
-{
-	bool isSub = Opc == ARM_AM_sub;
-	return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16);
-}
-
-static inline unsigned ARM_AM_getAM2Offset(unsigned AM2Opc)
-{
-	return AM2Opc & ((1 << 12) - 1);
-}
-
-static inline ARM_AM_AddrOpc ARM_AM_getAM2Op(unsigned AM2Opc)
-{
-	return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add;
-}
-
-static inline ARM_AM_ShiftOpc ARM_AM_getAM2ShiftOpc(unsigned AM2Opc)
-{
-	return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7);
-}
-
-static inline unsigned ARM_AM_getAM2IdxMode(unsigned AM2Opc)
-{
-	return (AM2Opc >> 16);
-}
-
-//===--------------------------------------------------------------------===//
-// Addressing Mode #3
-//===--------------------------------------------------------------------===//
-//
-// This is used for sign-extending loads, and load/store-pair instructions.
-//
-// addrmode3 := reg +/- reg
-// addrmode3 := reg +/- imm8
-//
-// The first operand is always a Reg.  The second operand is a reg if in
-// reg/reg form, otherwise it's reg#0.  The third field encodes the operation
-// in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
-// index mode.
-/// getAM3Opc - This function encodes the addrmode3 opc field.
-static inline unsigned ARM_AM_getAM3Opc(ARM_AM_AddrOpc Opc,
-					unsigned char Offset, unsigned IdxMode)
-{
-	bool isSub = Opc == ARM_AM_sub;
-	return ((int)isSub << 8) | Offset | (IdxMode << 9);
-}
-
-static inline unsigned char ARM_AM_getAM3Offset(unsigned AM3Opc)
-{
-	return AM3Opc & 0xFF;
-}
-
-static inline ARM_AM_AddrOpc ARM_AM_getAM3Op(unsigned AM3Opc)
-{
-	return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
-}
-
-static inline unsigned ARM_AM_getAM3IdxMode(unsigned AM3Opc)
-{
-	return (AM3Opc >> 9);
-}
-
-//===--------------------------------------------------------------------===//
-// Addressing Mode #4
-//===--------------------------------------------------------------------===//
-//
-// This is used for load / store multiple instructions.
-//
-// addrmode4 := reg, <mode>
-//
-// The four modes are:
-//    IA - Increment after
-//    IB - Increment before
-//    DA - Decrement after
-//    DB - Decrement before
-// For VFP instructions, only the IA and DB modes are valid.
-static inline ARM_AM_SubMode ARM_AM_getAM4SubMode(unsigned Mode)
-{
-	return (ARM_AM_SubMode)(Mode & 0x7);
-}
-
-static inline unsigned ARM_AM_getAM4ModeImm(ARM_AM_SubMode SubMode)
-{
-	return (int)SubMode;
-}
-
-//===--------------------------------------------------------------------===//
-// Addressing Mode #5
-//===--------------------------------------------------------------------===//
-//
-// This is used for coprocessor instructions, such as FP load/stores.
-//
-// addrmode5 := reg +/- imm8*4
-//
-// The first operand is always a Reg.  The second operand encodes the
-// operation (add or subtract) in bit 8 and the immediate in bits 0-7.
-/// getAM5Opc - This function encodes the addrmode5 opc field.
-static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc,
-					unsigned char Offset)
-{
-	bool isSub = Opc == ARM_AM_sub;
-	return ((int)isSub << 8) | Offset;
-}
-
-static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc)
-{
-	return AM5Opc & 0xFF;
-}
-
-static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc)
-{
-	return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
-}
-
-//===--------------------------------------------------------------------===//
-// Addressing Mode #5 FP16
-//===--------------------------------------------------------------------===//
-//
-// This is used for coprocessor instructions, such as 16-bit FP load/stores.
-//
-// addrmode5fp16 := reg +/- imm8*2
-//
-// The first operand is always a Reg.  The second operand encodes the
-// operation (add or subtract) in bit 8 and the immediate in bits 0-7.
-/// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
-static inline unsigned ARM_AM_getAM5FP16Opc(ARM_AM_AddrOpc Opc,
-					    unsigned char Offset)
-{
-	bool isSub = Opc == ARM_AM_sub;
-	return ((int)isSub << 8) | Offset;
-}
-
-static inline unsigned char ARM_AM_getAM5FP16Offset(unsigned AM5Opc)
-{
-	return AM5Opc & 0xFF;
-}
-
-static inline ARM_AM_AddrOpc ARM_AM_getAM5FP16Op(unsigned AM5Opc)
-{
-	return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
-}
-
-//===--------------------------------------------------------------------===//
-// Addressing Mode #6
-//===--------------------------------------------------------------------===//
-//
-// This is used for NEON load / store instructions.
-//
-// addrmode6 := reg with optional alignment
-//
-// This is stored in two operands [regaddr, align].  The first is the
-// address register.  The second operand is the value of the alignment
-// specifier in bytes or zero if no explicit alignment.
-// Valid alignments depend on the specific instruction.
-//===--------------------------------------------------------------------===//
-// NEON/MVE Modified Immediates
-//===--------------------------------------------------------------------===//
-//
-// Several NEON and MVE instructions (e.g., VMOV) take a "modified immediate"
-// vector operand, where a small immediate encoded in the instruction
-// specifies a full NEON vector value.  These modified immediates are
-// represented here as encoded integers.  The low 8 bits hold the immediate
-// value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
-// the "Cmode" field of the instruction.  The interfaces below treat the
-// Op and Cmode values as a single 5-bit value.
-static inline unsigned ARM_AM_createVMOVModImm(unsigned OpCmode, unsigned Val)
-{
-	return (OpCmode << 8) | Val;
-}
-
-static inline unsigned ARM_AM_getVMOVModImmOpCmode(unsigned ModImm)
-{
-	return (ModImm >> 8) & 0x1f;
-}
-
-static inline unsigned ARM_AM_getVMOVModImmVal(unsigned ModImm)
-{
-	return ModImm & 0xff;
-}
-
-/// decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the
-/// element value and the element size in bits.  (If the element size is
-/// smaller than the vector, it is splatted into all the elements.)
-static inline uint64_t ARM_AM_decodeVMOVModImm(unsigned ModImm,
-					       unsigned *EltBits)
-{
-	unsigned OpCmode = ARM_AM_getVMOVModImmOpCmode(ModImm);
-	unsigned Imm8 = ARM_AM_getVMOVModImmVal(ModImm);
-	uint64_t Val = 0;
-
-	if (OpCmode == 0xe) {
-		// 8-bit vector elements
-		Val = Imm8;
-		*EltBits = 8;
-	} else if ((OpCmode & 0xc) == 0x8) {
-		// 16-bit vector elements
-		unsigned ByteNum = (OpCmode & 0x6) >> 1;
-		Val = Imm8 << (8 * ByteNum);
-		*EltBits = 16;
-	} else if ((OpCmode & 0x8) == 0) {
-		// 32-bit vector elements, zero with one byte set
-		unsigned ByteNum = (OpCmode & 0x6) >> 1;
-		Val = Imm8 << (8 * ByteNum);
-		*EltBits = 32;
-	} else if ((OpCmode & 0xe) == 0xc) {
-		// 32-bit vector elements, one byte with low bits set
-		unsigned ByteNum = 1 + (OpCmode & 0x1);
-		Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
-		*EltBits = 32;
-	} else if (OpCmode == 0x1e) {
-		// 64-bit vector elements
-		for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
-			if ((ModImm >> ByteNum) & 1)
-				Val |= (uint64_t)0xff << (8 * ByteNum);
-		}
-		*EltBits = 64;
-	} else {
-		assert(0 && "Unsupported VMOV immediate");
-	}
-	return Val;
-}
-
-// Generic validation for single-byte immediate (0X00, 00X0, etc).
-static inline bool ARM_AM_isNEONBytesplat(unsigned Value, unsigned Size)
-{
-	unsigned count = 0;
-	for (unsigned i = 0; i < Size; ++i) {
-		if (Value & 0xff)
-			count++;
-		Value >>= 8;
-	}
-	return count == 1;
-}
-
-/// Checks if Value is a correct immediate for instructions like VBIC/VORR.
-static inline bool ARM_AM_isNEONi16splat(unsigned Value)
-{
-	if (Value > 0xffff)
-		return false;
-	// i16 value with set bits only in one byte X0 or 0X.
-	return Value == 0 || ARM_AM_isNEONBytesplat(Value, 2);
-}
-
-// Encode NEON 16 bits Splat immediate for instructions like VBIC/VORR
-static inline unsigned ARM_AM_encodeNEONi16splat(unsigned Value)
-{
-	if (Value >= 0x100)
-		Value = (Value >> 8) | 0xa00;
-	else
-		Value |= 0x800;
-	return Value;
-}
-
-/// Checks if Value is a correct immediate for instructions like VBIC/VORR.
-static inline bool ARM_AM_isNEONi32splat(unsigned Value)
-{
-	// i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
-	return Value == 0 || ARM_AM_isNEONBytesplat(Value, 4);
-}
-
-/// Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR.
-static inline unsigned ARM_AM_encodeNEONi32splat(unsigned Value)
-{
-	if (Value >= 0x100 && Value <= 0xff00)
-		Value = (Value >> 8) | 0x200;
-	else if (Value > 0xffff && Value <= 0xff0000)
-		Value = (Value >> 16) | 0x400;
-	else if (Value > 0xffffff)
-		Value = (Value >> 24) | 0x600;
-	return Value;
-}
-
-//===--------------------------------------------------------------------===//
-// Floating-point Immediates
-//
-static inline float ARM_AM_getFPImmFloat(unsigned Imm)
-{
-	// We expect an 8-bit binary encoding of a floating-point number here.
-
-	uint8_t Sign = (Imm >> 7) & 0x1;
-	uint8_t Exp = (Imm >> 4) & 0x7;
-	uint8_t Mantissa = Imm & 0xf;
-
-	//   8-bit FP    IEEE Float Encoding
-	//   abcd efgh   aBbbbbbc defgh000 00000000 00000000
-	//
-	// where B = NOT(b);
-	uint32_t I = 0;
-	I |= Sign << 31;
-	I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
-	I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
-	I |= (Exp & 0x3) << 23;
-	I |= Mantissa << 19;
-	return BitsToFloat(I);
-}
-
-#endif // CS_ARM_ADDRESSINGMODES_H

thirdparty/capstone/arch/ARM/ARMBaseInfo.c

@@ -1,101 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
-/* Automatically translated source file from LLVM. */
-
-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
-
-/* Only small edits allowed. */
-/* For multiple similar edits, please create a Patch for the translator. */
-
-/* Capstone's C++ file translator: */
-/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
-
-//===-- ARMBaseInfo.cpp - ARM Base encoding information------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides basic encoding and assembly information for ARM.
-//
-//===----------------------------------------------------------------------===//
-#include <capstone/platform.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "ARMBaseInfo.h"
-#include "ARMMapping.h"
-
-#define CONCAT(a, b) CONCAT_(a, b)
-#define CONCAT_(a, b) a##_##b
-
-const char *get_pred_mask(ARM_PredBlockMask pred_mask)
-{
-	switch (pred_mask) {
-	default:
-		assert(0 && "pred_mask not handled.");
-	case ARM_T:
-		return "T";
-	case ARM_TT:
-		return "TT";
-	case ARM_TE:
-		return "TE";
-	case ARM_TTT:
-		return "TTT";
-	case ARM_TTE:
-		return "TTE";
-	case ARM_TEE:
-		return "TEE";
-	case ARM_TET:
-		return "TET";
-	case ARM_TTTT:
-		return "TTTT";
-	case ARM_TTTE:
-		return "TTTE";
-	case ARM_TTEE:
-		return "TTEE";
-	case ARM_TTET:
-		return "TTET";
-	case ARM_TEEE:
-		return "TEEE";
-	case ARM_TEET:
-		return "TEET";
-	case ARM_TETT:
-		return "TETT";
-	case ARM_TETE:
-		return "TETE";
-	}
-}
-
-#define GET_MCLASSSYSREG_IMPL
-#include "ARMGenSystemRegister.inc"
-
-// lookup system register using 12-bit SYSm value.
-// Note: the search is uniqued using M1 mask
-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
-{
-	return ARMSysReg_lookupMClassSysRegByM1Encoding12(SYSm);
-}
-
-// returns APSR with _<bits> qualifier.
-// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
-{
-	return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 9) |
-							   (SYSm & 0xFF));
-}
-
-// lookup system registers using 8-bit SYSm value
-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
-{
-	return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 8) |
-							   (SYSm & 0xFF));
-}

thirdparty/capstone/arch/ARM/ARMBaseInfo.h

@@ -1,573 +0,0 @@
-//===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains small standalone helper functions and enum definitions for
-// the ARM target useful for the compiler back-end and the MC libraries.
-// As such, it deliberately does not include references to LLVM core
-// code gen types, passes, etc..
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef CS_ARM_BASEINFO_H
-#define CS_ARM_BASEINFO_H
-
-#include <assert.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <string.h>
-
-#include "../../MCInstPrinter.h"
-#include "capstone/arm.h"
-
-#define GET_INSTRINFO_ENUM
-#include "ARMGenInstrInfo.inc"
-
-// System Registers
-typedef struct MClassSysReg {
-	const char *Name;
-	arm_sysop_reg sysreg;
-	uint16_t M1Encoding12;
-	uint16_t M2M3Encoding8;
-	uint16_t Encoding;
-	int FeaturesRequired[2];
-} ARMSysReg_MClassSysReg;
-
-// return true if FeaturesRequired are all present in ActiveFeatures
-static inline bool hasRequiredFeatures(const ARMSysReg_MClassSysReg *TheReg,
-				       int ActiveFeatures)
-{
-	return (TheReg->FeaturesRequired[0] == ActiveFeatures ||
-		TheReg->FeaturesRequired[1] == ActiveFeatures);
-}
-
-// returns true if TestFeatures are all present in FeaturesRequired
-static inline bool
-MClassSysReg_isInRequiredFeatures(const ARMSysReg_MClassSysReg *TheReg,
-				  int TestFeatures)
-{
-	return (TheReg->FeaturesRequired[0] == TestFeatures ||
-		TheReg->FeaturesRequired[1] == TestFeatures);
-}
-
-#define GET_SUBTARGETINFO_ENUM
-#include "ARMGenSubtargetInfo.inc"
-
-// lookup system register using 12-bit SYSm value.
-// Note: the search is uniqued using M1 mask
-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm);
-// returns APSR with _<bits> qualifier.
-// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm);
-// lookup system registers using 8-bit SYSm value
-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm);
-// end namespace ARMSysReg
-
-// Banked Registers
-typedef struct BankedReg {
-	const char *Name;
-	arm_sysop_reg sysreg;
-	uint16_t Encoding;
-} ARMBankedReg_BankedReg;
-
-#define GET_BANKEDREG_DECL
-#define GET_MCLASSSYSREG_DECL
-#include "ARMGenSystemRegister.inc"
-
-typedef enum IMod { ARM_PROC_IE = 2, ARM_PROC_ID = 3 } ARM_PROC_IMod;
-
-typedef enum IFlags {
-	ARM_PROC_F = 1,
-	ARM_PROC_I = 2,
-	ARM_PROC_A = 4
-} ARM_PROC_IFlags;
-
-inline static const char *ARM_PROC_IFlagsToString(unsigned val)
-{
-	switch (val) {
-	default:
-		// llvm_unreachable("Unknown iflags operand");
-	case ARM_PROC_F:
-		return "f";
-	case ARM_PROC_I:
-		return "i";
-	case ARM_PROC_A:
-		return "a";
-	}
-}
-
-inline static const char *ARM_PROC_IModToString(unsigned val)
-{
-	switch (val) {
-	default:
-		// llvm_unreachable("Unknown imod operand");
-		assert(0);
-	case ARM_PROC_IE:
-		return "ie";
-	case ARM_PROC_ID:
-		return "id";
-	}
-}
-
-inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
-{
-	switch (val) {
-	default:
-		// llvm_unreachable("Unknown memory operation");
-		assert(0);
-	case ARM_MB_SY:
-		return "sy";
-	case ARM_MB_ST:
-		return "st";
-	case ARM_MB_LD:
-		return HasV8 ? "ld" : "#0xd";
-	case ARM_MB_RESERVED_12:
-		return "#0xc";
-	case ARM_MB_ISH:
-		return "ish";
-	case ARM_MB_ISHST:
-		return "ishst";
-	case ARM_MB_ISHLD:
-		return HasV8 ? "ishld" : "#0x9";
-	case ARM_MB_RESERVED_8:
-		return "#0x8";
-	case ARM_MB_NSH:
-		return "nsh";
-	case ARM_MB_NSHST:
-		return "nshst";
-	case ARM_MB_NSHLD:
-		return HasV8 ? "nshld" : "#0x5";
-	case ARM_MB_RESERVED_4:
-		return "#0x4";
-	case ARM_MB_OSH:
-		return "osh";
-	case ARM_MB_OSHST:
-		return "oshst";
-	case ARM_MB_OSHLD:
-		return HasV8 ? "oshld" : "#0x1";
-	case ARM_MB_RESERVED_0:
-		return "#0x0";
-	}
-}
-
-typedef enum TraceSyncBOpt { ARM_TSB_CSYNC = 0 } ARM_TSB_TraceSyncBOpt;
-
-inline static const char *ARM_TSB_TraceSyncBOptToString(unsigned val)
-{
-	switch (val) {
-	default:
-		// llvm_unreachable("Unknown trace synchronization barrier operation");
-		assert(0);
-	case ARM_TSB_CSYNC:
-		return "csync";
-	}
-}
-
-typedef enum InstSyncBOpt {
-	ARM_ISB_RESERVED_0 = 0,
-	ARM_ISB_RESERVED_1 = 1,
-	ARM_ISB_RESERVED_2 = 2,
-	ARM_ISB_RESERVED_3 = 3,
-	ARM_ISB_RESERVED_4 = 4,
-	ARM_ISB_RESERVED_5 = 5,
-	ARM_ISB_RESERVED_6 = 6,
-	ARM_ISB_RESERVED_7 = 7,
-	ARM_ISB_RESERVED_8 = 8,
-	ARM_ISB_RESERVED_9 = 9,
-	ARM_ISB_RESERVED_10 = 10,
-	ARM_ISB_RESERVED_11 = 11,
-	ARM_ISB_RESERVED_12 = 12,
-	ARM_ISB_RESERVED_13 = 13,
-	ARM_ISB_RESERVED_14 = 14,
-	ARM_ISB_SY = 15
-} ARM_ISB_InstSyncBOpt;
-
-inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val)
-{
-	switch (val) {
-	default:
-		// llvm_unreachable("Unknown memory operation");
-		assert(0);
-	case ARM_ISB_RESERVED_0:
-		return "#0x0";
-	case ARM_ISB_RESERVED_1:
-		return "#0x1";
-	case ARM_ISB_RESERVED_2:
-		return "#0x2";
-	case ARM_ISB_RESERVED_3:
-		return "#0x3";
-	case ARM_ISB_RESERVED_4:
-		return "#0x4";
-	case ARM_ISB_RESERVED_5:
-		return "#0x5";
-	case ARM_ISB_RESERVED_6:
-		return "#0x6";
-	case ARM_ISB_RESERVED_7:
-		return "#0x7";
-	case ARM_ISB_RESERVED_8:
-		return "#0x8";
-	case ARM_ISB_RESERVED_9:
-		return "#0x9";
-	case ARM_ISB_RESERVED_10:
-		return "#0xa";
-	case ARM_ISB_RESERVED_11:
-		return "#0xb";
-	case ARM_ISB_RESERVED_12:
-		return "#0xc";
-	case ARM_ISB_RESERVED_13:
-		return "#0xd";
-	case ARM_ISB_RESERVED_14:
-		return "#0xe";
-	case ARM_ISB_SY:
-		return "sy";
-	}
-}
-
-#define GET_REGINFO_ENUM
-#include "ARMGenRegisterInfo.inc"
-
-/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
-///
-static inline bool isARMLowRegister(unsigned Reg)
-{
-	switch (Reg) {
-	case ARM_R0:
-	case ARM_R1:
-	case ARM_R2:
-	case ARM_R3:
-	case ARM_R4:
-	case ARM_R5:
-	case ARM_R6:
-	case ARM_R7:
-		return true;
-	default:
-		return false;
-	}
-}
-
-/// ARMII - This namespace holds all of the target specific flags that
-/// instruction info tracks.
-///
-/// ARM Index Modes
-typedef enum IndexMode {
-	ARMII_IndexModeNone = 0,
-	ARMII_IndexModePre = 1,
-	ARMII_IndexModePost = 2,
-	ARMII_IndexModeUpd = 3
-} ARMII_IndexMode;
-
-/// ARM Addressing Modes
-typedef enum AddrMode {
-	ARMII_AddrModeNone = 0,
-	ARMII_AddrMode1 = 1,
-	ARMII_AddrMode2 = 2,
-	ARMII_AddrMode3 = 3,
-	ARMII_AddrMode4 = 4,
-	ARMII_AddrMode5 = 5,
-	ARMII_AddrMode6 = 6,
-	ARMII_AddrModeT1_1 = 7,
-	ARMII_AddrModeT1_2 = 8,
-	ARMII_AddrModeT1_4 = 9,
-	ARMII_AddrModeT1_s = 10,     // i8 * 4 for pc and sp relative data
-	ARMII_AddrModeT2_i12 = 11,
-	ARMII_AddrModeT2_i8 = 12,    // +/- i8
-	ARMII_AddrModeT2_i8pos = 13, // + i8
-	ARMII_AddrModeT2_i8neg = 14, // - i8
-	ARMII_AddrModeT2_so = 15,
-	ARMII_AddrModeT2_pc = 16,    // +/- i12 for pc relative data
-	ARMII_AddrModeT2_i8s4 = 17,  // i8 * 4
-	ARMII_AddrMode_i12 = 18,
-	ARMII_AddrMode5FP16 = 19,    // i8 * 2
-	ARMII_AddrModeT2_ldrex = 20, // i8 * 4, with unscaled offset in MCInst
-	ARMII_AddrModeT2_i7s4 = 21,  // i7 * 4
-	ARMII_AddrModeT2_i7s2 = 22,  // i7 * 2
-	ARMII_AddrModeT2_i7 = 23,    // i7 * 1
-} ARMII_AddrMode;
-
-inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
-{
-	switch (addrmode) {
-	case ARMII_AddrModeNone:
-		return "AddrModeNone";
-	case ARMII_AddrMode1:
-		return "AddrMode1";
-	case ARMII_AddrMode2:
-		return "AddrMode2";
-	case ARMII_AddrMode3:
-		return "AddrMode3";
-	case ARMII_AddrMode4:
-		return "AddrMode4";
-	case ARMII_AddrMode5:
-		return "AddrMode5";
-	case ARMII_AddrMode5FP16:
-		return "AddrMode5FP16";
-	case ARMII_AddrMode6:
-		return "AddrMode6";
-	case ARMII_AddrModeT1_1:
-		return "AddrModeT1_1";
-	case ARMII_AddrModeT1_2:
-		return "AddrModeT1_2";
-	case ARMII_AddrModeT1_4:
-		return "AddrModeT1_4";
-	case ARMII_AddrModeT1_s:
-		return "AddrModeT1_s";
-	case ARMII_AddrModeT2_i12:
-		return "AddrModeT2_i12";
-	case ARMII_AddrModeT2_i8:
-		return "AddrModeT2_i8";
-	case ARMII_AddrModeT2_i8pos:
-		return "AddrModeT2_i8pos";
-	case ARMII_AddrModeT2_i8neg:
-		return "AddrModeT2_i8neg";
-	case ARMII_AddrModeT2_so:
-		return "AddrModeT2_so";
-	case ARMII_AddrModeT2_pc:
-		return "AddrModeT2_pc";
-	case ARMII_AddrModeT2_i8s4:
-		return "AddrModeT2_i8s4";
-	case ARMII_AddrMode_i12:
-		return "AddrMode_i12";
-	case ARMII_AddrModeT2_ldrex:
-		return "AddrModeT2_ldrex";
-	case ARMII_AddrModeT2_i7s4:
-		return "AddrModeT2_i7s4";
-	case ARMII_AddrModeT2_i7s2:
-		return "AddrModeT2_i7s2";
-	case ARMII_AddrModeT2_i7:
-		return "AddrModeT2_i7";
-	}
-}
-
-/// Target Operand Flag enum.
-typedef enum TOF {
-	//===------------------------------------------------------------------===//
-	// ARM Specific MachineOperand flags.
-
-	ARMII_MO_NO_FLAG = 0,
-
-	/// MO_LO16 - On a symbol operand, this represents a relocation containing
-	/// lower 16 bit of the address. Used only via movw instruction.
-	ARMII_MO_LO16 = 0x1,
-
-	/// MO_HI16 - On a symbol operand, this represents a relocation containing
-	/// higher 16 bit of the address. Used only via movt instruction.
-	ARMII_MO_HI16 = 0x2,
-
-	/// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
-	/// just that part of the flag set.
-	ARMII_MO_OPTION_MASK = 0x3,
-
-	/// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
-	/// reference is actually to the ".refptr.FOO" symbol.  This is used for
-	/// stub symbols on windows.
-	ARMII_MO_COFFSTUB = 0x4,
-
-	/// MO_GOT - On a symbol operand, this represents a GOT relative relocation.
-	ARMII_MO_GOT = 0x8,
-
-	/// MO_SBREL - On a symbol operand, this represents a static base relative
-	/// relocation. Used in movw and movt instructions.
-	ARMII_MO_SBREL = 0x10,
-
-	/// MO_DLLIMPORT - On a symbol operand, this represents that the reference
-	/// to the symbol is for an import stub.  This is used for DLL import
-	/// storage class indication on Windows.
-	ARMII_MO_DLLIMPORT = 0x20,
-
-	/// MO_SECREL - On a symbol operand this indicates that the immediate is
-	/// the offset from beginning of section.
-	///
-	/// This is the TLS offset for the COFF/Windows TLS mechanism.
-	ARMII_MO_SECREL = 0x40,
-
-	/// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
-	/// represents a symbol which, if indirect, will get special Darwin mangling
-	/// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
-	/// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
-	/// example).
-	ARMII_MO_NONLAZY = 0x80,
-
-	// It's undefined behaviour if an enum overflows the range between its
-	// smallest and largest values, but since these are |ed together, it can
-	// happen. Put a sentinel in (values of this enum are stored as "unsigned
-	// char").
-	ARMII_MO_UNUSED_MAXIMUM = 0xff
-} ARMII_TOF;
-
-enum {
-	//===------------------------------------------------------------------===//
-	// Instruction Flags.
-
-	//===------------------------------------------------------------------===//
-	// This four-bit field describes the addressing mode used.
-	ARMII_AddrModeMask =
-		0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
-
-	// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
-	// and store ops only.  Generic "updating" flag is used for ld/st multiple.
-	// The index mode enums are declared in ARMBaseInfo.h
-	ARMII_IndexModeShift = 5,
-	ARMII_IndexModeMask = 3 << ARMII_IndexModeShift,
-
-	//===------------------------------------------------------------------===//
-	// Instruction encoding formats.
-	//
-	ARMII_FormShift = 7,
-	ARMII_FormMask = 0x3f << ARMII_FormShift,
-
-	// Pseudo instructions
-	ARMII_Pseudo = 0 << ARMII_FormShift,
-
-	// Multiply instructions
-	ARMII_MulFrm = 1 << ARMII_FormShift,
-
-	// Branch instructions
-	ARMII_BrFrm = 2 << ARMII_FormShift,
-	ARMII_BrMiscFrm = 3 << ARMII_FormShift,
-
-	// Data Processing instructions
-	ARMII_DPFrm = 4 << ARMII_FormShift,
-	ARMII_DPSoRegFrm = 5 << ARMII_FormShift,
-
-	// Load and Store
-	ARMII_LdFrm = 6 << ARMII_FormShift,
-	ARMII_StFrm = 7 << ARMII_FormShift,
-	ARMII_LdMiscFrm = 8 << ARMII_FormShift,
-	ARMII_StMiscFrm = 9 << ARMII_FormShift,
-	ARMII_LdStMulFrm = 10 << ARMII_FormShift,
-
-	ARMII_LdStExFrm = 11 << ARMII_FormShift,
-
-	// Miscellaneous arithmetic instructions
-	ARMII_ArithMiscFrm = 12 << ARMII_FormShift,
-	ARMII_SatFrm = 13 << ARMII_FormShift,
-
-	// Extend instructions
-	ARMII_ExtFrm = 14 << ARMII_FormShift,
-
-	// VFP formats
-	ARMII_VFPUnaryFrm = 15 << ARMII_FormShift,
-	ARMII_VFPBinaryFrm = 16 << ARMII_FormShift,
-	ARMII_VFPConv1Frm = 17 << ARMII_FormShift,
-	ARMII_VFPConv2Frm = 18 << ARMII_FormShift,
-	ARMII_VFPConv3Frm = 19 << ARMII_FormShift,
-	ARMII_VFPConv4Frm = 20 << ARMII_FormShift,
-	ARMII_VFPConv5Frm = 21 << ARMII_FormShift,
-	ARMII_VFPLdStFrm = 22 << ARMII_FormShift,
-	ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift,
-	ARMII_VFPMiscFrm = 24 << ARMII_FormShift,
-
-	// Thumb format
-	ARMII_ThumbFrm = 25 << ARMII_FormShift,
-
-	// Miscelleaneous format
-	ARMII_MiscFrm = 26 << ARMII_FormShift,
-
-	// NEON formats
-	ARMII_NGetLnFrm = 27 << ARMII_FormShift,
-	ARMII_NSetLnFrm = 28 << ARMII_FormShift,
-	ARMII_NDupFrm = 29 << ARMII_FormShift,
-	ARMII_NLdStFrm = 30 << ARMII_FormShift,
-	ARMII_N1RegModImmFrm = 31 << ARMII_FormShift,
-	ARMII_N2RegFrm = 32 << ARMII_FormShift,
-	ARMII_NVCVTFrm = 33 << ARMII_FormShift,
-	ARMII_NVDupLnFrm = 34 << ARMII_FormShift,
-	ARMII_N2RegVShLFrm = 35 << ARMII_FormShift,
-	ARMII_N2RegVShRFrm = 36 << ARMII_FormShift,
-	ARMII_N3RegFrm = 37 << ARMII_FormShift,
-	ARMII_N3RegVShFrm = 38 << ARMII_FormShift,
-	ARMII_NVExtFrm = 39 << ARMII_FormShift,
-	ARMII_NVMulSLFrm = 40 << ARMII_FormShift,
-	ARMII_NVTBLFrm = 41 << ARMII_FormShift,
-	ARMII_N3RegCplxFrm = 43 << ARMII_FormShift,
-
-	//===------------------------------------------------------------------===//
-	// Misc flags.
-
-	// UnaryDP - Indicates this is a unary data processing instruction, i.e.
-	// it doesn't have a Rn operand.
-	ARMII_UnaryDP = 1 << 13,
-
-	// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
-	// a 16-bit Thumb instruction if certain conditions are met.
-	ARMII_Xform16Bit = 1 << 14,
-
-	// ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
-	// instruction. Used by the parser to determine whether to require the 'S'
-	// suffix on the mnemonic (when not in an IT block) or preclude it (when
-	// in an IT block).
-	ARMII_ThumbArithFlagSetting = 1 << 19,
-
-	// Whether an instruction can be included in an MVE tail-predicated loop,
-	// though extra validity checks may need to be performed too.
-	ARMII_ValidForTailPredication = 1 << 20,
-
-	// Whether an instruction writes to the top/bottom half of a vector element
-	// and leaves the other half untouched.
-	ARMII_RetainsPreviousHalfElement = 1 << 21,
-
-	// Whether the instruction produces a scalar result from vector operands.
-	ARMII_HorizontalReduction = 1 << 22,
-
-	// Whether this instruction produces a vector result that is larger than
-	// its input, typically reading from the top/bottom halves of the input(s).
-	ARMII_DoubleWidthResult = 1 << 23,
-
-	// The vector element size for MVE instructions. 00 = i8, 01 = i16, 10 = i32
-	// and 11 = i64. This is the largest type if multiple are present, so a
-	// MVE_VMOVLs8bh is ize 01=i16, as it extends from a i8 to a i16. There are
-	// some caveats so cannot be used blindly, such as exchanging VMLADAVA's and
-	// complex instructions, which may use different input lanes.
-	ARMII_VecSizeShift = 24,
-	ARMII_VecSize = 3 << ARMII_VecSizeShift,
-
-	//===------------------------------------------------------------------===//
-	// Code domain.
-	ARMII_DomainShift = 15,
-	ARMII_DomainMask = 15 << ARMII_DomainShift,
-	ARMII_DomainGeneral = 0 << ARMII_DomainShift,
-	ARMII_DomainVFP = 1 << ARMII_DomainShift,
-	ARMII_DomainNEON = 2 << ARMII_DomainShift,
-	ARMII_DomainNEONA8 = 4 << ARMII_DomainShift,
-	ARMII_DomainMVE = 8 << ARMII_DomainShift,
-
-	//===------------------------------------------------------------------===//
-	// Field shifts - such shifts are used to set field while generating
-	// machine instructions.
-	//
-	// FIXME: This list will need adjusting/fixing as the MC code emitter
-	// takes shape and the ARMCodeEmitter.cpp bits go away.
-	ARMII_ShiftTypeShift = 4,
-
-	ARMII_M_BitShift = 5,
-	ARMII_ShiftImmShift = 5,
-	ARMII_ShiftShift = 7,
-	ARMII_N_BitShift = 7,
-	ARMII_ImmHiShift = 8,
-	ARMII_SoRotImmShift = 8,
-	ARMII_RegRsShift = 8,
-	ARMII_ExtRotImmShift = 10,
-	ARMII_RegRdLoShift = 12,
-	ARMII_RegRdShift = 12,
-	ARMII_RegRdHiShift = 16,
-	ARMII_RegRnShift = 16,
-	ARMII_S_BitShift = 20,
-	ARMII_W_BitShift = 21,
-	ARMII_AM3_I_BitShift = 22,
-	ARMII_D_BitShift = 22,
-	ARMII_U_BitShift = 23,
-	ARMII_P_BitShift = 24,
-	ARMII_I_BitShift = 25,
-	ARMII_CondShift = 28
-};
-
-const char *get_pred_mask(ARM_PredBlockMask pred_mask);
-
-#endif // CS_ARM_BASEINFO_H

thirdparty/capstone/arch/ARM/ARMDisassemblerExtension.c

@@ -1,238 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
-
-#include "ARMDisassemblerExtension.h"
-#include "ARMBaseInfo.h"
-
-bool ITBlock_push_back(ARM_ITBlock *it, char v)
-{
-	if (it->size >= sizeof(it->ITStates)) {
-		// TODO: consider warning user.
-		it->size = 0;
-	}
-	it->ITStates[it->size] = v;
-	it->size++;
-
-	return true;
-}
-
-// Returns true if the current instruction is in an IT block
-bool ITBlock_instrInITBlock(ARM_ITBlock *it)
-{
-	return (it->size > 0);
-}
-
-// Returns true if current instruction is the last instruction in an IT block
-bool ITBlock_instrLastInITBlock(ARM_ITBlock *it)
-{
-	return (it->size == 1);
-}
-
-// Returns the condition code for instruction in IT block
-unsigned ITBlock_getITCC(ARM_ITBlock *it)
-{
-	unsigned CC = ARMCC_AL;
-
-	if (ITBlock_instrInITBlock(it))
-		CC = it->ITStates[it->size - 1];
-
-	return CC;
-}
-
-// Advances the IT block state to the next T or E
-void ITBlock_advanceITState(ARM_ITBlock *it)
-{
-	it->size--;
-}
-
-// Called when decoding an IT instruction. Sets the IT state for the following
-// instructions that for the IT block. Firstcond and Mask correspond to the
-// fields in the IT instruction encoding.
-void ITBlock_setITState(ARM_ITBlock *it, char Firstcond, char Mask)
-{
-	// (3 - the number of trailing zeros) is the number of then / else.
-	unsigned NumTZ = CountTrailingZeros_8(Mask);
-	unsigned char CCBits = (unsigned char)(Firstcond & 0xf);
-	assert(NumTZ <= 3 && "Invalid IT mask!");
-	// push condition codes onto the stack the correct order for the pops
-	for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
-		unsigned Else = (Mask >> Pos) & 1;
-		ITBlock_push_back(it, CCBits ^ Else);
-	}
-	ITBlock_push_back(it, CCBits);
-}
-
-bool VPTBlock_push_back(ARM_VPTBlock *it, char v)
-{
-	if (it->size >= sizeof(it->VPTStates)) {
-		// TODO: consider warning user.
-		it->size = 0;
-	}
-	it->VPTStates[it->size] = v;
-	it->size++;
-
-	return true;
-}
-
-bool VPTBlock_instrInVPTBlock(ARM_VPTBlock *VPT)
-{
-	return VPT->size > 0;
-}
-
-unsigned VPTBlock_getVPTPred(ARM_VPTBlock *VPT)
-{
-	unsigned Pred = ARMVCC_None;
-	if (VPTBlock_instrInVPTBlock(VPT))
-		Pred = VPT->VPTStates[VPT->size - 1];
-	return Pred;
-}
-
-void VPTBlock_advanceVPTState(ARM_VPTBlock *VPT)
-{
-	VPT->size--;
-}
-
-void VPTBlock_setVPTState(ARM_VPTBlock *VPT, char Mask)
-{
-	// (3 - the number of trailing zeros) is the number of then / else.
-	unsigned NumTZ = CountTrailingZeros_8(Mask);
-	assert(NumTZ <= 3 && "Invalid VPT mask!");
-	// push predicates onto the stack the correct order for the pops
-	for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
-		bool T = ((Mask >> Pos) & 1) == 0;
-		if (T)
-			VPTBlock_push_back(VPT, ARMVCC_Then);
-		else
-			VPTBlock_push_back(VPT, ARMVCC_Else);
-	}
-	VPTBlock_push_back(VPT, ARMVCC_Then);
-}
-
-/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
-
-bool Check(DecodeStatus *Out, DecodeStatus In)
-{
-	switch (In) {
-	case MCDisassembler_Success:
-		// Out stays the same.
-		return true;
-	case MCDisassembler_SoftFail:
-		*Out = In;
-		return true;
-	case MCDisassembler_Fail:
-		*Out = In;
-		return false;
-	default: // never reached
-		return false;
-	}
-}
-
-// Imported from ARMBaseInstrInfo.h
-//
-/// isValidCoprocessorNumber - decide whether an explicit coprocessor
-/// number is legal in generic instructions like CDP. The answer can
-/// vary with the subtarget.
-bool isValidCoprocessorNumber(MCInst *Inst, unsigned Num)
-{
-	// In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
-	// coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
-	// useful for code which is shared with older architectures which do not
-	// know the new VFP/NEON mnemonics.
-
-	// Armv8-A disallows everything *other* than 111x (CP14 and CP15).
-	if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) &&
-	    (Num & 0xE) != 0xE)
-		return false;
-
-	// Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
-	// which clash with MVE.
-	if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps) &&
-	    ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
-		return false;
-
-	return true;
-}
-
-// Imported from ARMMCTargetDesc.h
-bool ARM_isVpred(arm_op_type op)
-{
-	return op == ARM_OP_VPRED_R || op == ARM_OP_VPRED_N;
-}
-
-// Imported from ARMBaseInstrInfo.h
-//
-// This table shows the VPT instruction variants, i.e. the different
-// mask field encodings, see also B5.6. Predication/conditional execution in
-// the ArmARM.
-bool isVPTOpcode(int Opc)
-{
-	return Opc == ARM_MVE_VPTv16i8 || Opc == ARM_MVE_VPTv16u8 ||
-	       Opc == ARM_MVE_VPTv16s8 || Opc == ARM_MVE_VPTv8i16 ||
-	       Opc == ARM_MVE_VPTv8u16 || Opc == ARM_MVE_VPTv8s16 ||
-	       Opc == ARM_MVE_VPTv4i32 || Opc == ARM_MVE_VPTv4u32 ||
-	       Opc == ARM_MVE_VPTv4s32 || Opc == ARM_MVE_VPTv4f32 ||
-	       Opc == ARM_MVE_VPTv8f16 || Opc == ARM_MVE_VPTv16i8r ||
-	       Opc == ARM_MVE_VPTv16u8r || Opc == ARM_MVE_VPTv16s8r ||
-	       Opc == ARM_MVE_VPTv8i16r || Opc == ARM_MVE_VPTv8u16r ||
-	       Opc == ARM_MVE_VPTv8s16r || Opc == ARM_MVE_VPTv4i32r ||
-	       Opc == ARM_MVE_VPTv4u32r || Opc == ARM_MVE_VPTv4s32r ||
-	       Opc == ARM_MVE_VPTv4f32r || Opc == ARM_MVE_VPTv8f16r ||
-	       Opc == ARM_MVE_VPST;
-}
-
-// Imported from ARMMCTargetDesc.cpp
-bool ARM_isCDECoproc(size_t Coproc, const MCInst *MI)
-{
-	// Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
-	// to rely on feature bits.
-	if (Coproc >= 8)
-		return false;
-
-	return ARM_getFeatureBits(MI->csh->mode,
-				  ARM_FeatureCoprocCDE0 + Coproc);
-}
-
-// Hacky: enable all features for disassembler
-bool ARM_getFeatureBits(unsigned int mode, unsigned int feature)
-{
-	if (feature == ARM_ModeThumb) {
-		if (mode & CS_MODE_THUMB)
-			return true;
-		return false;
-	}
-
-	if (feature == ARM_FeatureDFB)
-		return false;
-
-	if (feature == ARM_FeatureRAS)
-		return false;
-
-	if (feature == ARM_FeatureMClass && (mode & CS_MODE_MCLASS) == 0)
-		return false;
-
-	if ((feature == ARM_HasMVEIntegerOps || feature == ARM_HasMVEFloatOps ||
-	     feature == ARM_FeatureMVEVectorCostFactor1 ||
-	     feature == ARM_FeatureMVEVectorCostFactor2 ||
-	     feature == ARM_FeatureMVEVectorCostFactor4) &&
-	    (mode & CS_MODE_MCLASS) == 0)
-		return false;
-
-	if ((feature == ARM_HasV8Ops || feature == ARM_HasV8_1MMainlineOps ||
-	     feature == ARM_HasV8_1aOps || feature == ARM_HasV8_2aOps ||
-	     feature == ARM_HasV8_3aOps || feature == ARM_HasV8_4aOps ||
-	     feature == ARM_HasV8_5aOps || feature == ARM_HasV8_6aOps ||
-	     feature == ARM_HasV8_7aOps || feature == ARM_HasV8_8aOps ||
-	     feature == ARM_HasV8_9aOps) &&
-	    (mode & CS_MODE_V8) == 0)
-		return false;
-
-	if (feature >= ARM_FeatureCoprocCDE0 &&
-	    feature <= ARM_FeatureCoprocCDE7)
-		// We currently have no way to detect CDE (Custom-Datapath-Extension)
-		// coprocessors.
-		return false;
-
-	// we support everything
-	return true;
-}

thirdparty/capstone/arch/ARM/ARMDisassemblerExtension.h

@@ -1,51 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
-
-#ifndef CS_ARM_DISASSEMBLER_EXTENSION_H
-#define CS_ARM_DISASSEMBLER_EXTENSION_H
-
-#include "../../MCDisassembler.h"
-#include "../../MCRegisterInfo.h"
-#include "../../MathExtras.h"
-#include "../../cs_priv.h"
-#include "ARMAddressingModes.h"
-#include "capstone/capstone.h"
-
-unsigned ARM_AM_getAM5FP16Opc(ARM_AM_AddrOpc Opc, unsigned char Offset);
-
-bool ITBlock_push_back(ARM_ITBlock *it, char v);
-
-bool ITBlock_instrInITBlock(ARM_ITBlock *it);
-
-bool ITBlock_instrLastInITBlock(ARM_ITBlock *it);
-
-unsigned ITBlock_getITCC(ARM_ITBlock *it);
-
-void ITBlock_advanceITState(ARM_ITBlock *it);
-
-void ITBlock_setITState(ARM_ITBlock *it, char Firstcond, char Mask);
-
-bool Check(DecodeStatus *Out, DecodeStatus In);
-
-bool isValidCoprocessorNumber(MCInst *Inst, unsigned Num);
-
-bool ARM_isVpred(arm_op_type op);
-
-bool isVPTOpcode(int Opc);
-
-bool ARM_isCDECoproc(size_t Coproc, const MCInst *MI);
-
-bool VPTBlock_push_back(ARM_VPTBlock *it, char v);
-
-bool VPTBlock_instrInVPTBlock(ARM_VPTBlock *VPT);
-
-unsigned VPTBlock_getVPTPred(ARM_VPTBlock *VPT);
-
-void VPTBlock_advanceVPTState(ARM_VPTBlock *VPT);
-
-void VPTBlock_setVPTState(ARM_VPTBlock *VPT, char Mask);
-
-bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
-
-#endif // CS_ARM_DISASSEMBLER_EXTENSION_H

thirdparty/capstone/arch/ARM/ARMFeatureEnum.inc

@@ -1,22 +0,0 @@
-ARM_FEATURE_IsThumb = 128, ARM_FEATURE_IsARM, ARM_FEATURE_UseNegativeImmediates,
-	ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasAES,
-	ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, ARM_FEATURE_HasV7,
-	ARM_FEATURE_IsMClass, ARM_FEATURE_HasPACBTI, ARM_FEATURE_HasV8MBaseline,
-	ARM_FEATURE_HasLOB, ARM_FEATURE_HasV6T2, ARM_FEATURE_HasV5T,
-	ARM_FEATURE_IsNotMClass, ARM_FEATURE_Has8MSecExt, ARM_FEATURE_HasV4T,
-	ARM_FEATURE_PreV8, ARM_FEATURE_HasCLRBHB, ARM_FEATURE_HasV6K,
-	ARM_FEATURE_HasV7Clrex, ARM_FEATURE_HasCRC, ARM_FEATURE_HasCDE,
-	ARM_FEATURE_HasDFB, ARM_FEATURE_HasDB, ARM_FEATURE_HasVirtualization,
-	ARM_FEATURE_HasRAS, ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP,
-	ARM_FEATURE_HasVFP3, ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV6M,
-	ARM_FEATURE_HasV6, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV5TE,
-	ARM_FEATURE_HasDSP, ARM_FEATURE_HasMP, ARM_FEATURE_HasSB,
-	ARM_FEATURE_HasDivideInThumb, ARM_FEATURE_HasDivideInARM,
-	ARM_FEATURE_HasV8_1a, ARM_FEATURE_HasSHA2, ARM_FEATURE_HasTrustZone,
-	ARM_FEATURE_UseNaClTrap, ARM_FEATURE_HasV8_4a, ARM_FEATURE_HasNEON,
-	ARM_FEATURE_HasFullFP16, ARM_FEATURE_HasMVEFloat, ARM_FEATURE_HasV8_3a,
-	ARM_FEATURE_HasFP16, ARM_FEATURE_HasBF16, ARM_FEATURE_HasFPARMv8,
-	ARM_FEATURE_HasVFP4, ARM_FEATURE_HasFP16FML, ARM_FEATURE_HasFPRegs16,
-	ARM_FEATURE_HasV8MMainline, ARM_FEATURE_HasFPRegs64,
-	ARM_FEATURE_HasFPRegsV8_1M, ARM_FEATURE_HasDotProd,
-	ARM_FEATURE_HasMatMulInt8,

thirdparty/capstone/arch/ARM/ARMGenCSAliasMnemMap.inc

@@ -1,48 +0,0 @@
-/* Capstone Disassembly Engine, https://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
-/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
-
-/* LLVM-commit: <commit> */
-/* LLVM-tag: <tag> */
-
-/* Do not edit. */
-
-/* Capstone's LLVM TableGen Backends: */
-/* https://github.com/capstone-engine/llvm-capstone */
-
-	{ ARM_INS_ALIAS_VMOV, "vmov" },
-	{ ARM_INS_ALIAS_NOP, "nop" },
-	{ ARM_INS_ALIAS_YIELD, "yield" },
-	{ ARM_INS_ALIAS_WFE, "wfe" },
-	{ ARM_INS_ALIAS_WFI, "wfi" },
-	{ ARM_INS_ALIAS_SEV, "sev" },
-	{ ARM_INS_ALIAS_SEVL, "sevl" },
-	{ ARM_INS_ALIAS_ESB, "esb" },
-	{ ARM_INS_ALIAS_CSDB, "csdb" },
-	{ ARM_INS_ALIAS_CLRBHB, "clrbhb" },
-	{ ARM_INS_ALIAS_PACBTI, "pacbti" },
-	{ ARM_INS_ALIAS_BTI, "bti" },
-	{ ARM_INS_ALIAS_PAC, "pac" },
-	{ ARM_INS_ALIAS_AUT, "aut" },
-	{ ARM_INS_ALIAS_SSBB, "ssbb" },
-	{ ARM_INS_ALIAS_PSSBB, "pssbb" },
-	{ ARM_INS_ALIAS_DFB, "dfb" },
-	{ ARM_INS_ALIAS_CSETM, "csetm" },
-	{ ARM_INS_ALIAS_CSET, "cset" },
-	{ ARM_INS_ALIAS_CINC, "cinc" },
-	{ ARM_INS_ALIAS_CINV, "cinv" },
-	{ ARM_INS_ALIAS_CNEG, "cneg" },
-	{ ARM_INS_ALIAS_VMLAV, "vmlav" },
-	{ ARM_INS_ALIAS_VMLAVA, "vmlava" },
-	{ ARM_INS_ALIAS_VRMLALVH, "vrmlalvh" },
-	{ ARM_INS_ALIAS_VRMLALVHA, "vrmlalvha" },
-	{ ARM_INS_ALIAS_VMLALV, "vmlalv" },
-	{ ARM_INS_ALIAS_VMLALVA, "vmlalva" },
-	{ ARM_INS_ALIAS_VBIC, "vbic" },
-	{ ARM_INS_ALIAS_VEOR, "veor" },
-	{ ARM_INS_ALIAS_VORN, "vorn" },
-	{ ARM_INS_ALIAS_VORR, "vorr" },
-	{ ARM_INS_ALIAS_VAND, "vand" },
-	{ ARM_INS_ALIAS_VPSEL, "vpsel" },
-	{ ARM_INS_ALIAS_ERET, "eret" },

thirdparty/capstone/arch/ARM/ARMGenCSFeatureName.inc

@@ -1,60 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
-/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
-
-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
-
-/* Do not edit. */
-
-/* Capstone's LLVM TableGen Backends: */
-/* https://github.com/capstone-engine/llvm-capstone */
-
-{ ARM_FEATURE_IsARM, "IsARM" }, { ARM_FEATURE_HasV5T, "HasV5T" },
-	{ ARM_FEATURE_HasV4T, "HasV4T" }, { ARM_FEATURE_HasVFP2, "HasVFP2" },
-	{ ARM_FEATURE_HasV5TE, "HasV5TE" }, { ARM_FEATURE_HasV6T2, "HasV6T2" },
-	{ ARM_FEATURE_HasMVEInt, "HasMVEInt" },
-	{ ARM_FEATURE_HasNEON, "HasNEON" },
-	{ ARM_FEATURE_HasFPRegs64, "HasFPRegs64" },
-	{ ARM_FEATURE_HasFPRegs, "HasFPRegs" },
-	{ ARM_FEATURE_IsThumb2, "IsThumb2" },
-	{ ARM_FEATURE_HasV8_1MMainline, "HasV8_1MMainline" },
-	{ ARM_FEATURE_HasLOB, "HasLOB" }, { ARM_FEATURE_IsThumb, "IsThumb" },
-	{ ARM_FEATURE_HasV8MBaseline, "HasV8MBaseline" },
-	{ ARM_FEATURE_Has8MSecExt, "Has8MSecExt" },
-	{ ARM_FEATURE_HasV8, "HasV8" }, { ARM_FEATURE_HasAES, "HasAES" },
-	{ ARM_FEATURE_HasBF16, "HasBF16" }, { ARM_FEATURE_HasCDE, "HasCDE" },
-	{ ARM_FEATURE_PreV8, "PreV8" }, { ARM_FEATURE_HasV6K, "HasV6K" },
-	{ ARM_FEATURE_HasCRC, "HasCRC" }, { ARM_FEATURE_HasV7, "HasV7" },
-	{ ARM_FEATURE_HasDB, "HasDB" },
-	{ ARM_FEATURE_HasVirtualization, "HasVirtualization" },
-	{ ARM_FEATURE_HasVFP3, "HasVFP3" },
-	{ ARM_FEATURE_HasDPVFP, "HasDPVFP" },
-	{ ARM_FEATURE_HasFullFP16, "HasFullFP16" },
-	{ ARM_FEATURE_HasV6, "HasV6" },
-	{ ARM_FEATURE_HasAcquireRelease, "HasAcquireRelease" },
-	{ ARM_FEATURE_HasV7Clrex, "HasV7Clrex" },
-	{ ARM_FEATURE_HasMVEFloat, "HasMVEFloat" },
-	{ ARM_FEATURE_HasFPRegsV8_1M, "HasFPRegsV8_1M" },
-	{ ARM_FEATURE_HasMP, "HasMP" }, { ARM_FEATURE_HasSB, "HasSB" },
-	{ ARM_FEATURE_HasDivideInARM, "HasDivideInARM" },
-	{ ARM_FEATURE_HasV8_1a, "HasV8_1a" },
-	{ ARM_FEATURE_HasSHA2, "HasSHA2" },
-	{ ARM_FEATURE_HasTrustZone, "HasTrustZone" },
-	{ ARM_FEATURE_UseNaClTrap, "UseNaClTrap" },
-	{ ARM_FEATURE_HasV8_4a, "HasV8_4a" },
-	{ ARM_FEATURE_HasV8_3a, "HasV8_3a" },
-	{ ARM_FEATURE_HasFPARMv8, "HasFPARMv8" },
-	{ ARM_FEATURE_HasFP16, "HasFP16" }, { ARM_FEATURE_HasVFP4, "HasVFP4" },
-	{ ARM_FEATURE_HasFP16FML, "HasFP16FML" },
-	{ ARM_FEATURE_HasFPRegs16, "HasFPRegs16" },
-	{ ARM_FEATURE_HasV8MMainline, "HasV8MMainline" },
-	{ ARM_FEATURE_HasDotProd, "HasDotProd" },
-	{ ARM_FEATURE_HasMatMulInt8, "HasMatMulInt8" },
-	{ ARM_FEATURE_IsMClass, "IsMClass" },
-	{ ARM_FEATURE_HasPACBTI, "HasPACBTI" },
-	{ ARM_FEATURE_IsNotMClass, "IsNotMClass" },
-	{ ARM_FEATURE_HasDSP, "HasDSP" },
-	{ ARM_FEATURE_HasDivideInThumb, "HasDivideInThumb" },
-	{ ARM_FEATURE_HasV6M, "HasV6M" },

thirdparty/capstone/arch/ARM/ARMGenCSMappingInsnName.inc

@@ -1,650 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
-/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
-
-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
-
-/* Do not edit. */
-
-/* Capstone's LLVM TableGen Backends: */
-/* https://github.com/capstone-engine/llvm-capstone */
-
-"invalid",		// ARM_INS_INVALID
-	"asr",		// ARM_INS_ASR
-	"it",		// ARM_INS_IT
-	"ldrbt",	// ARM_INS_LDRBT
-	"ldr",		// ARM_INS_LDR
-	"ldrht",	// ARM_INS_LDRHT
-	"ldrsbt",	// ARM_INS_LDRSBT
-	"ldrsht",	// ARM_INS_LDRSHT
-	"ldrt",		// ARM_INS_LDRT
-	"lsl",		// ARM_INS_LSL
-	"lsr",		// ARM_INS_LSR
-	"ror",		// ARM_INS_ROR
-	"rrx",		// ARM_INS_RRX
-	"strbt",	// ARM_INS_STRBT
-	"strt",		// ARM_INS_STRT
-	"vld1",		// ARM_INS_VLD1
-	"vld2",		// ARM_INS_VLD2
-	"vld3",		// ARM_INS_VLD3
-	"vld4",		// ARM_INS_VLD4
-	"vst1",		// ARM_INS_VST1
-	"vst2",		// ARM_INS_VST2
-	"vst3",		// ARM_INS_VST3
-	"vst4",		// ARM_INS_VST4
-	"ldrb",		// ARM_INS_LDRB
-	"ldrh",		// ARM_INS_LDRH
-	"ldrsb",	// ARM_INS_LDRSB
-	"ldrsh",	// ARM_INS_LDRSH
-	"movs",		// ARM_INS_MOVS
-	"mov",		// ARM_INS_MOV
-	"str",		// ARM_INS_STR
-	"adc",		// ARM_INS_ADC
-	"add",		// ARM_INS_ADD
-	"adr",		// ARM_INS_ADR
-	"aesd",		// ARM_INS_AESD
-	"aese",		// ARM_INS_AESE
-	"aesimc",	// ARM_INS_AESIMC
-	"aesmc",	// ARM_INS_AESMC
-	"and",		// ARM_INS_AND
-	"vdot",		// ARM_INS_VDOT
-	"vcvt",		// ARM_INS_VCVT
-	"vcvtb",	// ARM_INS_VCVTB
-	"vcvtt",	// ARM_INS_VCVTT
-	"bfc",		// ARM_INS_BFC
-	"bfi",		// ARM_INS_BFI
-	"bic",		// ARM_INS_BIC
-	"bkpt",		// ARM_INS_BKPT
-	"bl",		// ARM_INS_BL
-	"blx",		// ARM_INS_BLX
-	"bx",		// ARM_INS_BX
-	"bxj",		// ARM_INS_BXJ
-	"b",		// ARM_INS_B
-	"cx1",		// ARM_INS_CX1
-	"cx1a",		// ARM_INS_CX1A
-	"cx1d",		// ARM_INS_CX1D
-	"cx1da",	// ARM_INS_CX1DA
-	"cx2",		// ARM_INS_CX2
-	"cx2a",		// ARM_INS_CX2A
-	"cx2d",		// ARM_INS_CX2D
-	"cx2da",	// ARM_INS_CX2DA
-	"cx3",		// ARM_INS_CX3
-	"cx3a",		// ARM_INS_CX3A
-	"cx3d",		// ARM_INS_CX3D
-	"cx3da",	// ARM_INS_CX3DA
-	"vcx1a",	// ARM_INS_VCX1A
-	"vcx1",		// ARM_INS_VCX1
-	"vcx2a",	// ARM_INS_VCX2A
-	"vcx2",		// ARM_INS_VCX2
-	"vcx3a",	// ARM_INS_VCX3A
-	"vcx3",		// ARM_INS_VCX3
-	"cdp",		// ARM_INS_CDP
-	"cdp2",		// ARM_INS_CDP2
-	"clrex",	// ARM_INS_CLREX
-	"clz",		// ARM_INS_CLZ
-	"cmn",		// ARM_INS_CMN
-	"cmp",		// ARM_INS_CMP
-	"cps",		// ARM_INS_CPS
-	"crc32b",	// ARM_INS_CRC32B
-	"crc32cb",	// ARM_INS_CRC32CB
-	"crc32ch",	// ARM_INS_CRC32CH
-	"crc32cw",	// ARM_INS_CRC32CW
-	"crc32h",	// ARM_INS_CRC32H
-	"crc32w",	// ARM_INS_CRC32W
-	"dbg",		// ARM_INS_DBG
-	"dmb",		// ARM_INS_DMB
-	"dsb",		// ARM_INS_DSB
-	"eor",		// ARM_INS_EOR
-	"eret",		// ARM_INS_ERET
-	"vmov",		// ARM_INS_VMOV
-	"fldmdbx",	// ARM_INS_FLDMDBX
-	"fldmiax",	// ARM_INS_FLDMIAX
-	"vmrs",		// ARM_INS_VMRS
-	"fstmdbx",	// ARM_INS_FSTMDBX
-	"fstmiax",	// ARM_INS_FSTMIAX
-	"hint",		// ARM_INS_HINT
-	"hlt",		// ARM_INS_HLT
-	"hvc",		// ARM_INS_HVC
-	"isb",		// ARM_INS_ISB
-	"lda",		// ARM_INS_LDA
-	"ldab",		// ARM_INS_LDAB
-	"ldaex",	// ARM_INS_LDAEX
-	"ldaexb",	// ARM_INS_LDAEXB
-	"ldaexd",	// ARM_INS_LDAEXD
-	"ldaexh",	// ARM_INS_LDAEXH
-	"ldah",		// ARM_INS_LDAH
-	"ldc2l",	// ARM_INS_LDC2L
-	"ldc2",		// ARM_INS_LDC2
-	"ldcl",		// ARM_INS_LDCL
-	"ldc",		// ARM_INS_LDC
-	"ldmda",	// ARM_INS_LDMDA
-	"ldmdb",	// ARM_INS_LDMDB
-	"ldm",		// ARM_INS_LDM
-	"ldmib",	// ARM_INS_LDMIB
-	"ldrd",		// ARM_INS_LDRD
-	"ldrex",	// ARM_INS_LDREX
-	"ldrexb",	// ARM_INS_LDREXB
-	"ldrexd",	// ARM_INS_LDREXD
-	"ldrexh",	// ARM_INS_LDREXH
-	"mcr",		// ARM_INS_MCR
-	"mcr2",		// ARM_INS_MCR2
-	"mcrr",		// ARM_INS_MCRR
-	"mcrr2",	// ARM_INS_MCRR2
-	"mla",		// ARM_INS_MLA
-	"mls",		// ARM_INS_MLS
-	"movt",		// ARM_INS_MOVT
-	"movw",		// ARM_INS_MOVW
-	"mrc",		// ARM_INS_MRC
-	"mrc2",		// ARM_INS_MRC2
-	"mrrc",		// ARM_INS_MRRC
-	"mrrc2",	// ARM_INS_MRRC2
-	"mrs",		// ARM_INS_MRS
-	"msr",		// ARM_INS_MSR
-	"mul",		// ARM_INS_MUL
-	"asrl",		// ARM_INS_ASRL
-	"dlstp",	// ARM_INS_DLSTP
-	"lctp",		// ARM_INS_LCTP
-	"letp",		// ARM_INS_LETP
-	"lsll",		// ARM_INS_LSLL
-	"lsrl",		// ARM_INS_LSRL
-	"sqrshr",	// ARM_INS_SQRSHR
-	"sqrshrl",	// ARM_INS_SQRSHRL
-	"sqshl",	// ARM_INS_SQSHL
-	"sqshll",	// ARM_INS_SQSHLL
-	"srshr",	// ARM_INS_SRSHR
-	"srshrl",	// ARM_INS_SRSHRL
-	"uqrshl",	// ARM_INS_UQRSHL
-	"uqrshll",	// ARM_INS_UQRSHLL
-	"uqshl",	// ARM_INS_UQSHL
-	"uqshll",	// ARM_INS_UQSHLL
-	"urshr",	// ARM_INS_URSHR
-	"urshrl",	// ARM_INS_URSHRL
-	"vabav",	// ARM_INS_VABAV
-	"vabd",		// ARM_INS_VABD
-	"vabs",		// ARM_INS_VABS
-	"vadc",		// ARM_INS_VADC
-	"vadci",	// ARM_INS_VADCI
-	"vaddlva",	// ARM_INS_VADDLVA
-	"vaddlv",	// ARM_INS_VADDLV
-	"vaddva",	// ARM_INS_VADDVA
-	"vaddv",	// ARM_INS_VADDV
-	"vadd",		// ARM_INS_VADD
-	"vand",		// ARM_INS_VAND
-	"vbic",		// ARM_INS_VBIC
-	"vbrsr",	// ARM_INS_VBRSR
-	"vcadd",	// ARM_INS_VCADD
-	"vcls",		// ARM_INS_VCLS
-	"vclz",		// ARM_INS_VCLZ
-	"vcmla",	// ARM_INS_VCMLA
-	"vcmp",		// ARM_INS_VCMP
-	"vcmul",	// ARM_INS_VCMUL
-	"vctp",		// ARM_INS_VCTP
-	"vcvta",	// ARM_INS_VCVTA
-	"vcvtm",	// ARM_INS_VCVTM
-	"vcvtn",	// ARM_INS_VCVTN
-	"vcvtp",	// ARM_INS_VCVTP
-	"vddup",	// ARM_INS_VDDUP
-	"vdup",		// ARM_INS_VDUP
-	"vdwdup",	// ARM_INS_VDWDUP
-	"veor",		// ARM_INS_VEOR
-	"vfmas",	// ARM_INS_VFMAS
-	"vfma",		// ARM_INS_VFMA
-	"vfms",		// ARM_INS_VFMS
-	"vhadd",	// ARM_INS_VHADD
-	"vhcadd",	// ARM_INS_VHCADD
-	"vhsub",	// ARM_INS_VHSUB
-	"vidup",	// ARM_INS_VIDUP
-	"viwdup",	// ARM_INS_VIWDUP
-	"vld20",	// ARM_INS_VLD20
-	"vld21",	// ARM_INS_VLD21
-	"vld40",	// ARM_INS_VLD40
-	"vld41",	// ARM_INS_VLD41
-	"vld42",	// ARM_INS_VLD42
-	"vld43",	// ARM_INS_VLD43
-	"vldrb",	// ARM_INS_VLDRB
-	"vldrd",	// ARM_INS_VLDRD
-	"vldrh",	// ARM_INS_VLDRH
-	"vldrw",	// ARM_INS_VLDRW
-	"vmaxav",	// ARM_INS_VMAXAV
-	"vmaxa",	// ARM_INS_VMAXA
-	"vmaxnmav",	// ARM_INS_VMAXNMAV
-	"vmaxnma",	// ARM_INS_VMAXNMA
-	"vmaxnmv",	// ARM_INS_VMAXNMV
-	"vmaxnm",	// ARM_INS_VMAXNM
-	"vmaxv",	// ARM_INS_VMAXV
-	"vmax",		// ARM_INS_VMAX
-	"vminav",	// ARM_INS_VMINAV
-	"vmina",	// ARM_INS_VMINA
-	"vminnmav",	// ARM_INS_VMINNMAV
-	"vminnma",	// ARM_INS_VMINNMA
-	"vminnmv",	// ARM_INS_VMINNMV
-	"vminnm",	// ARM_INS_VMINNM
-	"vminv",	// ARM_INS_VMINV
-	"vmin",		// ARM_INS_VMIN
-	"vmladava",	// ARM_INS_VMLADAVA
-	"vmladavax",	// ARM_INS_VMLADAVAX
-	"vmladav",	// ARM_INS_VMLADAV
-	"vmladavx",	// ARM_INS_VMLADAVX
-	"vmlaldava",	// ARM_INS_VMLALDAVA
-	"vmlaldavax",	// ARM_INS_VMLALDAVAX
-	"vmlaldav",	// ARM_INS_VMLALDAV
-	"vmlaldavx",	// ARM_INS_VMLALDAVX
-	"vmlas",	// ARM_INS_VMLAS
-	"vmla",		// ARM_INS_VMLA
-	"vmlsdava",	// ARM_INS_VMLSDAVA
-	"vmlsdavax",	// ARM_INS_VMLSDAVAX
-	"vmlsdav",	// ARM_INS_VMLSDAV
-	"vmlsdavx",	// ARM_INS_VMLSDAVX
-	"vmlsldava",	// ARM_INS_VMLSLDAVA
-	"vmlsldavax",	// ARM_INS_VMLSLDAVAX
-	"vmlsldav",	// ARM_INS_VMLSLDAV
-	"vmlsldavx",	// ARM_INS_VMLSLDAVX
-	"vmovlb",	// ARM_INS_VMOVLB
-	"vmovlt",	// ARM_INS_VMOVLT
-	"vmovnb",	// ARM_INS_VMOVNB
-	"vmovnt",	// ARM_INS_VMOVNT
-	"vmulh",	// ARM_INS_VMULH
-	"vmullb",	// ARM_INS_VMULLB
-	"vmullt",	// ARM_INS_VMULLT
-	"vmul",		// ARM_INS_VMUL
-	"vmvn",		// ARM_INS_VMVN
-	"vneg",		// ARM_INS_VNEG
-	"vorn",		// ARM_INS_VORN
-	"vorr",		// ARM_INS_VORR
-	"vpnot",	// ARM_INS_VPNOT
-	"vpsel",	// ARM_INS_VPSEL
-	"vpst",		// ARM_INS_VPST
-	"vpt",		// ARM_INS_VPT
-	"vqabs",	// ARM_INS_VQABS
-	"vqadd",	// ARM_INS_VQADD
-	"vqdmladhx",	// ARM_INS_VQDMLADHX
-	"vqdmladh",	// ARM_INS_VQDMLADH
-	"vqdmlah",	// ARM_INS_VQDMLAH
-	"vqdmlash",	// ARM_INS_VQDMLASH
-	"vqdmlsdhx",	// ARM_INS_VQDMLSDHX
-	"vqdmlsdh",	// ARM_INS_VQDMLSDH
-	"vqdmulh",	// ARM_INS_VQDMULH
-	"vqdmullb",	// ARM_INS_VQDMULLB
-	"vqdmullt",	// ARM_INS_VQDMULLT
-	"vqmovnb",	// ARM_INS_VQMOVNB
-	"vqmovnt",	// ARM_INS_VQMOVNT
-	"vqmovunb",	// ARM_INS_VQMOVUNB
-	"vqmovunt",	// ARM_INS_VQMOVUNT
-	"vqneg",	// ARM_INS_VQNEG
-	"vqrdmladhx",	// ARM_INS_VQRDMLADHX
-	"vqrdmladh",	// ARM_INS_VQRDMLADH
-	"vqrdmlah",	// ARM_INS_VQRDMLAH
-	"vqrdmlash",	// ARM_INS_VQRDMLASH
-	"vqrdmlsdhx",	// ARM_INS_VQRDMLSDHX
-	"vqrdmlsdh",	// ARM_INS_VQRDMLSDH
-	"vqrdmulh",	// ARM_INS_VQRDMULH
-	"vqrshl",	// ARM_INS_VQRSHL
-	"vqrshrnb",	// ARM_INS_VQRSHRNB
-	"vqrshrnt",	// ARM_INS_VQRSHRNT
-	"vqrshrunb",	// ARM_INS_VQRSHRUNB
-	"vqrshrunt",	// ARM_INS_VQRSHRUNT
-	"vqshlu",	// ARM_INS_VQSHLU
-	"vqshl",	// ARM_INS_VQSHL
-	"vqshrnb",	// ARM_INS_VQSHRNB
-	"vqshrnt",	// ARM_INS_VQSHRNT
-	"vqshrunb",	// ARM_INS_VQSHRUNB
-	"vqshrunt",	// ARM_INS_VQSHRUNT
-	"vqsub",	// ARM_INS_VQSUB
-	"vrev16",	// ARM_INS_VREV16
-	"vrev32",	// ARM_INS_VREV32
-	"vrev64",	// ARM_INS_VREV64
-	"vrhadd",	// ARM_INS_VRHADD
-	"vrinta",	// ARM_INS_VRINTA
-	"vrintm",	// ARM_INS_VRINTM
-	"vrintn",	// ARM_INS_VRINTN
-	"vrintp",	// ARM_INS_VRINTP
-	"vrintx",	// ARM_INS_VRINTX
-	"vrintz",	// ARM_INS_VRINTZ
-	"vrmlaldavha",	// ARM_INS_VRMLALDAVHA
-	"vrmlaldavhax", // ARM_INS_VRMLALDAVHAX
-	"vrmlaldavh",	// ARM_INS_VRMLALDAVH
-	"vrmlaldavhx",	// ARM_INS_VRMLALDAVHX
-	"vrmlsldavha",	// ARM_INS_VRMLSLDAVHA
-	"vrmlsldavhax", // ARM_INS_VRMLSLDAVHAX
-	"vrmlsldavh",	// ARM_INS_VRMLSLDAVH
-	"vrmlsldavhx",	// ARM_INS_VRMLSLDAVHX
-	"vrmulh",	// ARM_INS_VRMULH
-	"vrshl",	// ARM_INS_VRSHL
-	"vrshrnb",	// ARM_INS_VRSHRNB
-	"vrshrnt",	// ARM_INS_VRSHRNT
-	"vrshr",	// ARM_INS_VRSHR
-	"vsbc",		// ARM_INS_VSBC
-	"vsbci",	// ARM_INS_VSBCI
-	"vshlc",	// ARM_INS_VSHLC
-	"vshllb",	// ARM_INS_VSHLLB
-	"vshllt",	// ARM_INS_VSHLLT
-	"vshl",		// ARM_INS_VSHL
-	"vshrnb",	// ARM_INS_VSHRNB
-	"vshrnt",	// ARM_INS_VSHRNT
-	"vshr",		// ARM_INS_VSHR
-	"vsli",		// ARM_INS_VSLI
-	"vsri",		// ARM_INS_VSRI
-	"vst20",	// ARM_INS_VST20
-	"vst21",	// ARM_INS_VST21
-	"vst40",	// ARM_INS_VST40
-	"vst41",	// ARM_INS_VST41
-	"vst42",	// ARM_INS_VST42
-	"vst43",	// ARM_INS_VST43
-	"vstrb",	// ARM_INS_VSTRB
-	"vstrd",	// ARM_INS_VSTRD
-	"vstrh",	// ARM_INS_VSTRH
-	"vstrw",	// ARM_INS_VSTRW
-	"vsub",		// ARM_INS_VSUB
-	"wlstp",	// ARM_INS_WLSTP
-	"mvn",		// ARM_INS_MVN
-	"orr",		// ARM_INS_ORR
-	"pkhbt",	// ARM_INS_PKHBT
-	"pkhtb",	// ARM_INS_PKHTB
-	"pldw",		// ARM_INS_PLDW
-	"pld",		// ARM_INS_PLD
-	"pli",		// ARM_INS_PLI
-	"qadd",		// ARM_INS_QADD
-	"qadd16",	// ARM_INS_QADD16
-	"qadd8",	// ARM_INS_QADD8
-	"qasx",		// ARM_INS_QASX
-	"qdadd",	// ARM_INS_QDADD
-	"qdsub",	// ARM_INS_QDSUB
-	"qsax",		// ARM_INS_QSAX
-	"qsub",		// ARM_INS_QSUB
-	"qsub16",	// ARM_INS_QSUB16
-	"qsub8",	// ARM_INS_QSUB8
-	"rbit",		// ARM_INS_RBIT
-	"rev",		// ARM_INS_REV
-	"rev16",	// ARM_INS_REV16
-	"revsh",	// ARM_INS_REVSH
-	"rfeda",	// ARM_INS_RFEDA
-	"rfedb",	// ARM_INS_RFEDB
-	"rfeia",	// ARM_INS_RFEIA
-	"rfeib",	// ARM_INS_RFEIB
-	"rsb",		// ARM_INS_RSB
-	"rsc",		// ARM_INS_RSC
-	"sadd16",	// ARM_INS_SADD16
-	"sadd8",	// ARM_INS_SADD8
-	"sasx",		// ARM_INS_SASX
-	"sb",		// ARM_INS_SB
-	"sbc",		// ARM_INS_SBC
-	"sbfx",		// ARM_INS_SBFX
-	"sdiv",		// ARM_INS_SDIV
-	"sel",		// ARM_INS_SEL
-	"setend",	// ARM_INS_SETEND
-	"setpan",	// ARM_INS_SETPAN
-	"sha1c",	// ARM_INS_SHA1C
-	"sha1h",	// ARM_INS_SHA1H
-	"sha1m",	// ARM_INS_SHA1M
-	"sha1p",	// ARM_INS_SHA1P
-	"sha1su0",	// ARM_INS_SHA1SU0
-	"sha1su1",	// ARM_INS_SHA1SU1
-	"sha256h",	// ARM_INS_SHA256H
-	"sha256h2",	// ARM_INS_SHA256H2
-	"sha256su0",	// ARM_INS_SHA256SU0
-	"sha256su1",	// ARM_INS_SHA256SU1
-	"shadd16",	// ARM_INS_SHADD16
-	"shadd8",	// ARM_INS_SHADD8
-	"shasx",	// ARM_INS_SHASX
-	"shsax",	// ARM_INS_SHSAX
-	"shsub16",	// ARM_INS_SHSUB16
-	"shsub8",	// ARM_INS_SHSUB8
-	"smc",		// ARM_INS_SMC
-	"smlabb",	// ARM_INS_SMLABB
-	"smlabt",	// ARM_INS_SMLABT
-	"smlad",	// ARM_INS_SMLAD
-	"smladx",	// ARM_INS_SMLADX
-	"smlal",	// ARM_INS_SMLAL
-	"smlalbb",	// ARM_INS_SMLALBB
-	"smlalbt",	// ARM_INS_SMLALBT
-	"smlald",	// ARM_INS_SMLALD
-	"smlaldx",	// ARM_INS_SMLALDX
-	"smlaltb",	// ARM_INS_SMLALTB
-	"smlaltt",	// ARM_INS_SMLALTT
-	"smlatb",	// ARM_INS_SMLATB
-	"smlatt",	// ARM_INS_SMLATT
-	"smlawb",	// ARM_INS_SMLAWB
-	"smlawt",	// ARM_INS_SMLAWT
-	"smlsd",	// ARM_INS_SMLSD
-	"smlsdx",	// ARM_INS_SMLSDX
-	"smlsld",	// ARM_INS_SMLSLD
-	"smlsldx",	// ARM_INS_SMLSLDX
-	"smmla",	// ARM_INS_SMMLA
-	"smmlar",	// ARM_INS_SMMLAR
-	"smmls",	// ARM_INS_SMMLS
-	"smmlsr",	// ARM_INS_SMMLSR
-	"smmul",	// ARM_INS_SMMUL
-	"smmulr",	// ARM_INS_SMMULR
-	"smuad",	// ARM_INS_SMUAD
-	"smuadx",	// ARM_INS_SMUADX
-	"smulbb",	// ARM_INS_SMULBB
-	"smulbt",	// ARM_INS_SMULBT
-	"smull",	// ARM_INS_SMULL
-	"smultb",	// ARM_INS_SMULTB
-	"smultt",	// ARM_INS_SMULTT
-	"smulwb",	// ARM_INS_SMULWB
-	"smulwt",	// ARM_INS_SMULWT
-	"smusd",	// ARM_INS_SMUSD
-	"smusdx",	// ARM_INS_SMUSDX
-	"srsda",	// ARM_INS_SRSDA
-	"srsdb",	// ARM_INS_SRSDB
-	"srsia",	// ARM_INS_SRSIA
-	"srsib",	// ARM_INS_SRSIB
-	"ssat",		// ARM_INS_SSAT
-	"ssat16",	// ARM_INS_SSAT16
-	"ssax",		// ARM_INS_SSAX
-	"ssub16",	// ARM_INS_SSUB16
-	"ssub8",	// ARM_INS_SSUB8
-	"stc2l",	// ARM_INS_STC2L
-	"stc2",		// ARM_INS_STC2
-	"stcl",		// ARM_INS_STCL
-	"stc",		// ARM_INS_STC
-	"stl",		// ARM_INS_STL
-	"stlb",		// ARM_INS_STLB
-	"stlex",	// ARM_INS_STLEX
-	"stlexb",	// ARM_INS_STLEXB
-	"stlexd",	// ARM_INS_STLEXD
-	"stlexh",	// ARM_INS_STLEXH
-	"stlh",		// ARM_INS_STLH
-	"stmda",	// ARM_INS_STMDA
-	"stmdb",	// ARM_INS_STMDB
-	"stm",		// ARM_INS_STM
-	"stmib",	// ARM_INS_STMIB
-	"strb",		// ARM_INS_STRB
-	"strd",		// ARM_INS_STRD
-	"strex",	// ARM_INS_STREX
-	"strexb",	// ARM_INS_STREXB
-	"strexd",	// ARM_INS_STREXD
-	"strexh",	// ARM_INS_STREXH
-	"strh",		// ARM_INS_STRH
-	"strht",	// ARM_INS_STRHT
-	"sub",		// ARM_INS_SUB
-	"svc",		// ARM_INS_SVC
-	"swp",		// ARM_INS_SWP
-	"swpb",		// ARM_INS_SWPB
-	"sxtab",	// ARM_INS_SXTAB
-	"sxtab16",	// ARM_INS_SXTAB16
-	"sxtah",	// ARM_INS_SXTAH
-	"sxtb",		// ARM_INS_SXTB
-	"sxtb16",	// ARM_INS_SXTB16
-	"sxth",		// ARM_INS_SXTH
-	"teq",		// ARM_INS_TEQ
-	"trap",		// ARM_INS_TRAP
-	"tsb",		// ARM_INS_TSB
-	"tst",		// ARM_INS_TST
-	"uadd16",	// ARM_INS_UADD16
-	"uadd8",	// ARM_INS_UADD8
-	"uasx",		// ARM_INS_UASX
-	"ubfx",		// ARM_INS_UBFX
-	"udf",		// ARM_INS_UDF
-	"udiv",		// ARM_INS_UDIV
-	"uhadd16",	// ARM_INS_UHADD16
-	"uhadd8",	// ARM_INS_UHADD8
-	"uhasx",	// ARM_INS_UHASX
-	"uhsax",	// ARM_INS_UHSAX
-	"uhsub16",	// ARM_INS_UHSUB16
-	"uhsub8",	// ARM_INS_UHSUB8
-	"umaal",	// ARM_INS_UMAAL
-	"umlal",	// ARM_INS_UMLAL
-	"umull",	// ARM_INS_UMULL
-	"uqadd16",	// ARM_INS_UQADD16
-	"uqadd8",	// ARM_INS_UQADD8
-	"uqasx",	// ARM_INS_UQASX
-	"uqsax",	// ARM_INS_UQSAX
-	"uqsub16",	// ARM_INS_UQSUB16
-	"uqsub8",	// ARM_INS_UQSUB8
-	"usad8",	// ARM_INS_USAD8
-	"usada8",	// ARM_INS_USADA8
-	"usat",		// ARM_INS_USAT
-	"usat16",	// ARM_INS_USAT16
-	"usax",		// ARM_INS_USAX
-	"usub16",	// ARM_INS_USUB16
-	"usub8",	// ARM_INS_USUB8
-	"uxtab",	// ARM_INS_UXTAB
-	"uxtab16",	// ARM_INS_UXTAB16
-	"uxtah",	// ARM_INS_UXTAH
-	"uxtb",		// ARM_INS_UXTB
-	"uxtb16",	// ARM_INS_UXTB16
-	"uxth",		// ARM_INS_UXTH
-	"vabal",	// ARM_INS_VABAL
-	"vaba",		// ARM_INS_VABA
-	"vabdl",	// ARM_INS_VABDL
-	"vacge",	// ARM_INS_VACGE
-	"vacgt",	// ARM_INS_VACGT
-	"vaddhn",	// ARM_INS_VADDHN
-	"vaddl",	// ARM_INS_VADDL
-	"vaddw",	// ARM_INS_VADDW
-	"vfmab",	// ARM_INS_VFMAB
-	"vfmat",	// ARM_INS_VFMAT
-	"vbif",		// ARM_INS_VBIF
-	"vbit",		// ARM_INS_VBIT
-	"vbsl",		// ARM_INS_VBSL
-	"vceq",		// ARM_INS_VCEQ
-	"vcge",		// ARM_INS_VCGE
-	"vcgt",		// ARM_INS_VCGT
-	"vcle",		// ARM_INS_VCLE
-	"vclt",		// ARM_INS_VCLT
-	"vcmpe",	// ARM_INS_VCMPE
-	"vcnt",		// ARM_INS_VCNT
-	"vdiv",		// ARM_INS_VDIV
-	"vext",		// ARM_INS_VEXT
-	"vfmal",	// ARM_INS_VFMAL
-	"vfmsl",	// ARM_INS_VFMSL
-	"vfnma",	// ARM_INS_VFNMA
-	"vfnms",	// ARM_INS_VFNMS
-	"vins",		// ARM_INS_VINS
-	"vjcvt",	// ARM_INS_VJCVT
-	"vldmdb",	// ARM_INS_VLDMDB
-	"vldmia",	// ARM_INS_VLDMIA
-	"vldr",		// ARM_INS_VLDR
-	"vlldm",	// ARM_INS_VLLDM
-	"vlstm",	// ARM_INS_VLSTM
-	"vmlal",	// ARM_INS_VMLAL
-	"vmls",		// ARM_INS_VMLS
-	"vmlsl",	// ARM_INS_VMLSL
-	"vmmla",	// ARM_INS_VMMLA
-	"vmovx",	// ARM_INS_VMOVX
-	"vmovl",	// ARM_INS_VMOVL
-	"vmovn",	// ARM_INS_VMOVN
-	"vmsr",		// ARM_INS_VMSR
-	"vmull",	// ARM_INS_VMULL
-	"vnmla",	// ARM_INS_VNMLA
-	"vnmls",	// ARM_INS_VNMLS
-	"vnmul",	// ARM_INS_VNMUL
-	"vpadal",	// ARM_INS_VPADAL
-	"vpaddl",	// ARM_INS_VPADDL
-	"vpadd",	// ARM_INS_VPADD
-	"vpmax",	// ARM_INS_VPMAX
-	"vpmin",	// ARM_INS_VPMIN
-	"vqdmlal",	// ARM_INS_VQDMLAL
-	"vqdmlsl",	// ARM_INS_VQDMLSL
-	"vqdmull",	// ARM_INS_VQDMULL
-	"vqmovun",	// ARM_INS_VQMOVUN
-	"vqmovn",	// ARM_INS_VQMOVN
-	"vqrdmlsh",	// ARM_INS_VQRDMLSH
-	"vqrshrn",	// ARM_INS_VQRSHRN
-	"vqrshrun",	// ARM_INS_VQRSHRUN
-	"vqshrn",	// ARM_INS_VQSHRN
-	"vqshrun",	// ARM_INS_VQSHRUN
-	"vraddhn",	// ARM_INS_VRADDHN
-	"vrecpe",	// ARM_INS_VRECPE
-	"vrecps",	// ARM_INS_VRECPS
-	"vrintr",	// ARM_INS_VRINTR
-	"vrshrn",	// ARM_INS_VRSHRN
-	"vrsqrte",	// ARM_INS_VRSQRTE
-	"vrsqrts",	// ARM_INS_VRSQRTS
-	"vrsra",	// ARM_INS_VRSRA
-	"vrsubhn",	// ARM_INS_VRSUBHN
-	"vscclrm",	// ARM_INS_VSCCLRM
-	"vsdot",	// ARM_INS_VSDOT
-	"vseleq",	// ARM_INS_VSELEQ
-	"vselge",	// ARM_INS_VSELGE
-	"vselgt",	// ARM_INS_VSELGT
-	"vselvs",	// ARM_INS_VSELVS
-	"vshll",	// ARM_INS_VSHLL
-	"vshrn",	// ARM_INS_VSHRN
-	"vsmmla",	// ARM_INS_VSMMLA
-	"vsqrt",	// ARM_INS_VSQRT
-	"vsra",		// ARM_INS_VSRA
-	"vstmdb",	// ARM_INS_VSTMDB
-	"vstmia",	// ARM_INS_VSTMIA
-	"vstr",		// ARM_INS_VSTR
-	"vsubhn",	// ARM_INS_VSUBHN
-	"vsubl",	// ARM_INS_VSUBL
-	"vsubw",	// ARM_INS_VSUBW
-	"vsudot",	// ARM_INS_VSUDOT
-	"vswp",		// ARM_INS_VSWP
-	"vtbl",		// ARM_INS_VTBL
-	"vtbx",		// ARM_INS_VTBX
-	"vcvtr",	// ARM_INS_VCVTR
-	"vtrn",		// ARM_INS_VTRN
-	"vtst",		// ARM_INS_VTST
-	"vudot",	// ARM_INS_VUDOT
-	"vummla",	// ARM_INS_VUMMLA
-	"vusdot",	// ARM_INS_VUSDOT
-	"vusmmla",	// ARM_INS_VUSMMLA
-	"vuzp",		// ARM_INS_VUZP
-	"vzip",		// ARM_INS_VZIP
-	"addw",		// ARM_INS_ADDW
-	"aut",		// ARM_INS_AUT
-	"autg",		// ARM_INS_AUTG
-	"bfl",		// ARM_INS_BFL
-	"bflx",		// ARM_INS_BFLX
-	"bf",		// ARM_INS_BF
-	"bfcsel",	// ARM_INS_BFCSEL
-	"bfx",		// ARM_INS_BFX
-	"bti",		// ARM_INS_BTI
-	"bxaut",	// ARM_INS_BXAUT
-	"clrm",		// ARM_INS_CLRM
-	"csel",		// ARM_INS_CSEL
-	"csinc",	// ARM_INS_CSINC
-	"csinv",	// ARM_INS_CSINV
-	"csneg",	// ARM_INS_CSNEG
-	"dcps1",	// ARM_INS_DCPS1
-	"dcps2",	// ARM_INS_DCPS2
-	"dcps3",	// ARM_INS_DCPS3
-	"dls",		// ARM_INS_DLS
-	"le",		// ARM_INS_LE
-	"orn",		// ARM_INS_ORN
-	"pac",		// ARM_INS_PAC
-	"pacbti",	// ARM_INS_PACBTI
-	"pacg",		// ARM_INS_PACG
-	"sg",		// ARM_INS_SG
-	"subs",		// ARM_INS_SUBS
-	"subw",		// ARM_INS_SUBW
-	"tbb",		// ARM_INS_TBB
-	"tbh",		// ARM_INS_TBH
-	"tt",		// ARM_INS_TT
-	"tta",		// ARM_INS_TTA
-	"ttat",		// ARM_INS_TTAT
-	"ttt",		// ARM_INS_TTT
-	"wls",		// ARM_INS_WLS
-	"blxns",	// ARM_INS_BLXNS
-	"bxns",		// ARM_INS_BXNS
-	"cbnz",		// ARM_INS_CBNZ
-	"cbz",		// ARM_INS_CBZ
-	"pop",		// ARM_INS_POP
-	"push",		// ARM_INS_PUSH
-	"__brkdiv0",	// ARM_INS___BRKDIV0

thirdparty/capstone/arch/ARM/ARMGenCSOpGroup.inc

@@ -1,90 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
-/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
-
-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
-
-/* Do not edit. */
-
-/* Capstone's LLVM TableGen Backends: */
-/* https://github.com/capstone-engine/llvm-capstone */
-
-ARM_OP_GROUP_RegImmShift = 0,
-	ARM_OP_GROUP_LdStmModeOperand = 1,
-	ARM_OP_GROUP_MandatoryInvertedPredicateOperand = 2,
-	ARM_OP_GROUP_Operand = 3, ARM_OP_GROUP_ModImmOperand = 4,
-	ARM_OP_GROUP_PredicateOperand = 5, ARM_OP_GROUP_SORegImmOperand = 6,
-	ARM_OP_GROUP_SORegRegOperand = 7, ARM_OP_GROUP_SBitModifierOperand = 8,
-	ARM_OP_GROUP_AddrModeImm12Operand_0 = 9,
-	ARM_OP_GROUP_AddrMode2Operand = 10, ARM_OP_GROUP_CPInstOperand = 11,
-	ARM_OP_GROUP_MandatoryPredicateOperand = 12,
-	ARM_OP_GROUP_ThumbITMask = 13, ARM_OP_GROUP_RegisterList = 14,
-	ARM_OP_GROUP_AddrMode7Operand = 15, ARM_OP_GROUP_GPRPairOperand = 16,
-	ARM_OP_GROUP_AddrMode3Operand_0 = 17, ARM_OP_GROUP_PCLabel = 18,
-	ARM_OP_GROUP_AddrModePCOperand = 19,
-	ARM_OP_GROUP_AddrMode2OffsetOperand = 20,
-	ARM_OP_GROUP_AddrMode3OffsetOperand = 21,
-	ARM_OP_GROUP_AddrMode6Operand = 22,
-	ARM_OP_GROUP_VectorListThreeAllLanes = 23,
-	ARM_OP_GROUP_VectorListThreeSpacedAllLanes = 24,
-	ARM_OP_GROUP_VectorListThree = 25,
-	ARM_OP_GROUP_VectorListThreeSpaced = 26,
-	ARM_OP_GROUP_VectorListFourAllLanes = 27,
-	ARM_OP_GROUP_VectorListFourSpacedAllLanes = 28,
-	ARM_OP_GROUP_VectorListFour = 29,
-	ARM_OP_GROUP_VectorListFourSpaced = 30, ARM_OP_GROUP_T2SOOperand = 31,
-	ARM_OP_GROUP_T2AddrModeImm8OffsetOperand = 32,
-	ARM_OP_GROUP_T2AddrModeImm8Operand_1 = 33,
-	ARM_OP_GROUP_AdrLabelOperand_0 = 34, ARM_OP_GROUP_VectorIndex = 35,
-	ARM_OP_GROUP_BitfieldInvMaskImmOperand = 36,
-	ARM_OP_GROUP_PImmediate = 37, ARM_OP_GROUP_VPTPredicateOperand = 38,
-	ARM_OP_GROUP_CImmediate = 39, ARM_OP_GROUP_CPSIMod = 40,
-	ARM_OP_GROUP_CPSIFlag = 41, ARM_OP_GROUP_MemBOption = 42,
-	ARM_OP_GROUP_FPImmOperand = 43, ARM_OP_GROUP_InstSyncBOption = 44,
-	ARM_OP_GROUP_AddrMode5Operand_0 = 45, ARM_OP_GROUP_CoprocOptionImm = 46,
-	ARM_OP_GROUP_PostIdxImm8s4Operand = 47,
-	ARM_OP_GROUP_AddrMode5Operand_1 = 48,
-	ARM_OP_GROUP_AddrModeImm12Operand_1 = 49,
-	ARM_OP_GROUP_AddrMode3Operand_1 = 50,
-	ARM_OP_GROUP_PostIdxImm8Operand = 51,
-	ARM_OP_GROUP_PostIdxRegOperand = 52, ARM_OP_GROUP_BankedRegOperand = 53,
-	ARM_OP_GROUP_MSRMaskOperand = 54, ARM_OP_GROUP_MveSaturateOp = 55,
-	ARM_OP_GROUP_VMOVModImmOperand = 56,
-	ARM_OP_GROUP_ComplexRotationOp_180_90 = 57,
-	ARM_OP_GROUP_ComplexRotationOp_90_0 = 58,
-	ARM_OP_GROUP_MandatoryRestrictedPredicateOperand = 59,
-	ARM_OP_GROUP_MVEVectorList_2 = 60, ARM_OP_GROUP_MVEVectorList_4 = 61,
-	ARM_OP_GROUP_T2AddrModeImm8Operand_0 = 62,
-	ARM_OP_GROUP_MveAddrModeRQOperand_0 = 63,
-	ARM_OP_GROUP_MveAddrModeRQOperand_3 = 64,
-	ARM_OP_GROUP_MveAddrModeRQOperand_1 = 65,
-	ARM_OP_GROUP_MveAddrModeRQOperand_2 = 66, ARM_OP_GROUP_VPTMask = 67,
-	ARM_OP_GROUP_PKHLSLShiftImm = 68, ARM_OP_GROUP_PKHASRShiftImm = 69,
-	ARM_OP_GROUP_ImmPlusOneOperand = 70, ARM_OP_GROUP_SetendOperand = 71,
-	ARM_OP_GROUP_ShiftImmOperand = 72, ARM_OP_GROUP_RotImmOperand = 73,
-	ARM_OP_GROUP_TraceSyncBOption = 74,
-	ARM_OP_GROUP_VectorListOneAllLanes = 75,
-	ARM_OP_GROUP_VectorListTwoAllLanes = 76,
-	ARM_OP_GROUP_NoHashImmediate = 77,
-	ARM_OP_GROUP_AddrMode6OffsetOperand = 78,
-	ARM_OP_GROUP_VectorListOne = 79, ARM_OP_GROUP_VectorListTwo = 80,
-	ARM_OP_GROUP_VectorListTwoSpacedAllLanes = 81,
-	ARM_OP_GROUP_VectorListTwoSpaced = 82,
-	ARM_OP_GROUP_AddrMode5FP16Operand_0 = 83,
-	ARM_OP_GROUP_T2AddrModeImm8s4Operand_0 = 84,
-	ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand = 85,
-	ARM_OP_GROUP_T2AddrModeImm8s4Operand_1 = 86, ARM_OP_GROUP_FBits16 = 87,
-	ARM_OP_GROUP_FBits32 = 88, ARM_OP_GROUP_ThumbSRImm = 89,
-	ARM_OP_GROUP_ThumbLdrLabelOperand = 90,
-	ARM_OP_GROUP_T2AddrModeSoRegOperand = 91,
-	ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand = 92,
-	ARM_OP_GROUP_AddrModeTBB = 93, ARM_OP_GROUP_AddrModeTBH = 94,
-	ARM_OP_GROUP_ThumbS4ImmOperand = 95,
-	ARM_OP_GROUP_AdrLabelOperand_2 = 96,
-	ARM_OP_GROUP_ThumbAddrModeImm5S1Operand = 97,
-	ARM_OP_GROUP_ThumbAddrModeRROperand = 98,
-	ARM_OP_GROUP_ThumbAddrModeImm5S2Operand = 99,
-	ARM_OP_GROUP_ThumbAddrModeImm5S4Operand = 100,
-	ARM_OP_GROUP_ThumbAddrModeSPOperand = 101,