mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-02 15:22:06 +00:00
229 lines
5.5 KiB
YAML
229 lines
5.5 KiB
YAML
test_cases:
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-
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input:
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bytes: [ 0x80, 0xa0, 0x40, 0x02, 0x85, 0xc2, 0x60, 0x08, 0x85, 0xe8, 0x20, 0x01, 0x81, 0xe8, 0x00, 0x00, 0x90, 0x10, 0x20, 0x01, 0xd5, 0xf6, 0x10, 0x16, 0x21, 0x00, 0x00, 0x0a, 0x86, 0x00, 0x40, 0x02, 0x01, 0x00, 0x00, 0x00, 0x12, 0xbf, 0xff, 0xff, 0x10, 0xbf, 0xff, 0xff, 0xa0, 0x02, 0x00, 0x09, 0x0d, 0xbf, 0xff, 0xff, 0xd4, 0x20, 0x60, 0x00, 0xd4, 0x4e, 0x00, 0x16, 0x2a, 0xc2, 0x80, 0x03 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "cmp %g1, %g2"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: g1
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type: SPARC_OP_REG
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reg: g2
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asm_text: "jmpl %o1+8, %g2"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_MEM
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mem_base: o1
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mem_disp: 0x8
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type: SPARC_OP_REG
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reg: g2
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asm_text: "restore %g0, 1, %g2"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: g0
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type: SPARC_OP_IMM
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imm: 0x1
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type: SPARC_OP_REG
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reg: g2
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asm_text: "restore"
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asm_text: "mov 1, %o0"
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details:
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sparc:
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operands:
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type: SPARC_OP_IMM
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imm: 0x1
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type: SPARC_OP_REG
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reg: o0
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-
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asm_text: "casx [%i0], %l6, %o2"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_MEM
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mem_base: i0
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-
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type: SPARC_OP_REG
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reg: l6
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type: SPARC_OP_REG
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reg: o2
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asm_text: "sethi 0xa, %l0"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_IMM
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imm: 0xa
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type: SPARC_OP_REG
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reg: l0
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asm_text: "add %g1, %g2, %g3"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: g1
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type: SPARC_OP_REG
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reg: g2
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type: SPARC_OP_REG
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reg: g3
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asm_text: "nop"
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asm_text: "bne 0x1020"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_IMM
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imm: 0x1020
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cc: SPARC_CC_ICC_NE
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asm_text: "ba 0x1024"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_IMM
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imm: 0x1024
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asm_text: "add %o0, %o1, %l0"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: o0
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type: SPARC_OP_REG
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reg: o1
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type: SPARC_OP_REG
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reg: l0
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asm_text: "fbg 0x102c"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_IMM
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imm: 0x102c
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cc: SPARC_CC_FCC_G
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asm_text: "st %o2, [%g1]"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: o2
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type: SPARC_OP_MEM
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mem_base: g1
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asm_text: "ldsb [%i0+%l6], %o2"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_MEM
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mem_base: i0
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mem_index: l6
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type: SPARC_OP_REG
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reg: o2
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asm_text: "brnz,a,pn %o2, 0x1048"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: o2
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type: SPARC_OP_IMM
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imm: 0x1048
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hint: SPARC_HINT_A_PN
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input:
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bytes: [ 0x81, 0xa8, 0x0a, 0x24, 0x89, 0xa0, 0x10, 0x20, 0x89, 0xa0, 0x1a, 0x60, 0x89, 0xa0, 0x00, 0xe0 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "fcmps %f0, %f4"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: f0
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type: SPARC_OP_REG
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reg: f4
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asm_text: "fstox %f0, %f4"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: f0
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type: SPARC_OP_REG
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reg: f4
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asm_text: "fqtoi %f0, %f4"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: f0
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type: SPARC_OP_REG
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reg: f4
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asm_text: "fnegq %f0, %f4"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: f0
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-
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type: SPARC_OP_REG
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reg: f4
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