mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-06-11 01:55:08 +00:00
107 lines
3.6 KiB
YAML
107 lines
3.6 KiB
YAML
test_cases:
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input:
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bytes: [ 0x06, 0x20, 0x42, 0xe2, 0x06, 0x20, 0x42, 0xe2, 0x03, 0x20, 0x42, 0xe0, 0x03, 0x20, 0x42, 0xe0, 0x06, 0x20, 0x82, 0xe2, 0x06, 0x20, 0x82, 0xe2, 0x03, 0x20, 0x82, 0xe0, 0x03, 0x20, 0x82, 0xe0, 0x06, 0x20, 0x02, 0xe2, 0x06, 0x20, 0x02, 0xe2, 0x03, 0x20, 0x02, 0xe0, 0x03, 0x20, 0x02, 0xe0, 0x06, 0x20, 0x82, 0xe3, 0x06, 0x20, 0x82, 0xe3, 0x03, 0x20, 0x82, 0xe1, 0x03, 0x20, 0x82, 0xe1, 0x06, 0x20, 0x22, 0xe2, 0x06, 0x20, 0x22, 0xe2, 0x03, 0x20, 0x22, 0xe0, 0x03, 0x20, 0x22, 0xe0, 0x06, 0x20, 0xc2, 0xe3, 0x06, 0x20, 0xc2, 0xe3, 0x03, 0x20, 0xc2, 0xe1, 0x03, 0x20, 0xc2, 0xe1, 0x06, 0x20, 0x52, 0x02, 0x06, 0x20, 0x52, 0x02, 0x03, 0x20, 0x52, 0x00, 0x03, 0x20, 0x52, 0x00, 0x06, 0x20, 0x92, 0x02, 0x06, 0x20, 0x92, 0x02, 0x03, 0x20, 0x92, 0x00, 0x03, 0x20, 0x92, 0x00, 0x06, 0x20, 0x12, 0x02, 0x06, 0x20, 0x12, 0x02, 0x03, 0x20, 0x12, 0x00, 0x03, 0x20, 0x12, 0x00, 0x06, 0x20, 0x92, 0x03, 0x06, 0x20, 0x92, 0x03, 0x03, 0x20, 0x92, 0x01, 0x03, 0x20, 0x92, 0x01, 0x06, 0x20, 0x32, 0x02, 0x06, 0x20, 0x32, 0x02, 0x03, 0x20, 0x32, 0x00, 0x03, 0x20, 0x32, 0x00, 0x06, 0x20, 0xd2, 0x03, 0x06, 0x20, 0xd2, 0x03, 0x03, 0x20, 0xd2, 0x01, 0x03, 0x20, 0xd2, 0x01, 0x7b, 0x00, 0x8f, 0xe2 ]
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arch: "CS_ARCH_ARM"
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options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
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expected:
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insns:
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asm_text: "sub r2, r2, #6"
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asm_text: "sub r2, r2, #6"
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asm_text: "sub r2, r2, r3"
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asm_text: "sub r2, r2, r3"
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asm_text: "add r2, r2, #6"
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asm_text: "add r2, r2, #6"
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asm_text: "add r2, r2, r3"
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asm_text: "add r2, r2, r3"
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asm_text: "and r2, r2, #6"
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asm_text: "and r2, r2, #6"
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asm_text: "and r2, r2, r3"
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asm_text: "and r2, r2, r3"
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asm_text: "orr r2, r2, #6"
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asm_text: "orr r2, r2, #6"
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asm_text: "orr r2, r2, r3"
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asm_text: "orr r2, r2, r3"
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asm_text: "eor r2, r2, #6"
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asm_text: "eor r2, r2, #6"
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asm_text: "eor r2, r2, r3"
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asm_text: "eor r2, r2, r3"
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asm_text: "bic r2, r2, #6"
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asm_text: "bic r2, r2, #6"
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asm_text: "bic r2, r2, r3"
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asm_text: "bic r2, r2, r3"
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asm_text: "subseq r2, r2, #6"
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asm_text: "subseq r2, r2, #6"
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asm_text: "subseq r2, r2, r3"
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asm_text: "subseq r2, r2, r3"
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asm_text: "addseq r2, r2, #6"
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asm_text: "addseq r2, r2, #6"
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asm_text: "addseq r2, r2, r3"
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asm_text: "addseq r2, r2, r3"
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asm_text: "andseq r2, r2, #6"
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asm_text: "andseq r2, r2, #6"
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asm_text: "andseq r2, r2, r3"
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asm_text: "andseq r2, r2, r3"
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asm_text: "orrseq r2, r2, #6"
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asm_text: "orrseq r2, r2, #6"
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asm_text: "orrseq r2, r2, r3"
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asm_text: "orrseq r2, r2, r3"
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asm_text: "eorseq r2, r2, #6"
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asm_text: "eorseq r2, r2, #6"
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asm_text: "eorseq r2, r2, r3"
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asm_text: "eorseq r2, r2, r3"
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asm_text: "bicseq r2, r2, #6"
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asm_text: "bicseq r2, r2, #6"
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asm_text: "bicseq r2, r2, r3"
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asm_text: "bicseq r2, r2, r3"
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asm_text: "add r0, pc, #0x7b"
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